| @@ -92,7 +92,7 @@ IDCT_FUNCS(avx) · 91 unmodified lines |
| 92 | const uint8_t *vf = ff_hevc_ ## f ## _filters[my]; | 92 | const uint8_t *vf = ff_hevc_ ## f ## _filters[my]; |
| 93 | | 93 | |
| 94 | #define FW_PUT(p, a, b, depth, opt) \ | 94 | #define FW_PUT(p, a, b, depth, opt) \ |
| 95 | void ff_hevc_put_ ## a ## _ ## depth ## _##opt(int16_t *dst, const uint8_t *src, ptrdiff_t srcstride, \ | 95 | static void hevc_put_ ## a ## _ ## depth ## _##opt(int16_t *dst, const uint8_t *src, ptrdiff_t srcstride, \ |
| 96 | int height, intptr_t mx, intptr_t my,int width) \ | 96 | int height, intptr_t mx, intptr_t my,int width) \ |
| 97 | { \ | 97 | { \ |
| 98 | DECL_HV_FILTER(p) \ | 98 | DECL_HV_FILTER(p) \ |
| @@ -190,7 +190,7 @@ FW_QPEL_HV(16, 10, avx2) · 91 unmodified lines |
| 190 | #endif | 190 | #endif |
| 191 | | 191 | |
| 192 | #define mc_rep_func(name, bitd, step, W, opt) \ | 192 | #define mc_rep_func(name, bitd, step, W, opt) \ |
| 193 | void ff_hevc_put_##name##W##_##bitd##_##opt(int16_t *_dst, \ | 193 | static void hevc_put_##name##W##_##bitd##_##opt(int16_t *_dst, \ |
| 194 | const uint8_t *_src, ptrdiff_t _srcstride, int height, \ | 194 | const uint8_t *_src, ptrdiff_t _srcstride, int height, \ |
| 195 | intptr_t mx, intptr_t my, int width) \ | 195 | intptr_t mx, intptr_t my, int width) \ |
| 196 | { \ | 196 | { \ |
| @@ -199,7 +199,7 @@ void ff_hevc_put_##name##W##_##bitd##_##opt(int16_t *_dst, · 2 unmodified lines |
| 199 | for (i = 0; i < W; i += step) { \ | 199 | for (i = 0; i < W; i += step) { \ |
| 200 | const uint8_t *src = _src + (i * ((bitd + 7) / 8)); \ | 200 | const uint8_t *src = _src + (i * ((bitd + 7) / 8)); \ |
| 201 | dst = _dst + i; \ | 201 | dst = _dst + i; \ |
| 202 | ff_hevc_put_##name##step##_##bitd##_##opt(dst, src, _srcstride, height, mx, my, width); \ | 202 | hevc_put_##name##step##_##bitd##_##opt(dst, src, _srcstride, height, mx, my, width); \ |
| 203 | } \ | 203 | } \ |
| 204 | } | 204 | } |
| 205 | #define mc_rep_uni_func(name, bitd, step, W, opt) \ | 205 | #define mc_rep_uni_func(name, bitd, step, W, opt) \ |
| @@ -238,13 +238,13 @@ void ff_hevc_put_bi_##name##W##_##bitd##_##opt(uint8_t *_dst, ptrdiff_t dststrid · 32 unmodified lines |
| 238 | mc_rep_bi_func(name, bitd, step, W, opt) | 238 | mc_rep_bi_func(name, bitd, step, W, opt) |
| 239 | | 239 | |
| 240 | #define mc_rep_func2(name, bitd, step1, step2, W, opt) \ | 240 | #define mc_rep_func2(name, bitd, step1, step2, W, opt) \ |
| 241 | void ff_hevc_put_##name##W##_##bitd##_##opt(int16_t *dst, \ | 241 | static void hevc_put_##name##W##_##bitd##_##opt(int16_t *dst, \ |
| 242 | const uint8_t *src, ptrdiff_t _srcstride, int height, \ | 242 | const uint8_t *src, ptrdiff_t _srcstride, int height, \ |
| 243 | intptr_t mx, intptr_t my, int width) \ | 243 | intptr_t mx, intptr_t my, int width) \ |
| 244 | { \ | 244 | { \ |
| 245 | ff_hevc_put_##name##step1##_##bitd##_##opt(dst, src, _srcstride, height, mx, my, width); \ | 245 | hevc_put_##name##step1##_##bitd##_##opt(dst, src, _srcstride, height, mx, my, width); \ |
| 246 | ff_hevc_put_##name##step2##_##bitd##_##opt(dst + step1, src + (step1 * ((bitd + 7) / 8)), \ | 246 | hevc_put_##name##step2##_##bitd##_##opt(dst + step1, src + (step1 * ((bitd + 7) / 8)), \ |
| 247 | _srcstride, height, mx, my, width); \ | 247 | _srcstride, height, mx, my, width); \ |
| 248 | } | 248 | } |
| 249 | #define mc_rep_uni_func2(name, bitd, step1, step2, W, opt) \ | 249 | #define mc_rep_uni_func2(name, bitd, step1, step2, W, opt) \ |
| 250 | static void hevc_put_uni_##name##W##_##bitd##_##opt(uint8_t *dst, ptrdiff_t dststride, \ | 250 | static void hevc_put_uni_##name##W##_##bitd##_##opt(uint8_t *dst, ptrdiff_t dststride, \ |
| @@ -275,12 +275,12 @@ void ff_hevc_put_bi_##name##W##_##bitd##_##opt(uint8_t *dst, ptrdiff_t dststride · 24 unmodified lines |
| 275 | #if ARCH_X86_64 && HAVE_SSE4_EXTERNAL | 275 | #if ARCH_X86_64 && HAVE_SSE4_EXTERNAL |
| 276 | | 276 | |
| 277 | #define mc_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) \ | 277 | #define mc_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) \ |
| 278 | void ff_hevc_put_##name##width1##_10_##opt1(int16_t *dst, const uint8_t *src, ptrdiff_t _srcstride, \ | 278 | static void hevc_put_##name##width1##_10_##opt1(int16_t *dst, const uint8_t *src, ptrdiff_t _srcstride, \ |
| 279 | int height, intptr_t mx, intptr_t my, int width) \ | 279 | int height, intptr_t mx, intptr_t my, int width) \ |
| 280 | \ | 280 | \ |
| 281 | { \ | 281 | { \ |
| 282 | ff_hevc_put_##name##width2##_10_##opt1(dst, src, _srcstride, height, mx, my, width); \ | 282 | hevc_put_##name##width2##_10_##opt1(dst, src, _srcstride, height, mx, my, width); \ |
| 283 | ff_hevc_put_##name##width3##_10_##opt2(dst+ width2, src+ width4, _srcstride, height, mx, my, width); \ | 283 | hevc_put_##name##width3##_10_##opt2(dst+ width2, src+ width4, _srcstride, height, mx, my, width); \ |
| 284 | } | 284 | } |
| 285 | | 285 | |
| 286 | #define mc_bi_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) \ | 286 | #define mc_bi_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) \ |
| @@ -311,12 +311,12 @@ mc_bi_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) \ · 24 unmodified lines |
| 311 | mc_uni_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) | 311 | mc_uni_rep_mix_10(name, width1, width2, width3, opt1, opt2, width4) |
| 312 | | 312 | |
| 313 | #define mc_rep_mix_8(name, width1, width2, width3, opt1, opt2) \ | 313 | #define mc_rep_mix_8(name, width1, width2, width3, opt1, opt2) \ |
| 314 | void ff_hevc_put_##name##width1##_8_##opt1(int16_t *dst, const uint8_t *src, ptrdiff_t _srcstride, \ | 314 | static void hevc_put_##name##width1##_8_##opt1(int16_t *dst, const uint8_t *src, ptrdiff_t _srcstride, \ |
| 315 | int height, intptr_t mx, intptr_t my, int width) \ | 315 | int height, intptr_t mx, intptr_t my, int width) \ |
| 316 | \ | 316 | \ |
| 317 | { \ | 317 | { \ |
| 318 | ff_hevc_put_##name##width2##_8_##opt1(dst, src, _srcstride, height, mx, my, width); \ | 318 | hevc_put_##name##width2##_8_##opt1(dst, src, _srcstride, height, mx, my, width); \ |
| 319 | ff_hevc_put_##name##width3##_8_##opt2(dst+ width2, src+ width2, _srcstride, height, mx, my, width); \ | 319 | hevc_put_##name##width3##_8_##opt2(dst+ width2, src+ width2, _srcstride, height, mx, my, width); \ |
| 320 | } | 320 | } |
| 321 | | 321 | |
| 322 | #define mc_bi_rep_mix_8(name, width1, width2, width3, opt1, opt2) \ | 322 | #define mc_bi_rep_mix_8(name, width1, width2, width3, opt1, opt2) \ |
| @@ -615,7 +615,7 @@ static void hevc_put_uni_w_##name##W##_##bitd##_##opt(uint8_t *_dst, ptrdiff_t _ · 292 unmodified lines |
| 615 | intptr_t mx, intptr_t my, int width) \ | 615 | intptr_t mx, intptr_t my, int width) \ |
| 616 | { \ | 616 | { \ |
| 617 | LOCAL_ALIGNED_16(int16_t, temp, [71 * MAX_PB_SIZE]); \ | 617 | LOCAL_ALIGNED_16(int16_t, temp, [71 * MAX_PB_SIZE]); \ |
| 618 | ff_hevc_put_##name##W##_##bitd##_##opt(temp, _src, _srcstride, height, mx, my, width); \ | 618 | hevc_put_##name##W##_##bitd##_##opt(temp, _src, _srcstride, height, mx, my, width); \ |
| 619 | ff_hevc_put_uni_w##W##_##bitd##_##opt(_dst, _dststride, temp, height, denom, _wx, _ox); \ | 619 | ff_hevc_put_uni_w##W##_##bitd##_##opt(_dst, _dststride, temp, height, denom, _wx, _ox); \ |
| 620 | } | 620 | } |
| 621 | | 621 | |
| @@ -674,7 +674,7 @@ static void hevc_put_bi_w_##name##W##_##bitd##_##opt(uint8_t *_dst, ptrdiff_t _d · 52 unmodified lines |
| 674 | intptr_t mx, intptr_t my, int width) \ | 674 | intptr_t mx, intptr_t my, int width) \ |
| 675 | { \ | 675 | { \ |
| 676 | LOCAL_ALIGNED_16(int16_t, temp, [71 * MAX_PB_SIZE]); \ | 676 | LOCAL_ALIGNED_16(int16_t, temp, [71 * MAX_PB_SIZE]); \ |
| 677 | ff_hevc_put_##name##W##_##bitd##_##opt(temp, _src, _srcstride, height, mx, my, width); \ | 677 | hevc_put_##name##W##_##bitd##_##opt(temp, _src, _srcstride, height, mx, my, width); \ |
| 678 | ff_hevc_put_bi_w##W##_##bitd##_##opt(_dst, _dststride, temp, _src2, \ | 678 | ff_hevc_put_bi_w##W##_##bitd##_##opt(_dst, _dststride, temp, _src2, \ |
| 679 | height, denom, _wx0, _wx1, _ox0, _ox1); \ | 679 | height, denom, _wx0, _wx1, _ox0, _ox1); \ |
| 680 | } | 680 | } |
| @@ -886,13 +886,13 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 205 unmodified lines |
| 886 | c->idct_dc[3] = ff_hevc_idct_32x32_dc_8_avx2; | 886 | c->idct_dc[3] = ff_hevc_idct_32x32_dc_8_avx2; |
| 887 | | 887 | |
| 888 | #if ARCH_X86_64 | 888 | #if ARCH_X86_64 |
| 889 | c->put_hevc_epel[7][0][0] = ff_hevc_put_pel_pixels32_8_avx2; | 889 | c->put_hevc_epel[7][0][0] = hevc_put_pel_pixels32_8_avx2; |
| 890 | c->put_hevc_epel[8][0][0] = ff_hevc_put_pel_pixels48_8_avx2; | 890 | c->put_hevc_epel[8][0][0] = hevc_put_pel_pixels48_8_avx2; |
| 891 | c->put_hevc_epel[9][0][0] = ff_hevc_put_pel_pixels64_8_avx2; | 891 | c->put_hevc_epel[9][0][0] = hevc_put_pel_pixels64_8_avx2; |
| 892 | | 892 | |
| 893 | c->put_hevc_qpel[7][0][0] = ff_hevc_put_pel_pixels32_8_avx2; | 893 | c->put_hevc_qpel[7][0][0] = hevc_put_pel_pixels32_8_avx2; |
| 894 | c->put_hevc_qpel[8][0][0] = ff_hevc_put_pel_pixels48_8_avx2; | 894 | c->put_hevc_qpel[8][0][0] = hevc_put_pel_pixels48_8_avx2; |
| 895 | c->put_hevc_qpel[9][0][0] = ff_hevc_put_pel_pixels64_8_avx2; | 895 | c->put_hevc_qpel[9][0][0] = hevc_put_pel_pixels64_8_avx2; |
| 896 | | 896 | |
| 897 | c->put_hevc_epel_uni[7][0][0] = hevc_put_uni_pel_pixels32_8_avx2; | 897 | c->put_hevc_epel_uni[7][0][0] = hevc_put_uni_pel_pixels32_8_avx2; |
| 898 | c->put_hevc_epel_uni[8][0][0] = hevc_put_uni_pel_pixels48_8_avx2; | 898 | c->put_hevc_epel_uni[8][0][0] = hevc_put_uni_pel_pixels48_8_avx2; |
| @@ -910,9 +910,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 11 unmodified lines |
| 910 | c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; | 910 | c->put_hevc_epel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_8_avx2; |
| 911 | c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; | 911 | c->put_hevc_epel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_8_avx2; |
| 912 | | 912 | |
| 913 | c->put_hevc_epel[7][0][1] = ff_hevc_put_epel_h32_8_avx2; | 913 | c->put_hevc_epel[7][0][1] = hevc_put_epel_h32_8_avx2; |
| 914 | c->put_hevc_epel[8][0][1] = ff_hevc_put_epel_h48_8_avx2; | 914 | c->put_hevc_epel[8][0][1] = hevc_put_epel_h48_8_avx2; |
| 915 | c->put_hevc_epel[9][0][1] = ff_hevc_put_epel_h64_8_avx2; | 915 | c->put_hevc_epel[9][0][1] = hevc_put_epel_h64_8_avx2; |
| 916 | | 916 | |
| 917 | c->put_hevc_epel_uni[7][0][1] = hevc_put_uni_epel_h32_8_avx2; | 917 | c->put_hevc_epel_uni[7][0][1] = hevc_put_uni_epel_h32_8_avx2; |
| 918 | c->put_hevc_epel_uni[8][0][1] = hevc_put_uni_epel_h48_8_avx2; | 918 | c->put_hevc_epel_uni[8][0][1] = hevc_put_uni_epel_h48_8_avx2; |
| @@ -922,9 +922,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines |
| 922 | c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_8_avx2; | 922 | c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_8_avx2; |
| 923 | c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_8_avx2; | 923 | c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_8_avx2; |
| 924 | | 924 | |
| 925 | c->put_hevc_epel[7][1][0] = ff_hevc_put_epel_v32_8_avx2; | 925 | c->put_hevc_epel[7][1][0] = hevc_put_epel_v32_8_avx2; |
| 926 | c->put_hevc_epel[8][1][0] = ff_hevc_put_epel_v48_8_avx2; | 926 | c->put_hevc_epel[8][1][0] = hevc_put_epel_v48_8_avx2; |
| 927 | c->put_hevc_epel[9][1][0] = ff_hevc_put_epel_v64_8_avx2; | 927 | c->put_hevc_epel[9][1][0] = hevc_put_epel_v64_8_avx2; |
| 928 | | 928 | |
| 929 | c->put_hevc_epel_uni[7][1][0] = hevc_put_uni_epel_v32_8_avx2; | 929 | c->put_hevc_epel_uni[7][1][0] = hevc_put_uni_epel_v32_8_avx2; |
| 930 | c->put_hevc_epel_uni[8][1][0] = hevc_put_uni_epel_v48_8_avx2; | 930 | c->put_hevc_epel_uni[8][1][0] = hevc_put_uni_epel_v48_8_avx2; |
| @@ -934,9 +934,9 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines |
| 934 | c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_8_avx2; | 934 | c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_8_avx2; |
| 935 | c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_8_avx2; | 935 | c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_8_avx2; |
| 936 | | 936 | |
| 937 | c->put_hevc_epel[7][1][1] = ff_hevc_put_epel_hv32_8_avx2; | 937 | c->put_hevc_epel[7][1][1] = hevc_put_epel_hv32_8_avx2; |
| 938 | c->put_hevc_epel[8][1][1] = ff_hevc_put_epel_hv48_8_avx2; | 938 | c->put_hevc_epel[8][1][1] = hevc_put_epel_hv48_8_avx2; |
| 939 | c->put_hevc_epel[9][1][1] = ff_hevc_put_epel_hv64_8_avx2; | 939 | c->put_hevc_epel[9][1][1] = hevc_put_epel_hv64_8_avx2; |
| 940 | | 940 | |
| 941 | c->put_hevc_epel_uni[7][1][1] = hevc_put_uni_epel_hv32_8_avx2; | 941 | c->put_hevc_epel_uni[7][1][1] = hevc_put_uni_epel_hv32_8_avx2; |
| 942 | c->put_hevc_epel_uni[8][1][1] = hevc_put_uni_epel_hv48_8_avx2; | 942 | c->put_hevc_epel_uni[8][1][1] = hevc_put_uni_epel_hv48_8_avx2; |
| @@ -946,13 +946,13 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 3 unmodified lines |
| 946 | c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_8_avx2; | 946 | c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_8_avx2; |
| 947 | c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_8_avx2; | 947 | c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_8_avx2; |
| 948 | | 948 | |
| 949 | c->put_hevc_qpel[7][0][1] = ff_hevc_put_qpel_h32_8_avx2; | 949 | c->put_hevc_qpel[7][0][1] = hevc_put_qpel_h32_8_avx2; |
| 950 | c->put_hevc_qpel[8][0][1] = ff_hevc_put_qpel_h48_8_avx2; | 950 | c->put_hevc_qpel[8][0][1] = hevc_put_qpel_h48_8_avx2; |
| 951 | c->put_hevc_qpel[9][0][1] = ff_hevc_put_qpel_h64_8_avx2; | 951 | c->put_hevc_qpel[9][0][1] = hevc_put_qpel_h64_8_avx2; |
| 952 | | 952 | |
| 953 | c->put_hevc_qpel[7][1][0] = ff_hevc_put_qpel_v32_8_avx2; | 953 | c->put_hevc_qpel[7][1][0] = hevc_put_qpel_v32_8_avx2; |
| 954 | c->put_hevc_qpel[8][1][0] = ff_hevc_put_qpel_v48_8_avx2; | 954 | c->put_hevc_qpel[8][1][0] = hevc_put_qpel_v48_8_avx2; |
| 955 | c->put_hevc_qpel[9][1][0] = ff_hevc_put_qpel_v64_8_avx2; | 955 | c->put_hevc_qpel[9][1][0] = hevc_put_qpel_v64_8_avx2; |
| 956 | | 956 | |
| 957 | c->put_hevc_qpel_uni[7][0][1] = hevc_put_uni_qpel_h32_8_avx2; | 957 | c->put_hevc_qpel_uni[7][0][1] = hevc_put_uni_qpel_h32_8_avx2; |
| 958 | c->put_hevc_qpel_uni[8][0][1] = hevc_put_uni_qpel_h48_8_avx2; | 958 | c->put_hevc_qpel_uni[8][0][1] = hevc_put_uni_qpel_h48_8_avx2; |
| @@ -1059,17 +1059,17 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 100 unmodified lines |
| 1059 | c->idct_dc[3] = ff_hevc_idct_32x32_dc_10_avx2; | 1059 | c->idct_dc[3] = ff_hevc_idct_32x32_dc_10_avx2; |
| 1060 | | 1060 | |
| 1061 | #if ARCH_X86_64 | 1061 | #if ARCH_X86_64 |
| 1062 | c->put_hevc_epel[5][0][0] = ff_hevc_put_pel_pixels16_10_avx2; | 1062 | c->put_hevc_epel[5][0][0] = hevc_put_pel_pixels16_10_avx2; |
| 1063 | c->put_hevc_epel[6][0][0] = ff_hevc_put_pel_pixels24_10_avx2; | 1063 | c->put_hevc_epel[6][0][0] = hevc_put_pel_pixels24_10_avx2; |
| 1064 | c->put_hevc_epel[7][0][0] = ff_hevc_put_pel_pixels32_10_avx2; | 1064 | c->put_hevc_epel[7][0][0] = hevc_put_pel_pixels32_10_avx2; |
| 1065 | c->put_hevc_epel[8][0][0] = ff_hevc_put_pel_pixels48_10_avx2; | 1065 | c->put_hevc_epel[8][0][0] = hevc_put_pel_pixels48_10_avx2; |
| 1066 | c->put_hevc_epel[9][0][0] = ff_hevc_put_pel_pixels64_10_avx2; | 1066 | c->put_hevc_epel[9][0][0] = hevc_put_pel_pixels64_10_avx2; |
| 1067 | | 1067 | |
| 1068 | c->put_hevc_qpel[5][0][0] = ff_hevc_put_pel_pixels16_10_avx2; | 1068 | c->put_hevc_qpel[5][0][0] = hevc_put_pel_pixels16_10_avx2; |
| 1069 | c->put_hevc_qpel[6][0][0] = ff_hevc_put_pel_pixels24_10_avx2; | 1069 | c->put_hevc_qpel[6][0][0] = hevc_put_pel_pixels24_10_avx2; |
| 1070 | c->put_hevc_qpel[7][0][0] = ff_hevc_put_pel_pixels32_10_avx2; | 1070 | c->put_hevc_qpel[7][0][0] = hevc_put_pel_pixels32_10_avx2; |
| 1071 | c->put_hevc_qpel[8][0][0] = ff_hevc_put_pel_pixels48_10_avx2; | 1071 | c->put_hevc_qpel[8][0][0] = hevc_put_pel_pixels48_10_avx2; |
| 1072 | c->put_hevc_qpel[9][0][0] = ff_hevc_put_pel_pixels64_10_avx2; | 1072 | c->put_hevc_qpel[9][0][0] = hevc_put_pel_pixels64_10_avx2; |
| 1073 | | 1073 | |
| 1074 | c->put_hevc_epel_uni[5][0][0] = hevc_put_uni_pel_pixels32_8_avx2; | 1074 | c->put_hevc_epel_uni[5][0][0] = hevc_put_uni_pel_pixels32_8_avx2; |
| 1075 | c->put_hevc_epel_uni[6][0][0] = hevc_put_uni_pel_pixels48_8_avx2; | 1075 | c->put_hevc_epel_uni[6][0][0] = hevc_put_uni_pel_pixels48_8_avx2; |
| @@ -1094,11 +1094,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 18 unmodified lines |
| 1094 | c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; | 1094 | c->put_hevc_qpel_bi[8][0][0] = ff_hevc_put_bi_pel_pixels48_10_avx2; |
| 1095 | c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; | 1095 | c->put_hevc_qpel_bi[9][0][0] = ff_hevc_put_bi_pel_pixels64_10_avx2; |
| 1096 | | 1096 | |
| 1097 | c->put_hevc_epel[5][0][1] = ff_hevc_put_epel_h16_10_avx2; | 1097 | c->put_hevc_epel[5][0][1] = hevc_put_epel_h16_10_avx2; |
| 1098 | c->put_hevc_epel[6][0][1] = ff_hevc_put_epel_h24_10_avx2; | 1098 | c->put_hevc_epel[6][0][1] = hevc_put_epel_h24_10_avx2; |
| 1099 | c->put_hevc_epel[7][0][1] = ff_hevc_put_epel_h32_10_avx2; | 1099 | c->put_hevc_epel[7][0][1] = hevc_put_epel_h32_10_avx2; |
| 1100 | c->put_hevc_epel[8][0][1] = ff_hevc_put_epel_h48_10_avx2; | 1100 | c->put_hevc_epel[8][0][1] = hevc_put_epel_h48_10_avx2; |
| 1101 | c->put_hevc_epel[9][0][1] = ff_hevc_put_epel_h64_10_avx2; | 1101 | c->put_hevc_epel[9][0][1] = hevc_put_epel_h64_10_avx2; |
| 1102 | | 1102 | |
| 1103 | c->put_hevc_epel_uni[5][0][1] = hevc_put_uni_epel_h16_10_avx2; | 1103 | c->put_hevc_epel_uni[5][0][1] = hevc_put_uni_epel_h16_10_avx2; |
| 1104 | c->put_hevc_epel_uni[6][0][1] = hevc_put_uni_epel_h24_10_avx2; | 1104 | c->put_hevc_epel_uni[6][0][1] = hevc_put_uni_epel_h24_10_avx2; |
| @@ -1112,11 +1112,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines |
| 1112 | c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_10_avx2; | 1112 | c->put_hevc_epel_bi[8][0][1] = ff_hevc_put_bi_epel_h48_10_avx2; |
| 1113 | c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_10_avx2; | 1113 | c->put_hevc_epel_bi[9][0][1] = ff_hevc_put_bi_epel_h64_10_avx2; |
| 1114 | | 1114 | |
| 1115 | c->put_hevc_epel[5][1][0] = ff_hevc_put_epel_v16_10_avx2; | 1115 | c->put_hevc_epel[5][1][0] = hevc_put_epel_v16_10_avx2; |
| 1116 | c->put_hevc_epel[6][1][0] = ff_hevc_put_epel_v24_10_avx2; | 1116 | c->put_hevc_epel[6][1][0] = hevc_put_epel_v24_10_avx2; |
| 1117 | c->put_hevc_epel[7][1][0] = ff_hevc_put_epel_v32_10_avx2; | 1117 | c->put_hevc_epel[7][1][0] = hevc_put_epel_v32_10_avx2; |
| 1118 | c->put_hevc_epel[8][1][0] = ff_hevc_put_epel_v48_10_avx2; | 1118 | c->put_hevc_epel[8][1][0] = hevc_put_epel_v48_10_avx2; |
| 1119 | c->put_hevc_epel[9][1][0] = ff_hevc_put_epel_v64_10_avx2; | 1119 | c->put_hevc_epel[9][1][0] = hevc_put_epel_v64_10_avx2; |
| 1120 | | 1120 | |
| 1121 | c->put_hevc_epel_uni[5][1][0] = hevc_put_uni_epel_v16_10_avx2; | 1121 | c->put_hevc_epel_uni[5][1][0] = hevc_put_uni_epel_v16_10_avx2; |
| 1122 | c->put_hevc_epel_uni[6][1][0] = hevc_put_uni_epel_v24_10_avx2; | 1122 | c->put_hevc_epel_uni[6][1][0] = hevc_put_uni_epel_v24_10_avx2; |
| @@ -1130,11 +1130,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines |
| 1130 | c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_10_avx2; | 1130 | c->put_hevc_epel_bi[8][1][0] = ff_hevc_put_bi_epel_v48_10_avx2; |
| 1131 | c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_10_avx2; | 1131 | c->put_hevc_epel_bi[9][1][0] = ff_hevc_put_bi_epel_v64_10_avx2; |
| 1132 | | 1132 | |
| 1133 | c->put_hevc_epel[5][1][1] = ff_hevc_put_epel_hv16_10_avx2; | 1133 | c->put_hevc_epel[5][1][1] = hevc_put_epel_hv16_10_avx2; |
| 1134 | c->put_hevc_epel[6][1][1] = ff_hevc_put_epel_hv24_10_avx2; | 1134 | c->put_hevc_epel[6][1][1] = hevc_put_epel_hv24_10_avx2; |
| 1135 | c->put_hevc_epel[7][1][1] = ff_hevc_put_epel_hv32_10_avx2; | 1135 | c->put_hevc_epel[7][1][1] = hevc_put_epel_hv32_10_avx2; |
| 1136 | c->put_hevc_epel[8][1][1] = ff_hevc_put_epel_hv48_10_avx2; | 1136 | c->put_hevc_epel[8][1][1] = hevc_put_epel_hv48_10_avx2; |
| 1137 | c->put_hevc_epel[9][1][1] = ff_hevc_put_epel_hv64_10_avx2; | 1137 | c->put_hevc_epel[9][1][1] = hevc_put_epel_hv64_10_avx2; |
| 1138 | | 1138 | |
| 1139 | c->put_hevc_epel_uni[5][1][1] = hevc_put_uni_epel_hv16_10_avx2; | 1139 | c->put_hevc_epel_uni[5][1][1] = hevc_put_uni_epel_hv16_10_avx2; |
| 1140 | c->put_hevc_epel_uni[6][1][1] = hevc_put_uni_epel_hv24_10_avx2; | 1140 | c->put_hevc_epel_uni[6][1][1] = hevc_put_uni_epel_hv24_10_avx2; |
| @@ -1148,11 +1148,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines |
| 1148 | c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_10_avx2; | 1148 | c->put_hevc_epel_bi[8][1][1] = ff_hevc_put_bi_epel_hv48_10_avx2; |
| 1149 | c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_10_avx2; | 1149 | c->put_hevc_epel_bi[9][1][1] = ff_hevc_put_bi_epel_hv64_10_avx2; |
| 1150 | | 1150 | |
| 1151 | c->put_hevc_qpel[5][0][1] = ff_hevc_put_qpel_h16_10_avx2; | 1151 | c->put_hevc_qpel[5][0][1] = hevc_put_qpel_h16_10_avx2; |
| 1152 | c->put_hevc_qpel[6][0][1] = ff_hevc_put_qpel_h24_10_avx2; | 1152 | c->put_hevc_qpel[6][0][1] = hevc_put_qpel_h24_10_avx2; |
| 1153 | c->put_hevc_qpel[7][0][1] = ff_hevc_put_qpel_h32_10_avx2; | 1153 | c->put_hevc_qpel[7][0][1] = hevc_put_qpel_h32_10_avx2; |
| 1154 | c->put_hevc_qpel[8][0][1] = ff_hevc_put_qpel_h48_10_avx2; | 1154 | c->put_hevc_qpel[8][0][1] = hevc_put_qpel_h48_10_avx2; |
| 1155 | c->put_hevc_qpel[9][0][1] = ff_hevc_put_qpel_h64_10_avx2; | 1155 | c->put_hevc_qpel[9][0][1] = hevc_put_qpel_h64_10_avx2; |
| 1156 | | 1156 | |
| 1157 | c->put_hevc_qpel_uni[5][0][1] = hevc_put_uni_qpel_h16_10_avx2; | 1157 | c->put_hevc_qpel_uni[5][0][1] = hevc_put_uni_qpel_h16_10_avx2; |
| 1158 | c->put_hevc_qpel_uni[6][0][1] = hevc_put_uni_qpel_h24_10_avx2; | 1158 | c->put_hevc_qpel_uni[6][0][1] = hevc_put_uni_qpel_h24_10_avx2; |
| @@ -1166,11 +1166,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines |
| 1166 | c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_10_avx2; | 1166 | c->put_hevc_qpel_bi[8][0][1] = ff_hevc_put_bi_qpel_h48_10_avx2; |
| 1167 | c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_10_avx2; | 1167 | c->put_hevc_qpel_bi[9][0][1] = ff_hevc_put_bi_qpel_h64_10_avx2; |
| 1168 | | 1168 | |
| 1169 | c->put_hevc_qpel[5][1][0] = ff_hevc_put_qpel_v16_10_avx2; | 1169 | c->put_hevc_qpel[5][1][0] = hevc_put_qpel_v16_10_avx2; |
| 1170 | c->put_hevc_qpel[6][1][0] = ff_hevc_put_qpel_v24_10_avx2; | 1170 | c->put_hevc_qpel[6][1][0] = hevc_put_qpel_v24_10_avx2; |
| 1171 | c->put_hevc_qpel[7][1][0] = ff_hevc_put_qpel_v32_10_avx2; | 1171 | c->put_hevc_qpel[7][1][0] = hevc_put_qpel_v32_10_avx2; |
| 1172 | c->put_hevc_qpel[8][1][0] = ff_hevc_put_qpel_v48_10_avx2; | 1172 | c->put_hevc_qpel[8][1][0] = hevc_put_qpel_v48_10_avx2; |
| 1173 | c->put_hevc_qpel[9][1][0] = ff_hevc_put_qpel_v64_10_avx2; | 1173 | c->put_hevc_qpel[9][1][0] = hevc_put_qpel_v64_10_avx2; |
| 1174 | | 1174 | |
| 1175 | c->put_hevc_qpel_uni[5][1][0] = hevc_put_uni_qpel_v16_10_avx2; | 1175 | c->put_hevc_qpel_uni[5][1][0] = hevc_put_uni_qpel_v16_10_avx2; |
| 1176 | c->put_hevc_qpel_uni[6][1][0] = hevc_put_uni_qpel_v24_10_avx2; | 1176 | c->put_hevc_qpel_uni[6][1][0] = hevc_put_uni_qpel_v24_10_avx2; |
| @@ -1184,11 +1184,11 @@ void ff_hevc_dsp_init_x86(HEVCDSPContext *c, const int bit_depth) · 7 unmodified lines |
| 1184 | c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_10_avx2; | 1184 | c->put_hevc_qpel_bi[8][1][0] = ff_hevc_put_bi_qpel_v48_10_avx2; |
| 1185 | c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_10_avx2; | 1185 | c->put_hevc_qpel_bi[9][1][0] = ff_hevc_put_bi_qpel_v64_10_avx2; |
| 1186 | | 1186 | |
| 1187 | c->put_hevc_qpel[5][1][1] = ff_hevc_put_qpel_hv16_10_avx2; | 1187 | c->put_hevc_qpel[5][1][1] = hevc_put_qpel_hv16_10_avx2; |
| 1188 | c->put_hevc_qpel[6][1][1] = ff_hevc_put_qpel_hv24_10_avx2; | 1188 | c->put_hevc_qpel[6][1][1] = hevc_put_qpel_hv24_10_avx2; |
| 1189 | c->put_hevc_qpel[7][1][1] = ff_hevc_put_qpel_hv32_10_avx2; | 1189 | c->put_hevc_qpel[7][1][1] = hevc_put_qpel_hv32_10_avx2; |
| 1190 | c->put_hevc_qpel[8][1][1] = ff_hevc_put_qpel_hv48_10_avx2; | 1190 | c->put_hevc_qpel[8][1][1] = hevc_put_qpel_hv48_10_avx2; |
| 1191 | c->put_hevc_qpel[9][1][1] = ff_hevc_put_qpel_hv64_10_avx2; | 1191 | c->put_hevc_qpel[9][1][1] = hevc_put_qpel_hv64_10_avx2; |
| 1192 | | 1192 | |
| 1193 | c->put_hevc_qpel_uni[5][1][1] = hevc_put_uni_qpel_hv16_10_avx2; | 1193 | c->put_hevc_qpel_uni[5][1][1] = hevc_put_uni_qpel_hv16_10_avx2; |
| 1194 | c->put_hevc_qpel_uni[6][1][1] = hevc_put_uni_qpel_hv24_10_avx2; | 1194 | c->put_hevc_qpel_uni[6][1][1] = hevc_put_uni_qpel_hv24_10_avx2; |