While narrowing clip is nominally a rounding operation, the rounding mode has no arithmetic consequence if the right shift is by zero bits.
Unified · Split
| @@ -31,14 +31,13 @@ func ff_h263_h_loop_filter_rvv, zve32x · 30 unmodified lines | |||
| 31 | vssseg4e8.v v8, (a0), a1 | 31 | vssseg4e8.v v8, (a0), a1 |
| 32 | ret | 32 | ret |
| 33 | 1: | 33 | 1: |
| 34 | csrwi vxrm, 0 | 34 | auipc t1, %pcrel_hi(ff_h263_loop_filter_strength) |
| 35 | 2: auipc t1, %pcrel_hi(ff_h263_loop_filter_strength) | ||
| 36 | vwsubu.vv v14, v10, v9 # p2 - p1 | 35 | vwsubu.vv v14, v10, v9 # p2 - p1 |
| 37 | add t1, t1, a2 | 36 | add t1, t1, a2 |
| 38 | vwsubu.vv v12, v8, v11 # p0 - p3 | 37 | vwsubu.vv v12, v8, v11 # p0 - p3 |
| 39 | vsetvli zero, zero, e16, m1, ta, mu | 38 | vsetvli zero, zero, e16, m1, ta, mu |
| 40 | vsll.vi v14, v14, 2 | 39 | vsll.vi v14, v14, 2 |
| 41 | lbu t1, %pcrel_lo(2b)(t1) # strength | 40 | lbu t1, %pcrel_lo(1b)(t1) # strength |
| 42 | vadd.vv v16, v12, v14 | 41 | vadd.vv v16, v12, v14 |
| 43 | # Divide by 8 toward 0. v16 is a signed 10-bit value at this point. | 42 | # Divide by 8 toward 0. v16 is a signed 10-bit value at this point. |
| 44 | vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0 | 43 | vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0 |
| @@ -169,7 +169,6 @@ endfunc · 168 unmodified lines | |||
| 169 | 169 | ||
| 170 | # a3 = DC | 170 | # a3 = DC |
| 171 | func ff_vp78_idct_dc_add_rvv, zve32x | 171 | func ff_vp78_idct_dc_add_rvv, zve32x |
| 172 | csrwi vxrm, 0 | ||
| 173 | vsetivli zero, 4, e8, mf4, ta, ma | 172 | vsetivli zero, 4, e8, mf4, ta, ma |
| 174 | sh zero, (a1) | 173 | sh zero, (a1) |
| 175 | vlse32.v v8, (a0), a2 | 174 | vlse32.v v8, (a0), a2 |