dmvr_hv_8_12x20_c: 8.0 ( 1.00x) dmvr_hv_8_12x20_neon: 1.2 ( 6.62x) dmvr_hv_8_20x12_c: 8.0 ( 1.00x) dmvr_hv_8_20x12_neon: 0.9 ( 8.37x) dmvr_hv_8_20x20_c: 12.9 ( 1.00x) dmvr_hv_8_20x20_neon: 1.7 ( 7.62x) dmvr_hv_10_12x20_c: 7.0 ( 1.00x) dmvr_hv_10_12x20_neon: 1.7 ( 4.09x) dmvr_hv_10_20x12_c: 7.0 ( 1.00x) dmvr_hv_10_20x12_neon: 1.7 ( 4.09x) dmvr_hv_10_20x20_c: 11.2 ( 1.00x) dmvr_hv_10_20x20_neon: 2.7 ( 4.15x) dmvr_hv_12_12x20_c: 6.5 ( 1.00x) dmvr_hv_12_12x20_neon: 1.7 ( 3.79x) dmvr_hv_12_20x12_c: 6.5 ( 1.00x) dmvr_hv_12_20x12_neon: 1.7 ( 3.79x) dmvr_hv_12_20x20_c: 10.2 ( 1.00x) dmvr_hv_12_20x20_neon: 2.2 ( 4.64x)
Unified · Split
| @@ -85,6 +85,15 @@ W_AVG_FUN(8) · 84 unmodified lines | |||
| 85 | W_AVG_FUN(10) | 85 | W_AVG_FUN(10) |
| 86 | W_AVG_FUN(12) | 86 | W_AVG_FUN(12) |
| 87 | 87 | ||
| 88 | #define DMVR_FUN(fn, bd) \ | ||
| 89 | void ff_vvc_dmvr_ ## fn ## bd ## _neon(int16_t *dst, \ | ||
| 90 | const uint8_t *_src, ptrdiff_t _src_stride, int height, \ | ||
| 91 | intptr_t mx, intptr_t my, int width); | ||
| 92 | |||
| 93 | DMVR_FUN(hv_, 8) | ||
| 94 | DMVR_FUN(hv_, 10) | ||
| 95 | DMVR_FUN(hv_, 12) | ||
| 96 | |||
| 88 | void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd) | 97 | void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd) |
| 89 | { | 98 | { |
| 90 | int cpu_flags = av_get_cpu_flags(); | 99 | int cpu_flags = av_get_cpu_flags(); |
| @@ -157,6 +166,7 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd) · 66 unmodified lines | |||
| 157 | 166 | ||
| 158 | c->inter.avg = ff_vvc_avg_8_neon; | 167 | c->inter.avg = ff_vvc_avg_8_neon; |
| 159 | c->inter.w_avg = vvc_w_avg_8; | 168 | c->inter.w_avg = vvc_w_avg_8; |
| 169 | c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_8_neon; | ||
| 160 | 170 | ||
| 161 | for (int i = 0; i < FF_ARRAY_ELEMS(c->sao.band_filter); i++) | 171 | for (int i = 0; i < FF_ARRAY_ELEMS(c->sao.band_filter); i++) |
| 162 | c->sao.band_filter[i] = ff_h26x_sao_band_filter_8x8_8_neon; | 172 | c->sao.band_filter[i] = ff_h26x_sao_band_filter_8x8_8_neon; |
| @@ -198,12 +208,14 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd) · 35 unmodified lines | |||
| 198 | } else if (bd == 10) { | 208 | } else if (bd == 10) { |
| 199 | c->inter.avg = ff_vvc_avg_10_neon; | 209 | c->inter.avg = ff_vvc_avg_10_neon; |
| 200 | c->inter.w_avg = vvc_w_avg_10; | 210 | c->inter.w_avg = vvc_w_avg_10; |
| 211 | c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_10_neon; | ||
| 201 | 212 | ||
| 202 | c->alf.filter[LUMA] = alf_filter_luma_10_neon; | 213 | c->alf.filter[LUMA] = alf_filter_luma_10_neon; |
| 203 | c->alf.filter[CHROMA] = alf_filter_chroma_10_neon; | 214 | c->alf.filter[CHROMA] = alf_filter_chroma_10_neon; |
| 204 | } else if (bd == 12) { | 215 | } else if (bd == 12) { |
| 205 | c->inter.avg = ff_vvc_avg_12_neon; | 216 | c->inter.avg = ff_vvc_avg_12_neon; |
| 206 | c->inter.w_avg = vvc_w_avg_12; | 217 | c->inter.w_avg = vvc_w_avg_12; |
| 218 | c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_12_neon; | ||
| 207 | 219 | ||
| 208 | c->alf.filter[LUMA] = alf_filter_luma_12_neon; | 220 | c->alf.filter[LUMA] = alf_filter_luma_12_neon; |
| 209 | c->alf.filter[CHROMA] = alf_filter_chroma_12_neon; | 221 | c->alf.filter[CHROMA] = alf_filter_chroma_12_neon; |
| @@ -226,3 +226,310 @@ vvc_avg avg, 12 · 225 unmodified lines | |||
| 226 | vvc_avg w_avg, 8 | 226 | vvc_avg w_avg, 8 |
| 227 | vvc_avg w_avg, 10 | 227 | vvc_avg w_avg, 10 |
| 228 | vvc_avg w_avg, 12 | 228 | vvc_avg w_avg, 12 |
| 229 | |||
| 230 | /* x0: int16_t *dst | ||
| 231 | * x1: const uint8_t *_src | ||
| 232 | * x2: ptrdiff_t _src_stride | ||
| 233 | * w3: int height | ||
| 234 | * x4: intptr_t mx | ||
| 235 | * x5: intptr_t my | ||
| 236 | * w6: int width | ||
| 237 | */ | ||
| 238 | function ff_vvc_dmvr_hv_8_neon, export=1 | ||
| 239 | dst .req x0 | ||
| 240 | src .req x1 | ||
| 241 | src_stride .req x2 | ||
| 242 | height .req w3 | ||
| 243 | mx .req x4 | ||
| 244 | my .req x5 | ||
| 245 | width .req w6 | ||
| 246 | tmp0 .req x7 | ||
| 247 | tmp1 .req x8 | ||
| 248 | |||
| 249 | sub sp, sp, #(VVC_MAX_PB_SIZE * 4) | ||
| 250 | |||
| 251 | movrel x9, X(ff_vvc_inter_luma_dmvr_filters) | ||
| 252 | add x12, x9, mx, lsl #1 | ||
| 253 | ldrb w10, [x12] | ||
| 254 | ldrb w11, [x12, #1] | ||
| 255 | mov tmp0, sp | ||
| 256 | add tmp1, tmp0, #(VVC_MAX_PB_SIZE * 2) | ||
| 257 | // We know the value are positive | ||
| 258 | dup v0.8h, w10 // filter_x[0] | ||
| 259 | dup v1.8h, w11 // filter_x[1] | ||
| 260 | |||
| 261 | add x12, x9, my, lsl #1 | ||
| 262 | ldrb w10, [x12] | ||
| 263 | ldrb w11, [x12, #1] | ||
| 264 | sxtw x6, w6 | ||
| 265 | movi v30.8h, #(1 << (8 - 7)) // offset1 | ||
| 266 | movi v31.8h, #8 // offset2 | ||
| 267 | dup v2.8h, w10 // filter_y[0] | ||
| 268 | dup v3.8h, w11 // filter_y[1] | ||
| 269 | |||
| 270 | // Valid value for width can only be 8 + 4, 16 + 4 | ||
| 271 | cmp width, #16 | ||
| 272 | mov w10, #0 // start filter_y or not | ||
| 273 | add height, height, #1 | ||
| 274 | sub dst, dst, #(VVC_MAX_PB_SIZE * 2) | ||
| 275 | sub src_stride, src_stride, x6 | ||
| 276 | cset w15, gt // width > 16 | ||
| 277 | 1: | ||
| 278 | mov x12, tmp0 | ||
| 279 | mov x13, tmp1 | ||
| 280 | mov x14, dst | ||
| 281 | cbz w15, 2f | ||
| 282 | |||
| 283 | // width > 16 | ||
| 284 | ldur q5, [src, #1] | ||
| 285 | ldr q4, [src], #16 | ||
| 286 | uxtl v7.8h, v5.8b | ||
| 287 | uxtl2 v17.8h, v5.16b | ||
| 288 | uxtl v6.8h, v4.8b | ||
| 289 | uxtl2 v16.8h, v4.16b | ||
| 290 | mul v6.8h, v6.8h, v0.8h | ||
| 291 | mul v16.8h, v16.8h, v0.8h | ||
| 292 | mla v6.8h, v7.8h, v1.8h | ||
| 293 | mla v16.8h, v17.8h, v1.8h | ||
| 294 | add v6.8h, v6.8h, v30.8h | ||
| 295 | add v16.8h, v16.8h, v30.8h | ||
| 296 | ushr v6.8h, v6.8h, #(8 - 6) | ||
| 297 | ushr v7.8h, v16.8h, #(8 - 6) | ||
| 298 | stp q6, q7, [x13], #32 | ||
| 299 | |||
| 300 | cbz w10, 3f | ||
| 301 | |||
| 302 | ldp q16, q17, [x12], #32 | ||
| 303 | mul v16.8h, v16.8h, v2.8h | ||
| 304 | mul v17.8h, v17.8h, v2.8h | ||
| 305 | mla v16.8h, v6.8h, v3.8h | ||
| 306 | mla v17.8h, v7.8h, v3.8h | ||
| 307 | add v16.8h, v16.8h, v31.8h | ||
| 308 | add v17.8h, v17.8h, v31.8h | ||
| 309 | ushr v16.8h, v16.8h, #4 | ||
| 310 | ushr v17.8h, v17.8h, #4 | ||
| 311 | stp q16, q17, [x14], #32 | ||
| 312 | b 3f | ||
| 313 | 2: | ||
| 314 | // width > 8 | ||
| 315 | ldur d5, [src, #1] | ||
| 316 | ldr d4, [src], #8 | ||
| 317 | uxtl v7.8h, v5.8b | ||
| 318 | uxtl v6.8h, v4.8b | ||
| 319 | mul v6.8h, v6.8h, v0.8h | ||
| 320 | mla v6.8h, v7.8h, v1.8h | ||
| 321 | add v6.8h, v6.8h, v30.8h | ||
| 322 | ushr v6.8h, v6.8h, #(8 - 6) | ||
| 323 | str q6, [x13], #16 | ||
| 324 | |||
| 325 | cbz w10, 3f | ||
| 326 | |||
| 327 | ldr q16, [x12], #16 | ||
| 328 | mul v16.8h, v16.8h, v2.8h | ||
| 329 | mla v16.8h, v6.8h, v3.8h | ||
| 330 | add v16.8h, v16.8h, v31.8h | ||
| 331 | ushr v16.8h, v16.8h, #4 | ||
| 332 | str q16, [x14], #16 | ||
| 333 | 3: | ||
| 334 | ldr s5, [src, #1] | ||
| 335 | ldr s4, [src], #4 | ||
| 336 | uxtl v7.8h, v5.8b | ||
| 337 | uxtl v6.8h, v4.8b | ||
| 338 | mul v6.4h, v6.4h, v0.4h | ||
| 339 | mla v6.4h, v7.4h, v1.4h | ||
| 340 | add v6.4h, v6.4h, v30.4h | ||
| 341 | ushr v6.4h, v6.4h, #(8 - 6) | ||
| 342 | str d6, [x13], #8 | ||
| 343 | |||
| 344 | cbz w10, 4f | ||
| 345 | |||
| 346 | ldr d16, [x12], #8 | ||
| 347 | mul v16.4h, v16.4h, v2.4h | ||
| 348 | mla v16.4h, v6.4h, v3.4h | ||
| 349 | add v16.4h, v16.4h, v31.4h | ||
| 350 | ushr v16.4h, v16.4h, #4 | ||
| 351 | str d16, [x14], #8 | ||
| 352 | 4: | ||
| 353 | subs height, height, #1 | ||
| 354 | mov w10, #1 | ||
| 355 | add src, src, src_stride | ||
| 356 | add dst, dst, #(VVC_MAX_PB_SIZE * 2) | ||
| 357 | eor tmp0, tmp0, tmp1 | ||
| 358 | eor tmp1, tmp0, tmp1 | ||
| 359 | eor tmp0, tmp0, tmp1 | ||
| 360 | b.ne 1b | ||
| 361 | |||
| 362 | add sp, sp, #(VVC_MAX_PB_SIZE * 4) | ||
| 363 | ret | ||
| 364 | endfunc | ||
| 365 | |||
| 366 | function ff_vvc_dmvr_hv_12_neon, export=1 | ||
| 367 | movi v29.4s, #(12 - 6) | ||
| 368 | movi v30.4s, #(1 << (12 - 7)) // offset1 | ||
| 369 | b 0f | ||
| 370 | endfunc | ||
| 371 | |||
| 372 | function ff_vvc_dmvr_hv_10_neon, export=1 | ||
| 373 | movi v29.4s, #(10 - 6) | ||
| 374 | movi v30.4s, #(1 << (10 - 7)) // offset1 | ||
| 375 | 0: | ||
| 376 | movi v31.4s, #8 // offset2 | ||
| 377 | neg v29.4s, v29.4s | ||
| 378 | |||
| 379 | sub sp, sp, #(VVC_MAX_PB_SIZE * 4) | ||
| 380 | |||
| 381 | movrel x9, X(ff_vvc_inter_luma_dmvr_filters) | ||
| 382 | add x12, x9, mx, lsl #1 | ||
| 383 | ldrb w10, [x12] | ||
| 384 | ldrb w11, [x12, #1] | ||
| 385 | mov tmp0, sp | ||
| 386 | add tmp1, tmp0, #(VVC_MAX_PB_SIZE * 2) | ||
| 387 | // We know the value are positive | ||
| 388 | dup v0.8h, w10 // filter_x[0] | ||
| 389 | dup v1.8h, w11 // filter_x[1] | ||
| 390 | |||
| 391 | add x12, x9, my, lsl #1 | ||
| 392 | ldrb w10, [x12] | ||
| 393 | ldrb w11, [x12, #1] | ||
| 394 | sxtw x6, w6 | ||
| 395 | dup v2.8h, w10 // filter_y[0] | ||
| 396 | dup v3.8h, w11 // filter_y[1] | ||
| 397 | |||
| 398 | // Valid value for width can only be 8 + 4, 16 + 4 | ||
| 399 | cmp width, #16 | ||
| 400 | mov w10, #0 // start filter_y or not | ||
| 401 | add height, height, #1 | ||
| 402 | sub dst, dst, #(VVC_MAX_PB_SIZE * 2) | ||
| 403 | sub src_stride, src_stride, x6, lsl #1 | ||
| 404 | cset w15, gt // width > 16 | ||
| 405 | 1: | ||
| 406 | mov x12, tmp0 | ||
| 407 | mov x13, tmp1 | ||
| 408 | mov x14, dst | ||
| 409 | cbz w15, 2f | ||
| 410 | |||
| 411 | // width > 16 | ||
| 412 | add x16, src, #2 | ||
| 413 | ldp q6, q16, [src], #32 | ||
| 414 | ldp q7, q17, [x16] | ||
| 415 | umull v4.4s, v6.4h, v0.4h | ||
| 416 | umull2 v5.4s, v6.8h, v0.8h | ||
| 417 | umull v18.4s, v16.4h, v0.4h | ||
| 418 | umull2 v19.4s, v16.8h, v0.8h | ||
| 419 | umlal v4.4s, v7.4h, v1.4h | ||
| 420 | umlal2 v5.4s, v7.8h, v1.8h | ||
| 421 | umlal v18.4s, v17.4h, v1.4h | ||
| 422 | umlal2 v19.4s, v17.8h, v1.8h | ||
| 423 | |||
| 424 | add v4.4s, v4.4s, v30.4s | ||
| 425 | add v5.4s, v5.4s, v30.4s | ||
| 426 | add v18.4s, v18.4s, v30.4s | ||
| 427 | add v19.4s, v19.4s, v30.4s | ||
| 428 | ushl v4.4s, v4.4s, v29.4s | ||
| 429 | ushl v5.4s, v5.4s, v29.4s | ||
| 430 | ushl v18.4s, v18.4s, v29.4s | ||
| 431 | ushl v19.4s, v19.4s, v29.4s | ||
| 432 | uqxtn v6.4h, v4.4s | ||
| 433 | uqxtn2 v6.8h, v5.4s | ||
| 434 | uqxtn v7.4h, v18.4s | ||
| 435 | uqxtn2 v7.8h, v19.4s | ||
| 436 | stp q6, q7, [x13], #32 | ||
| 437 | |||
| 438 | cbz w10, 3f | ||
| 439 | |||
| 440 | ldp q4, q5, [x12], #32 | ||
| 441 | umull v17.4s, v4.4h, v2.4h | ||
| 442 | umull2 v18.4s, v4.8h, v2.8h | ||
| 443 | umull v19.4s, v5.4h, v2.4h | ||
| 444 | umull2 v20.4s, v5.8h, v2.8h | ||
| 445 | umlal v17.4s, v6.4h, v3.4h | ||
| 446 | umlal2 v18.4s, v6.8h, v3.8h | ||
| 447 | umlal v19.4s, v7.4h, v3.4h | ||
| 448 | umlal2 v20.4s, v7.8h, v3.8h | ||
| 449 | add v17.4s, v17.4s, v31.4s | ||
| 450 | add v18.4s, v18.4s, v31.4s | ||
| 451 | add v19.4s, v19.4s, v31.4s | ||
| 452 | add v20.4s, v20.4s, v31.4s | ||
| 453 | ushr v17.4s, v17.4s, #4 | ||
| 454 | ushr v18.4s, v18.4s, #4 | ||
| 455 | ushr v19.4s, v19.4s, #4 | ||
| 456 | ushr v20.4s, v20.4s, #4 | ||
| 457 | uqxtn v6.4h, v17.4s | ||
| 458 | uqxtn2 v6.8h, v18.4s | ||
| 459 | uqxtn v7.4h, v19.4s | ||
| 460 | uqxtn2 v7.8h, v20.4s | ||
| 461 | stp q6, q7, [x14], #32 | ||
| 462 | b 3f | ||
| 463 | 2: | ||
| 464 | // width > 8 | ||
| 465 | ldur q7, [src, #2] | ||
| 466 | ldr q6, [src], #16 | ||
| 467 | umull v4.4s, v6.4h, v0.4h | ||
| 468 | umull2 v5.4s, v6.8h, v0.8h | ||
| 469 | umlal v4.4s, v7.4h, v1.4h | ||
| 470 | umlal2 v5.4s, v7.8h, v1.8h | ||
| 471 | |||
| 472 | add v4.4s, v4.4s, v30.4s | ||
| 473 | add v5.4s, v5.4s, v30.4s | ||
| 474 | ushl v4.4s, v4.4s, v29.4s | ||
| 475 | ushl v5.4s, v5.4s, v29.4s | ||
| 476 | uqxtn v6.4h, v4.4s | ||
| 477 | uqxtn2 v6.8h, v5.4s | ||
| 478 | str q6, [x13], #16 | ||
| 479 | |||
| 480 | cbz w10, 3f | ||
| 481 | |||
| 482 | ldr q16, [x12], #16 | ||
| 483 | umull v17.4s, v16.4h, v2.4h | ||
| 484 | umull2 v18.4s, v16.8h, v2.8h | ||
| 485 | umlal v17.4s, v6.4h, v3.4h | ||
| 486 | umlal2 v18.4s, v6.8h, v3.8h | ||
| 487 | add v17.4s, v17.4s, v31.4s | ||
| 488 | add v18.4s, v18.4s, v31.4s | ||
| 489 | ushr v17.4s, v17.4s, #4 | ||
| 490 | ushr v18.4s, v18.4s, #4 | ||
| 491 | uqxtn v16.4h, v17.4s | ||
| 492 | uqxtn2 v16.8h, v18.4s | ||
| 493 | str q16, [x14], #16 | ||
| 494 | 3: | ||
| 495 | ldr d7, [src, #2] | ||
| 496 | ldr d6, [src], #8 | ||
| 497 | umull v4.4s, v7.4h, v1.4h | ||
| 498 | umlal v4.4s, v6.4h, v0.4h | ||
| 499 | add v4.4s, v4.4s, v30.4s | ||
| 500 | ushl v4.4s, v4.4s, v29.4s | ||
| 501 | uqxtn v6.4h, v4.4s | ||
| 502 | str d6, [x13], #8 | ||
| 503 | |||
| 504 | cbz w10, 4f | ||
| 505 | |||
| 506 | ldr d16, [x12], #8 | ||
| 507 | umull v17.4s, v16.4h, v2.4h | ||
| 508 | umlal v17.4s, v6.4h, v3.4h | ||
| 509 | add v17.4s, v17.4s, v31.4s | ||
| 510 | ushr v17.4s, v17.4s, #4 | ||
| 511 | uqxtn v16.4h, v17.4s | ||
| 512 | str d16, [x14], #8 | ||
| 513 | 4: | ||
| 514 | subs height, height, #1 | ||
| 515 | mov w10, #1 | ||
| 516 | add src, src, src_stride | ||
| 517 | add dst, dst, #(VVC_MAX_PB_SIZE * 2) | ||
| 518 | eor tmp0, tmp0, tmp1 | ||
| 519 | eor tmp1, tmp0, tmp1 | ||
| 520 | eor tmp0, tmp0, tmp1 | ||
| 521 | b.ne 1b | ||
| 522 | |||
| 523 | add sp, sp, #(VVC_MAX_PB_SIZE * 4) | ||
| 524 | ret | ||
| 525 | |||
| 526 | .unreq dst | ||
| 527 | .unreq src | ||
| 528 | .unreq src_stride | ||
| 529 | .unreq height | ||
| 530 | .unreq mx | ||
| 531 | .unreq my | ||
| 532 | .unreq width | ||
| 533 | .unreq tmp0 | ||
| 534 | .unreq tmp1 | ||
| 535 | endfunc | ||