MIPS R6 supports unaligned memory access and does not have the load/store-left/right family of instructions.
Unified · Split
| @@ -24,7 +24,13 @@ · 23 unmodified lines | ||
| 24 | 24 | #include <stdint.h> |
| 25 | 25 | #include "config.h" |
| 26 | 26 | |
| 27 | −#if ARCH_MIPS64 && HAVE_INLINE_ASM | |
| 27 | +/* | |
| 28 | + * GCC actually handles unaligned accesses correctly in all cases | |
| 29 | + * except, absurdly, 32-bit loads on mips64. | |
| 30 | + * | |
| 31 | + * https://git.libav.org/?p=libav.git;a=commit;h=b82b49a5b774b6ad9119e981c72b8f594fee2ae0 | |
| 32 | + */ | |
| 33 | +#if HAVE_MIPS64R2_INLINE || HAVE_MIPS64R1_INLINE | |
| 28 | 34 | |
| 29 | 35 | #define AV_RN32 AV_RN32 |
| 30 | 36 | static av_always_inline uint32_t AV_RN32(const void *p) |
| @@ -41,6 +47,6 @@ static av_always_inline uint32_t AV_RN32(const void *p) · 10 unmodified lines | ||
| 41 | 47 | return v; |
| 42 | 48 | } |
| 43 | 49 | |
| 44 | −#endif /* ARCH_MIPS64 && HAVE_INLINE_ASM */ | |
| 50 | +#endif /* HAVE_MIPS64R2_INLINE || HAVE_MIPS64R1_INLINE */ | |
| 45 | 51 | |
| 46 | 52 | #endif /* AVUTIL_MIPS_INTREADWRITE_H */ |