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lavu/riscv: fix compilation without Vector support

The half-baked assembler in Clang 16 and earlier can't process our RISC-V assembler. This adds yet another work around that. If you must use Clang, please use version 17 or later.

Rémi Denis-Courmont committed 1 year ago

Commit e29432e1 parent 970d5791 file · +1 −1Browse files

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libavutil/riscv/cpu.h+1−1
@@ -56,7 +56,6 @@ static inline size_t ff_get_rv_vlenb(void) · 55 unmodified lines
5656 ".option pop\n" : "=r" (vlenb));
5757 return vlenb;
5858 }
59−#endif
6059
6160 /**
6261 * Checks that the vector bit-size is at least the given value.
@@ -78,3 +77,4 @@ static inline bool ff_rv_vlen_least(unsigned int bits) · 15 unmodified lines
7877 return bits <= (8 * ff_get_rv_vlenb());
7978 }
8079 #endif
80+#endif /* HAVE_RVV */

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