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Merge "Add high bitdepth 8x8 idct NEON intrinsics"

Linfeng Zhang committed 9 years ago

Commit 2d12a522 parents 90f889a 9b187957 files · +1018 −256Browse files

Unified · Split

7 files
  1. test/partial_idct_test.cc +24 −0
  2. vpx_dsp/arm/highbd_idct8x8_add_neon.c +614 −0
  3. vpx_dsp/arm/idct8x8_add_neon.c +0 −238
  4. vpx_dsp/arm/idct_neon.h +245 −0
  5. vpx_dsp/arm/transpose_neon.h +131 −16
  6. vpx_dsp/vpx_dsp.mk +1 −0
  7. vpx_dsp/vpx_dsp_rtcd_defs.pl +3 −2
test/partial_idct_test.cc+24−0
@@ -446,6 +446,30 @@ INSTANTIATE_TEST_CASE_P(C, PartialIDctTest, · 445 unmodified lines
446#if HAVE_NEON && !CONFIG_EMULATE_HARDWARE446#if HAVE_NEON && !CONFIG_EMULATE_HARDWARE
447const PartialInvTxfmParam neon_partial_idct_tests[] = {447const PartialInvTxfmParam neon_partial_idct_tests[] = {
448#if CONFIG_VP9_HIGHBITDEPTH448#if CONFIG_VP9_HIGHBITDEPTH
449 make_tuple(&vpx_highbd_fdct8x8_c,
450 &highbd_wrapper<vpx_highbd_idct8x8_64_add_c>,
451 &highbd_wrapper<vpx_highbd_idct8x8_64_add_neon>, TX_8X8, 64, 8, 2),
452 make_tuple(
453 &vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_64_add_c>,
454 &highbd_wrapper<vpx_highbd_idct8x8_64_add_neon>, TX_8X8, 64, 10, 2),
455 make_tuple(
456 &vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_64_add_c>,
457 &highbd_wrapper<vpx_highbd_idct8x8_64_add_neon>, TX_8X8, 64, 12, 2),
458 make_tuple(&vpx_highbd_fdct8x8_c,
459 &highbd_wrapper<vpx_highbd_idct8x8_12_add_c>,
460 &highbd_wrapper<vpx_highbd_idct8x8_12_add_neon>, TX_8X8, 12, 8, 2),
461 make_tuple(
462 &vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_12_add_c>,
463 &highbd_wrapper<vpx_highbd_idct8x8_12_add_neon>, TX_8X8, 12, 10, 2),
464 make_tuple(
465 &vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_12_add_c>,
466 &highbd_wrapper<vpx_highbd_idct8x8_12_add_neon>, TX_8X8, 12, 12, 2),
467 make_tuple(&vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_1_add_c>,
468 &highbd_wrapper<vpx_highbd_idct8x8_1_add_neon>, TX_8X8, 1, 8, 2),
469 make_tuple(&vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_1_add_c>,
470 &highbd_wrapper<vpx_highbd_idct8x8_1_add_neon>, TX_8X8, 1, 10, 2),
471 make_tuple(&vpx_highbd_fdct8x8_c, &highbd_wrapper<vpx_highbd_idct8x8_1_add_c>,
472 &highbd_wrapper<vpx_highbd_idct8x8_1_add_neon>, TX_8X8, 1, 12, 2),
449 make_tuple(&vpx_highbd_fdct4x4_c,473 make_tuple(&vpx_highbd_fdct4x4_c,
450 &highbd_wrapper<vpx_highbd_idct4x4_16_add_c>,474 &highbd_wrapper<vpx_highbd_idct4x4_16_add_c>,
451 &highbd_wrapper<vpx_highbd_idct4x4_16_add_neon>, TX_4X4, 16, 8, 2),475 &highbd_wrapper<vpx_highbd_idct4x4_16_add_neon>, TX_4X4, 16, 8, 2),
vpx_dsp/arm/highbd_idct8x8_add_neon.c+614−0
@@ -0,0 +1,614 @@
1/*
2 * Copyright (c) 2016 The WebM project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11#include <arm_neon.h>
12
13#include "./vpx_dsp_rtcd.h"
14#include "vpx_dsp/arm/idct_neon.h"
15#include "vpx_dsp/arm/transpose_neon.h"
16#include "vpx_dsp/inv_txfm.h"
17
18static INLINE void highbd_idct8x8_1_add_kernel(uint16_t **dest,
19 const int stride,
20 const int16x8_t res,
21 const int16x8_t max) {
22 const uint16x8_t a = vld1q_u16(*dest);
23 const int16x8_t b = vaddq_s16(res, vreinterpretq_s16_u16(a));
24 const int16x8_t c = vminq_s16(b, max);
25 const uint16x8_t d = vqshluq_n_s16(c, 0);
26 vst1q_u16(*dest, d);
27 *dest += stride;
28}
29
30void vpx_highbd_idct8x8_1_add_neon(const tran_low_t *input, uint8_t *dest8,
31 int stride, int bd) {
32 const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
33 const tran_low_t out0 =
34 HIGHBD_WRAPLOW(dct_const_round_shift(input[0] * cospi_16_64), bd);
35 const tran_low_t out1 =
36 HIGHBD_WRAPLOW(dct_const_round_shift(out0 * cospi_16_64), bd);
37 const int16_t a1 = ROUND_POWER_OF_TWO(out1, 5);
38 const int16x8_t dc = vdupq_n_s16(a1);
39 uint16_t *dest = CONVERT_TO_SHORTPTR(dest8);
40
41 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
42 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
43 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
44 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
45 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
46 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
47 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
48 highbd_idct8x8_1_add_kernel(&dest, stride, dc, max);
49}
50
51static INLINE void idct8x8_12_half1d_bd10(
52 const int32x4_t cospis0, const int32x4_t cospis1, int32x4_t *const io0,
53 int32x4_t *const io1, int32x4_t *const io2, int32x4_t *const io3,
54 int32x4_t *const io4, int32x4_t *const io5, int32x4_t *const io6,
55 int32x4_t *const io7) {
56 int32x4_t step1[8], step2[8];
57
58 transpose_s32_4x4(io0, io1, io2, io3);
59
60 // stage 1
61 step1[4] = vmulq_lane_s32(*io1, vget_high_s32(cospis1), 1);
62 step1[5] = vmulq_lane_s32(*io3, vget_high_s32(cospis1), 0);
63 step1[6] = vmulq_lane_s32(*io3, vget_low_s32(cospis1), 1);
64 step1[7] = vmulq_lane_s32(*io1, vget_low_s32(cospis1), 0);
65 step1[4] = vrshrq_n_s32(step1[4], 14);
66 step1[5] = vrshrq_n_s32(step1[5], 14);
67 step1[6] = vrshrq_n_s32(step1[6], 14);
68 step1[7] = vrshrq_n_s32(step1[7], 14);
69
70 // stage 2
71 step2[1] = vmulq_lane_s32(*io0, vget_high_s32(cospis0), 0);
72 step2[2] = vmulq_lane_s32(*io2, vget_high_s32(cospis0), 1);
73 step2[3] = vmulq_lane_s32(*io2, vget_low_s32(cospis0), 1);
74 step2[1] = vrshrq_n_s32(step2[1], 14);
75 step2[2] = vrshrq_n_s32(step2[2], 14);
76 step2[3] = vrshrq_n_s32(step2[3], 14);
77
78 step2[4] = vaddq_s32(step1[4], step1[5]);
79 step2[5] = vsubq_s32(step1[4], step1[5]);
80 step2[6] = vsubq_s32(step1[7], step1[6]);
81 step2[7] = vaddq_s32(step1[7], step1[6]);
82
83 // stage 3
84 step1[0] = vaddq_s32(step2[1], step2[3]);
85 step1[1] = vaddq_s32(step2[1], step2[2]);
86 step1[2] = vsubq_s32(step2[1], step2[2]);
87 step1[3] = vsubq_s32(step2[1], step2[3]);
88
89 step1[6] = vmulq_lane_s32(step2[6], vget_high_s32(cospis0), 0);
90 step1[5] = vmlsq_lane_s32(step1[6], step2[5], vget_high_s32(cospis0), 0);
91 step1[6] = vmlaq_lane_s32(step1[6], step2[5], vget_high_s32(cospis0), 0);
92 step1[5] = vrshrq_n_s32(step1[5], 14);
93 step1[6] = vrshrq_n_s32(step1[6], 14);
94
95 // stage 4
96 *io0 = vaddq_s32(step1[0], step2[7]);
97 *io1 = vaddq_s32(step1[1], step1[6]);
98 *io2 = vaddq_s32(step1[2], step1[5]);
99 *io3 = vaddq_s32(step1[3], step2[4]);
100 *io4 = vsubq_s32(step1[3], step2[4]);
101 *io5 = vsubq_s32(step1[2], step1[5]);
102 *io6 = vsubq_s32(step1[1], step1[6]);
103 *io7 = vsubq_s32(step1[0], step2[7]);
104}
105
106static INLINE void idct8x8_12_half1d_bd12(
107 const int32x4_t cospis0, const int32x4_t cospis1, int32x4_t *const io0,
108 int32x4_t *const io1, int32x4_t *const io2, int32x4_t *const io3,
109 int32x4_t *const io4, int32x4_t *const io5, int32x4_t *const io6,
110 int32x4_t *const io7) {
111 int32x2_t input_1l, input_1h, input_3l, input_3h;
112 int32x2_t step1l[2], step1h[2];
113 int32x4_t step1[8], step2[8];
114 int64x2_t t64[8];
115 int32x2_t t32[8];
116
117 transpose_s32_4x4(io0, io1, io2, io3);
118
119 // stage 1
120 input_1l = vget_low_s32(*io1);
121 input_1h = vget_high_s32(*io1);
122 input_3l = vget_low_s32(*io3);
123 input_3h = vget_high_s32(*io3);
124 step1l[0] = vget_low_s32(*io0);
125 step1h[0] = vget_high_s32(*io0);
126 step1l[1] = vget_low_s32(*io2);
127 step1h[1] = vget_high_s32(*io2);
128
129 t64[0] = vmull_lane_s32(input_1l, vget_high_s32(cospis1), 1);
130 t64[1] = vmull_lane_s32(input_1h, vget_high_s32(cospis1), 1);
131 t64[2] = vmull_lane_s32(input_3l, vget_high_s32(cospis1), 0);
132 t64[3] = vmull_lane_s32(input_3h, vget_high_s32(cospis1), 0);
133 t64[4] = vmull_lane_s32(input_3l, vget_low_s32(cospis1), 1);
134 t64[5] = vmull_lane_s32(input_3h, vget_low_s32(cospis1), 1);
135 t64[6] = vmull_lane_s32(input_1l, vget_low_s32(cospis1), 0);
136 t64[7] = vmull_lane_s32(input_1h, vget_low_s32(cospis1), 0);
137 t32[0] = vrshrn_n_s64(t64[0], 14);
138 t32[1] = vrshrn_n_s64(t64[1], 14);
139 t32[2] = vrshrn_n_s64(t64[2], 14);
140 t32[3] = vrshrn_n_s64(t64[3], 14);
141 t32[4] = vrshrn_n_s64(t64[4], 14);
142 t32[5] = vrshrn_n_s64(t64[5], 14);
143 t32[6] = vrshrn_n_s64(t64[6], 14);
144 t32[7] = vrshrn_n_s64(t64[7], 14);
145 step1[4] = vcombine_s32(t32[0], t32[1]);
146 step1[5] = vcombine_s32(t32[2], t32[3]);
147 step1[6] = vcombine_s32(t32[4], t32[5]);
148 step1[7] = vcombine_s32(t32[6], t32[7]);
149
150 // stage 2
151 t64[2] = vmull_lane_s32(step1l[0], vget_high_s32(cospis0), 0);
152 t64[3] = vmull_lane_s32(step1h[0], vget_high_s32(cospis0), 0);
153 t64[4] = vmull_lane_s32(step1l[1], vget_high_s32(cospis0), 1);
154 t64[5] = vmull_lane_s32(step1h[1], vget_high_s32(cospis0), 1);
155 t64[6] = vmull_lane_s32(step1l[1], vget_low_s32(cospis0), 1);
156 t64[7] = vmull_lane_s32(step1h[1], vget_low_s32(cospis0), 1);
157 t32[2] = vrshrn_n_s64(t64[2], 14);
158 t32[3] = vrshrn_n_s64(t64[3], 14);
159 t32[4] = vrshrn_n_s64(t64[4], 14);
160 t32[5] = vrshrn_n_s64(t64[5], 14);
161 t32[6] = vrshrn_n_s64(t64[6], 14);
162 t32[7] = vrshrn_n_s64(t64[7], 14);
163 step2[1] = vcombine_s32(t32[2], t32[3]);
164 step2[2] = vcombine_s32(t32[4], t32[5]);
165 step2[3] = vcombine_s32(t32[6], t32[7]);
166
167 step2[4] = vaddq_s32(step1[4], step1[5]);
168 step2[5] = vsubq_s32(step1[4], step1[5]);
169 step2[6] = vsubq_s32(step1[7], step1[6]);
170 step2[7] = vaddq_s32(step1[7], step1[6]);
171
172 // stage 3
173 step1[0] = vaddq_s32(step2[1], step2[3]);
174 step1[1] = vaddq_s32(step2[1], step2[2]);
175 step1[2] = vsubq_s32(step2[1], step2[2]);
176 step1[3] = vsubq_s32(step2[1], step2[3]);
177
178 t64[2] = vmull_lane_s32(vget_low_s32(step2[6]), vget_high_s32(cospis0), 0);
179 t64[3] = vmull_lane_s32(vget_high_s32(step2[6]), vget_high_s32(cospis0), 0);
180 t64[0] =
181 vmlsl_lane_s32(t64[2], vget_low_s32(step2[5]), vget_high_s32(cospis0), 0);
182 t64[1] = vmlsl_lane_s32(t64[3], vget_high_s32(step2[5]),
183 vget_high_s32(cospis0), 0);
184 t64[2] =
185 vmlal_lane_s32(t64[2], vget_low_s32(step2[5]), vget_high_s32(cospis0), 0);
186 t64[3] = vmlal_lane_s32(t64[3], vget_high_s32(step2[5]),
187 vget_high_s32(cospis0), 0);
188 t32[0] = vrshrn_n_s64(t64[0], 14);
189 t32[1] = vrshrn_n_s64(t64[1], 14);
190 t32[2] = vrshrn_n_s64(t64[2], 14);
191 t32[3] = vrshrn_n_s64(t64[3], 14);
192 step1[5] = vcombine_s32(t32[0], t32[1]);
193 step1[6] = vcombine_s32(t32[2], t32[3]);
194
195 // stage 4
196 *io0 = vaddq_s32(step1[0], step2[7]);
197 *io1 = vaddq_s32(step1[1], step1[6]);
198 *io2 = vaddq_s32(step1[2], step1[5]);
199 *io3 = vaddq_s32(step1[3], step2[4]);
200 *io4 = vsubq_s32(step1[3], step2[4]);
201 *io5 = vsubq_s32(step1[2], step1[5]);
202 *io6 = vsubq_s32(step1[1], step1[6]);
203 *io7 = vsubq_s32(step1[0], step2[7]);
204}
205
206static INLINE void highbd_add8x8(int16x8_t a0, int16x8_t a1, int16x8_t a2,
207 int16x8_t a3, int16x8_t a4, int16x8_t a5,
208 int16x8_t a6, int16x8_t a7, uint16_t *dest,
209 const int stride, const int bd) {
210 const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
211 const uint16_t *dst = dest;
212 uint16x8_t d0, d1, d2, d3, d4, d5, d6, d7;
213 uint16x8_t d0_u16, d1_u16, d2_u16, d3_u16, d4_u16, d5_u16, d6_u16, d7_u16;
214 int16x8_t d0_s16, d1_s16, d2_s16, d3_s16, d4_s16, d5_s16, d6_s16, d7_s16;
215
216 d0 = vld1q_u16(dst);
217 dst += stride;
218 d1 = vld1q_u16(dst);
219 dst += stride;
220 d2 = vld1q_u16(dst);
221 dst += stride;
222 d3 = vld1q_u16(dst);
223 dst += stride;
224 d4 = vld1q_u16(dst);
225 dst += stride;
226 d5 = vld1q_u16(dst);
227 dst += stride;
228 d6 = vld1q_u16(dst);
229 dst += stride;
230 d7 = vld1q_u16(dst);
231
232 d0_s16 = vqaddq_s16(a0, vreinterpretq_s16_u16(d0));
233 d1_s16 = vqaddq_s16(a1, vreinterpretq_s16_u16(d1));
234 d2_s16 = vqaddq_s16(a2, vreinterpretq_s16_u16(d2));
235 d3_s16 = vqaddq_s16(a3, vreinterpretq_s16_u16(d3));
236 d4_s16 = vqaddq_s16(a4, vreinterpretq_s16_u16(d4));
237 d5_s16 = vqaddq_s16(a5, vreinterpretq_s16_u16(d5));
238 d6_s16 = vqaddq_s16(a6, vreinterpretq_s16_u16(d6));
239 d7_s16 = vqaddq_s16(a7, vreinterpretq_s16_u16(d7));
240
241 d0_s16 = vminq_s16(d0_s16, max);
242 d1_s16 = vminq_s16(d1_s16, max);
243 d2_s16 = vminq_s16(d2_s16, max);
244 d3_s16 = vminq_s16(d3_s16, max);
245 d4_s16 = vminq_s16(d4_s16, max);
246 d5_s16 = vminq_s16(d5_s16, max);
247 d6_s16 = vminq_s16(d6_s16, max);
248 d7_s16 = vminq_s16(d7_s16, max);
249 d0_u16 = vqshluq_n_s16(d0_s16, 0);
250 d1_u16 = vqshluq_n_s16(d1_s16, 0);
251 d2_u16 = vqshluq_n_s16(d2_s16, 0);
252 d3_u16 = vqshluq_n_s16(d3_s16, 0);
253 d4_u16 = vqshluq_n_s16(d4_s16, 0);
254 d5_u16 = vqshluq_n_s16(d5_s16, 0);
255 d6_u16 = vqshluq_n_s16(d6_s16, 0);
256 d7_u16 = vqshluq_n_s16(d7_s16, 0);
257
258 vst1q_u16(dest, d0_u16);
259 dest += stride;
260 vst1q_u16(dest, d1_u16);
261 dest += stride;
262 vst1q_u16(dest, d2_u16);
263 dest += stride;
264 vst1q_u16(dest, d3_u16);
265 dest += stride;
266 vst1q_u16(dest, d4_u16);
267 dest += stride;
268 vst1q_u16(dest, d5_u16);
269 dest += stride;
270 vst1q_u16(dest, d6_u16);
271 dest += stride;
272 vst1q_u16(dest, d7_u16);
273}
274
275void vpx_highbd_idct8x8_12_add_neon(const tran_low_t *input, uint8_t *dest8,
276 int stride, int bd) {
277 uint16_t *dest = CONVERT_TO_SHORTPTR(dest8);
278 int32x4_t a0 = vld1q_s32(input);
279 int32x4_t a1 = vld1q_s32(input + 8);
280 int32x4_t a2 = vld1q_s32(input + 16);
281 int32x4_t a3 = vld1q_s32(input + 24);
282 int16x8_t c0, c1, c2, c3, c4, c5, c6, c7;
283
284 if (bd == 8) {
285 const int16x8_t cospis = vld1q_s16(kCospi);
286 const int16x8_t cospisd = vaddq_s16(cospis, cospis);
287 const int16x4_t cospis0 = vget_low_s16(cospis); // cospi 0, 8, 16, 24
288 const int16x4_t cospisd0 = vget_low_s16(cospisd); // doubled 0, 8, 16, 24
289 const int16x4_t cospisd1 = vget_high_s16(cospisd); // doubled 4, 12, 20, 28
290 int16x4_t b0 = vmovn_s32(a0);
291 int16x4_t b1 = vmovn_s32(a1);
292 int16x4_t b2 = vmovn_s32(a2);
293 int16x4_t b3 = vmovn_s32(a3);
294 int16x4_t b4, b5, b6, b7;
295
296 idct8x8_12_pass1_bd8(cospis0, cospisd0, cospisd1, &b0, &b1, &b2, &b3, &b4,
297 &b5, &b6, &b7);
298 idct8x8_12_pass2_bd8(cospis0, cospisd0, cospisd1, b0, b1, b2, b3, b4, b5,
299 b6, b7, &c0, &c1, &c2, &c3, &c4, &c5, &c6, &c7);
300 c0 = vrshrq_n_s16(c0, 5);
301 c1 = vrshrq_n_s16(c1, 5);
302 c2 = vrshrq_n_s16(c2, 5);
303 c3 = vrshrq_n_s16(c3, 5);
304 c4 = vrshrq_n_s16(c4, 5);
305 c5 = vrshrq_n_s16(c5, 5);
306 c6 = vrshrq_n_s16(c6, 5);
307 c7 = vrshrq_n_s16(c7, 5);
308 } else {
309 const int32x4_t cospis0 = vld1q_s32(kCospi32); // cospi 0, 8, 16, 24
310 const int32x4_t cospis1 = vld1q_s32(kCospi32 + 4); // cospi 4, 12, 20, 28
311 int32x4_t a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15;
312
313 if (bd == 10) {
314 idct8x8_12_half1d_bd10(cospis0, cospis1, &a0, &a1, &a2, &a3, &a4, &a5,
315 &a6, &a7);
316 idct8x8_12_half1d_bd10(cospis0, cospis1, &a0, &a1, &a2, &a3, &a8, &a9,
317 &a10, &a11);
318 idct8x8_12_half1d_bd10(cospis0, cospis1, &a4, &a5, &a6, &a7, &a12, &a13,
319 &a14, &a15);
320 } else {
321 idct8x8_12_half1d_bd12(cospis0, cospis1, &a0, &a1, &a2, &a3, &a4, &a5,
322 &a6, &a7);
323 idct8x8_12_half1d_bd12(cospis0, cospis1, &a0, &a1, &a2, &a3, &a8, &a9,
324 &a10, &a11);
325 idct8x8_12_half1d_bd12(cospis0, cospis1, &a4, &a5, &a6, &a7, &a12, &a13,
326 &a14, &a15);
327 }
328 c0 = vcombine_s16(vrshrn_n_s32(a0, 5), vrshrn_n_s32(a4, 5));
329 c1 = vcombine_s16(vrshrn_n_s32(a1, 5), vrshrn_n_s32(a5, 5));
330 c2 = vcombine_s16(vrshrn_n_s32(a2, 5), vrshrn_n_s32(a6, 5));
331 c3 = vcombine_s16(vrshrn_n_s32(a3, 5), vrshrn_n_s32(a7, 5));
332 c4 = vcombine_s16(vrshrn_n_s32(a8, 5), vrshrn_n_s32(a12, 5));
333 c5 = vcombine_s16(vrshrn_n_s32(a9, 5), vrshrn_n_s32(a13, 5));
334 c6 = vcombine_s16(vrshrn_n_s32(a10, 5), vrshrn_n_s32(a14, 5));
335 c7 = vcombine_s16(vrshrn_n_s32(a11, 5), vrshrn_n_s32(a15, 5));
336 }
337 highbd_add8x8(c0, c1, c2, c3, c4, c5, c6, c7, dest, stride, bd);
338}
339
340static INLINE void idct8x8_64_half1d_bd10(
341 const int32x4_t cospis0, const int32x4_t cospis1, int32x4_t *const io0,
342 int32x4_t *const io1, int32x4_t *const io2, int32x4_t *const io3,
343 int32x4_t *const io4, int32x4_t *const io5, int32x4_t *const io6,
344 int32x4_t *const io7) {
345 int32x4_t step1[8], step2[8];
346
347 transpose_s32_8x4(io0, io1, io2, io3, io4, io5, io6, io7);
348
349 // stage 1
350 step1[4] = vmulq_lane_s32(*io1, vget_high_s32(cospis1), 1);
351 step1[5] = vmulq_lane_s32(*io3, vget_high_s32(cospis1), 0);
352 step1[6] = vmulq_lane_s32(*io3, vget_low_s32(cospis1), 1);
353 step1[7] = vmulq_lane_s32(*io1, vget_low_s32(cospis1), 0);
354
355 step1[4] = vmlsq_lane_s32(step1[4], *io7, vget_low_s32(cospis1), 0);
356 step1[5] = vmlaq_lane_s32(step1[5], *io5, vget_low_s32(cospis1), 1);
357 step1[6] = vmlsq_lane_s32(step1[6], *io5, vget_high_s32(cospis1), 0);
358 step1[7] = vmlaq_lane_s32(step1[7], *io7, vget_high_s32(cospis1), 1);
359
360 step1[4] = vrshrq_n_s32(step1[4], 14);
361 step1[5] = vrshrq_n_s32(step1[5], 14);
362 step1[6] = vrshrq_n_s32(step1[6], 14);
363 step1[7] = vrshrq_n_s32(step1[7], 14);
364
365 // stage 2
366 step2[1] = vmulq_lane_s32(*io0, vget_high_s32(cospis0), 0);
367 step2[2] = vmulq_lane_s32(*io2, vget_high_s32(cospis0), 1);
368 step2[3] = vmulq_lane_s32(*io2, vget_low_s32(cospis0), 1);
369
370 step2[0] = vmlaq_lane_s32(step2[1], *io4, vget_high_s32(cospis0), 0);
371 step2[1] = vmlsq_lane_s32(step2[1], *io4, vget_high_s32(cospis0), 0);
372 step2[2] = vmlsq_lane_s32(step2[2], *io6, vget_low_s32(cospis0), 1);
373 step2[3] = vmlaq_lane_s32(step2[3], *io6, vget_high_s32(cospis0), 1);
374
375 step2[0] = vrshrq_n_s32(step2[0], 14);
376 step2[1] = vrshrq_n_s32(step2[1], 14);
377 step2[2] = vrshrq_n_s32(step2[2], 14);
378 step2[3] = vrshrq_n_s32(step2[3], 14);
379
380 step2[4] = vaddq_s32(step1[4], step1[5]);
381 step2[5] = vsubq_s32(step1[4], step1[5]);
382 step2[6] = vsubq_s32(step1[7], step1[6]);
383 step2[7] = vaddq_s32(step1[7], step1[6]);
384
385 // stage 3
386 step1[0] = vaddq_s32(step2[0], step2[3]);
387 step1[1] = vaddq_s32(step2[1], step2[2]);
388 step1[2] = vsubq_s32(step2[1], step2[2]);
389 step1[3] = vsubq_s32(step2[0], step2[3]);
390
391 step1[6] = vmulq_lane_s32(step2[6], vget_high_s32(cospis0), 0);
392 step1[5] = vmlsq_lane_s32(step1[6], step2[5], vget_high_s32(cospis0), 0);
393 step1[6] = vmlaq_lane_s32(step1[6], step2[5], vget_high_s32(cospis0), 0);
394 step1[5] = vrshrq_n_s32(step1[5], 14);
395 step1[6] = vrshrq_n_s32(step1[6], 14);
396
397 // stage 4
398 *io0 = vaddq_s32(step1[0], step2[7]);
399 *io1 = vaddq_s32(step1[1], step1[6]);
400 *io2 = vaddq_s32(step1[2], step1[5]);
401 *io3 = vaddq_s32(step1[3], step2[4]);
402 *io4 = vsubq_s32(step1[3], step2[4]);
403 *io5 = vsubq_s32(step1[2], step1[5]);
404 *io6 = vsubq_s32(step1[1], step1[6]);
405 *io7 = vsubq_s32(step1[0], step2[7]);
406}
407
408static INLINE void idct8x8_64_half1d_bd12(
409 const int32x4_t cospis0, const int32x4_t cospis1, int32x4_t *const io0,
410 int32x4_t *const io1, int32x4_t *const io2, int32x4_t *const io3,
411 int32x4_t *const io4, int32x4_t *const io5, int32x4_t *const io6,
412 int32x4_t *const io7) {
413 int32x2_t input_1l, input_1h, input_3l, input_3h, input_5l, input_5h,
414 input_7l, input_7h;
415 int32x2_t step1l[4], step1h[4];
416 int32x4_t step1[8], step2[8];
417 int64x2_t t64[8];
418 int32x2_t t32[8];
419
420 transpose_s32_8x4(io0, io1, io2, io3, io4, io5, io6, io7);
421
422 // stage 1
423 input_1l = vget_low_s32(*io1);
424 input_1h = vget_high_s32(*io1);
425 input_3l = vget_low_s32(*io3);
426 input_3h = vget_high_s32(*io3);
427 input_5l = vget_low_s32(*io5);
428 input_5h = vget_high_s32(*io5);
429 input_7l = vget_low_s32(*io7);
430 input_7h = vget_high_s32(*io7);
431 step1l[0] = vget_low_s32(*io0);
432 step1h[0] = vget_high_s32(*io0);
433 step1l[1] = vget_low_s32(*io2);
434 step1h[1] = vget_high_s32(*io2);
435 step1l[2] = vget_low_s32(*io4);
436 step1h[2] = vget_high_s32(*io4);
437 step1l[3] = vget_low_s32(*io6);
438 step1h[3] = vget_high_s32(*io6);
439
440 t64[0] = vmull_lane_s32(input_1l, vget_high_s32(cospis1), 1);
441 t64[1] = vmull_lane_s32(input_1h, vget_high_s32(cospis1), 1);
442 t64[2] = vmull_lane_s32(input_3l, vget_high_s32(cospis1), 0);
443 t64[3] = vmull_lane_s32(input_3h, vget_high_s32(cospis1), 0);
444 t64[4] = vmull_lane_s32(input_3l, vget_low_s32(cospis1), 1);
445 t64[5] = vmull_lane_s32(input_3h, vget_low_s32(cospis1), 1);
446 t64[6] = vmull_lane_s32(input_1l, vget_low_s32(cospis1), 0);
447 t64[7] = vmull_lane_s32(input_1h, vget_low_s32(cospis1), 0);
448 t64[0] = vmlsl_lane_s32(t64[0], input_7l, vget_low_s32(cospis1), 0);
449 t64[1] = vmlsl_lane_s32(t64[1], input_7h, vget_low_s32(cospis1), 0);
450 t64[2] = vmlal_lane_s32(t64[2], input_5l, vget_low_s32(cospis1), 1);
451 t64[3] = vmlal_lane_s32(t64[3], input_5h, vget_low_s32(cospis1), 1);
452 t64[4] = vmlsl_lane_s32(t64[4], input_5l, vget_high_s32(cospis1), 0);
453 t64[5] = vmlsl_lane_s32(t64[5], input_5h, vget_high_s32(cospis1), 0);
454 t64[6] = vmlal_lane_s32(t64[6], input_7l, vget_high_s32(cospis1), 1);
455 t64[7] = vmlal_lane_s32(t64[7], input_7h, vget_high_s32(cospis1), 1);
456 t32[0] = vrshrn_n_s64(t64[0], 14);
457 t32[1] = vrshrn_n_s64(t64[1], 14);
458 t32[2] = vrshrn_n_s64(t64[2], 14);
459 t32[3] = vrshrn_n_s64(t64[3], 14);
460 t32[4] = vrshrn_n_s64(t64[4], 14);
461 t32[5] = vrshrn_n_s64(t64[5], 14);
462 t32[6] = vrshrn_n_s64(t64[6], 14);
463 t32[7] = vrshrn_n_s64(t64[7], 14);
464 step1[4] = vcombine_s32(t32[0], t32[1]);
465 step1[5] = vcombine_s32(t32[2], t32[3]);
466 step1[6] = vcombine_s32(t32[4], t32[5]);
467 step1[7] = vcombine_s32(t32[6], t32[7]);
468
469 // stage 2
470 t64[2] = vmull_lane_s32(step1l[0], vget_high_s32(cospis0), 0);
471 t64[3] = vmull_lane_s32(step1h[0], vget_high_s32(cospis0), 0);
472 t64[4] = vmull_lane_s32(step1l[1], vget_high_s32(cospis0), 1);
473 t64[5] = vmull_lane_s32(step1h[1], vget_high_s32(cospis0), 1);
474 t64[6] = vmull_lane_s32(step1l[1], vget_low_s32(cospis0), 1);
475 t64[7] = vmull_lane_s32(step1h[1], vget_low_s32(cospis0), 1);
476 t64[0] = vmlal_lane_s32(t64[2], step1l[2], vget_high_s32(cospis0), 0);
477 t64[1] = vmlal_lane_s32(t64[3], step1h[2], vget_high_s32(cospis0), 0);
478 t64[2] = vmlsl_lane_s32(t64[2], step1l[2], vget_high_s32(cospis0), 0);
479 t64[3] = vmlsl_lane_s32(t64[3], step1h[2], vget_high_s32(cospis0), 0);
480 t64[4] = vmlsl_lane_s32(t64[4], step1l[3], vget_low_s32(cospis0), 1);
481 t64[5] = vmlsl_lane_s32(t64[5], step1h[3], vget_low_s32(cospis0), 1);
482 t64[6] = vmlal_lane_s32(t64[6], step1l[3], vget_high_s32(cospis0), 1);
483 t64[7] = vmlal_lane_s32(t64[7], step1h[3], vget_high_s32(cospis0), 1);
484 t32[0] = vrshrn_n_s64(t64[0], 14);
485 t32[1] = vrshrn_n_s64(t64[1], 14);
486 t32[2] = vrshrn_n_s64(t64[2], 14);
487 t32[3] = vrshrn_n_s64(t64[3], 14);
488 t32[4] = vrshrn_n_s64(t64[4], 14);
489 t32[5] = vrshrn_n_s64(t64[5], 14);
490 t32[6] = vrshrn_n_s64(t64[6], 14);
491 t32[7] = vrshrn_n_s64(t64[7], 14);
492 step2[0] = vcombine_s32(t32[0], t32[1]);
493 step2[1] = vcombine_s32(t32[2], t32[3]);
494 step2[2] = vcombine_s32(t32[4], t32[5]);
495 step2[3] = vcombine_s32(t32[6], t32[7]);
496
497 step2[4] = vaddq_s32(step1[4], step1[5]);
498 step2[5] = vsubq_s32(step1[4], step1[5]);
499 step2[6] = vsubq_s32(step1[7], step1[6]);
500 step2[7] = vaddq_s32(step1[7], step1[6]);
501
502 // stage 3
503 step1[0] = vaddq_s32(step2[0], step2[3]);
504 step1[1] = vaddq_s32(step2[1], step2[2]);
505 step1[2] = vsubq_s32(step2[1], step2[2]);
506 step1[3] = vsubq_s32(step2[0], step2[3]);
507
508 t64[2] = vmull_lane_s32(vget_low_s32(step2[6]), vget_high_s32(cospis0), 0);
509 t64[3] = vmull_lane_s32(vget_high_s32(step2[6]), vget_high_s32(cospis0), 0);
510 t64[0] =
511 vmlsl_lane_s32(t64[2], vget_low_s32(step2[5]), vget_high_s32(cospis0), 0);
512 t64[1] = vmlsl_lane_s32(t64[3], vget_high_s32(step2[5]),
513 vget_high_s32(cospis0), 0);
514 t64[2] =
515 vmlal_lane_s32(t64[2], vget_low_s32(step2[5]), vget_high_s32(cospis0), 0);
516 t64[3] = vmlal_lane_s32(t64[3], vget_high_s32(step2[5]),
517 vget_high_s32(cospis0), 0);
518 t32[0] = vrshrn_n_s64(t64[0], 14);
519 t32[1] = vrshrn_n_s64(t64[1], 14);
520 t32[2] = vrshrn_n_s64(t64[2], 14);
521 t32[3] = vrshrn_n_s64(t64[3], 14);
522 step1[5] = vcombine_s32(t32[0], t32[1]);
523 step1[6] = vcombine_s32(t32[2], t32[3]);
524
525 // stage 4
526 *io0 = vaddq_s32(step1[0], step2[7]);
527 *io1 = vaddq_s32(step1[1], step1[6]);
528 *io2 = vaddq_s32(step1[2], step1[5]);
529 *io3 = vaddq_s32(step1[3], step2[4]);
530 *io4 = vsubq_s32(step1[3], step2[4]);
531 *io5 = vsubq_s32(step1[2], step1[5]);
532 *io6 = vsubq_s32(step1[1], step1[6]);
533 *io7 = vsubq_s32(step1[0], step2[7]);
534}
535
536void vpx_highbd_idct8x8_64_add_neon(const tran_low_t *input, uint8_t *dest8,
537 int stride, int bd) {
538 uint16_t *dest = CONVERT_TO_SHORTPTR(dest8);
539 int32x4_t a0 = vld1q_s32(input);
540 int32x4_t a1 = vld1q_s32(input + 4);
541 int32x4_t a2 = vld1q_s32(input + 8);
542 int32x4_t a3 = vld1q_s32(input + 12);
543 int32x4_t a4 = vld1q_s32(input + 16);
544 int32x4_t a5 = vld1q_s32(input + 20);
545 int32x4_t a6 = vld1q_s32(input + 24);
546 int32x4_t a7 = vld1q_s32(input + 28);
547 int32x4_t a8 = vld1q_s32(input + 32);
548 int32x4_t a9 = vld1q_s32(input + 36);
549 int32x4_t a10 = vld1q_s32(input + 40);
550 int32x4_t a11 = vld1q_s32(input + 44);
551 int32x4_t a12 = vld1q_s32(input + 48);
552 int32x4_t a13 = vld1q_s32(input + 52);
553 int32x4_t a14 = vld1q_s32(input + 56);
554 int32x4_t a15 = vld1q_s32(input + 60);
555 int16x8_t c0, c1, c2, c3, c4, c5, c6, c7;
556
557 if (bd == 8) {
558 const int16x8_t cospis = vld1q_s16(kCospi);
559 const int16x4_t cospis0 = vget_low_s16(cospis); // cospi 0, 8, 16, 24
560 const int16x4_t cospis1 = vget_high_s16(cospis); // cospi 4, 12, 20, 28
561 int16x8_t b0 = vcombine_s16(vmovn_s32(a0), vmovn_s32(a1));
562 int16x8_t b1 = vcombine_s16(vmovn_s32(a2), vmovn_s32(a3));
563 int16x8_t b2 = vcombine_s16(vmovn_s32(a4), vmovn_s32(a5));
564 int16x8_t b3 = vcombine_s16(vmovn_s32(a6), vmovn_s32(a7));
565 int16x8_t b4 = vcombine_s16(vmovn_s32(a8), vmovn_s32(a9));
566 int16x8_t b5 = vcombine_s16(vmovn_s32(a10), vmovn_s32(a11));
567 int16x8_t b6 = vcombine_s16(vmovn_s32(a12), vmovn_s32(a13));
568 int16x8_t b7 = vcombine_s16(vmovn_s32(a14), vmovn_s32(a15));
569
570 idct8x8_64_1d_bd8(cospis0, cospis1, &b0, &b1, &b2, &b3, &b4, &b5, &b6, &b7);
571 idct8x8_64_1d_bd8(cospis0, cospis1, &b0, &b1, &b2, &b3, &b4, &b5, &b6, &b7);
572
573 c0 = vrshrq_n_s16(b0, 5);
574 c1 = vrshrq_n_s16(b1, 5);
575 c2 = vrshrq_n_s16(b2, 5);
576 c3 = vrshrq_n_s16(b3, 5);
577 c4 = vrshrq_n_s16(b4, 5);
578 c5 = vrshrq_n_s16(b5, 5);
579 c6 = vrshrq_n_s16(b6, 5);
580 c7 = vrshrq_n_s16(b7, 5);
581 } else {
582 const int32x4_t cospis0 = vld1q_s32(kCospi32); // cospi 0, 8, 16, 24
583 const int32x4_t cospis1 = vld1q_s32(kCospi32 + 4); // cospi 4, 12, 20, 28
584
585 if (bd == 10) {
586 idct8x8_64_half1d_bd10(cospis0, cospis1, &a0, &a1, &a2, &a3, &a4, &a5,
587 &a6, &a7);
588 idct8x8_64_half1d_bd10(cospis0, cospis1, &a8, &a9, &a10, &a11, &a12, &a13,
589 &a14, &a15);
590 idct8x8_64_half1d_bd10(cospis0, cospis1, &a0, &a8, &a1, &a9, &a2, &a10,
591 &a3, &a11);
592 idct8x8_64_half1d_bd10(cospis0, cospis1, &a4, &a12, &a5, &a13, &a6, &a14,
593 &a7, &a15);
594 } else {
595 idct8x8_64_half1d_bd12(cospis0, cospis1, &a0, &a1, &a2, &a3, &a4, &a5,
596 &a6, &a7);
597 idct8x8_64_half1d_bd12(cospis0, cospis1, &a8, &a9, &a10, &a11, &a12, &a13,
598 &a14, &a15);
599 idct8x8_64_half1d_bd12(cospis0, cospis1, &a0, &a8, &a1, &a9, &a2, &a10,
600 &a3, &a11);
601 idct8x8_64_half1d_bd12(cospis0, cospis1, &a4, &a12, &a5, &a13, &a6, &a14,
602 &a7, &a15);
603 }
604 c0 = vcombine_s16(vrshrn_n_s32(a0, 5), vrshrn_n_s32(a4, 5));
605 c1 = vcombine_s16(vrshrn_n_s32(a8, 5), vrshrn_n_s32(a12, 5));
606 c2 = vcombine_s16(vrshrn_n_s32(a1, 5), vrshrn_n_s32(a5, 5));
607 c3 = vcombine_s16(vrshrn_n_s32(a9, 5), vrshrn_n_s32(a13, 5));
608 c4 = vcombine_s16(vrshrn_n_s32(a2, 5), vrshrn_n_s32(a6, 5));
609 c5 = vcombine_s16(vrshrn_n_s32(a10, 5), vrshrn_n_s32(a14, 5));
610 c6 = vcombine_s16(vrshrn_n_s32(a3, 5), vrshrn_n_s32(a7, 5));
611 c7 = vcombine_s16(vrshrn_n_s32(a11, 5), vrshrn_n_s32(a15, 5));
612 }
613 highbd_add8x8(c0, c1, c2, c3, c4, c5, c6, c7, dest, stride, bd);
614}
vpx_dsp/arm/idct8x8_add_neon.c+0−238
@@ -16,132 +16,6 @@ · 15 unmodified lines
16#include "vpx_dsp/arm/transpose_neon.h"16#include "vpx_dsp/arm/transpose_neon.h"
17#include "vpx_dsp/txfm_common.h"17#include "vpx_dsp/txfm_common.h"
18 18
19static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
20 const int16x4_t cospis1,
21 int16x8_t *const io0, int16x8_t *const io1,
22 int16x8_t *const io2, int16x8_t *const io3,
23 int16x8_t *const io4, int16x8_t *const io5,
24 int16x8_t *const io6,
25 int16x8_t *const io7) {
26 int16x4_t input_1l, input_1h, input_3l, input_3h, input_5l, input_5h,
27 input_7l, input_7h;
28 int16x4_t step1l[4], step1h[4];
29 int16x8_t step1[8], step2[8];
30 int32x4_t t32[8];
31 int16x4_t t16[8];
32
33 transpose_s16_8x8(io0, io1, io2, io3, io4, io5, io6, io7);
34
35 // stage 1
36 input_1l = vget_low_s16(*io1);
37 input_1h = vget_high_s16(*io1);
38 input_3l = vget_low_s16(*io3);
39 input_3h = vget_high_s16(*io3);
40 input_5l = vget_low_s16(*io5);
41 input_5h = vget_high_s16(*io5);
42 input_7l = vget_low_s16(*io7);
43 input_7h = vget_high_s16(*io7);
44 step1l[0] = vget_low_s16(*io0);
45 step1h[0] = vget_high_s16(*io0);
46 step1l[1] = vget_low_s16(*io2);
47 step1h[1] = vget_high_s16(*io2);
48 step1l[2] = vget_low_s16(*io4);
49 step1h[2] = vget_high_s16(*io4);
50 step1l[3] = vget_low_s16(*io6);
51 step1h[3] = vget_high_s16(*io6);
52
53 t32[0] = vmull_lane_s16(input_1l, cospis1, 3);
54 t32[1] = vmull_lane_s16(input_1h, cospis1, 3);
55 t32[2] = vmull_lane_s16(input_3l, cospis1, 2);
56 t32[3] = vmull_lane_s16(input_3h, cospis1, 2);
57 t32[4] = vmull_lane_s16(input_3l, cospis1, 1);
58 t32[5] = vmull_lane_s16(input_3h, cospis1, 1);
59 t32[6] = vmull_lane_s16(input_1l, cospis1, 0);
60 t32[7] = vmull_lane_s16(input_1h, cospis1, 0);
61 t32[0] = vmlsl_lane_s16(t32[0], input_7l, cospis1, 0);
62 t32[1] = vmlsl_lane_s16(t32[1], input_7h, cospis1, 0);
63 t32[2] = vmlal_lane_s16(t32[2], input_5l, cospis1, 1);
64 t32[3] = vmlal_lane_s16(t32[3], input_5h, cospis1, 1);
65 t32[4] = vmlsl_lane_s16(t32[4], input_5l, cospis1, 2);
66 t32[5] = vmlsl_lane_s16(t32[5], input_5h, cospis1, 2);
67 t32[6] = vmlal_lane_s16(t32[6], input_7l, cospis1, 3);
68 t32[7] = vmlal_lane_s16(t32[7], input_7h, cospis1, 3);
69 t16[0] = vrshrn_n_s32(t32[0], 14);
70 t16[1] = vrshrn_n_s32(t32[1], 14);
71 t16[2] = vrshrn_n_s32(t32[2], 14);
72 t16[3] = vrshrn_n_s32(t32[3], 14);
73 t16[4] = vrshrn_n_s32(t32[4], 14);
74 t16[5] = vrshrn_n_s32(t32[5], 14);
75 t16[6] = vrshrn_n_s32(t32[6], 14);
76 t16[7] = vrshrn_n_s32(t32[7], 14);
77 step1[4] = vcombine_s16(t16[0], t16[1]);
78 step1[5] = vcombine_s16(t16[2], t16[3]);
79 step1[6] = vcombine_s16(t16[4], t16[5]);
80 step1[7] = vcombine_s16(t16[6], t16[7]);
81
82 // stage 2
83 t32[2] = vmull_lane_s16(step1l[0], cospis0, 2);
84 t32[3] = vmull_lane_s16(step1h[0], cospis0, 2);
85 t32[4] = vmull_lane_s16(step1l[1], cospis0, 3);
86 t32[5] = vmull_lane_s16(step1h[1], cospis0, 3);
87 t32[6] = vmull_lane_s16(step1l[1], cospis0, 1);
88 t32[7] = vmull_lane_s16(step1h[1], cospis0, 1);
89 t32[0] = vmlal_lane_s16(t32[2], step1l[2], cospis0, 2);
90 t32[1] = vmlal_lane_s16(t32[3], step1h[2], cospis0, 2);
91 t32[2] = vmlsl_lane_s16(t32[2], step1l[2], cospis0, 2);
92 t32[3] = vmlsl_lane_s16(t32[3], step1h[2], cospis0, 2);
93 t32[4] = vmlsl_lane_s16(t32[4], step1l[3], cospis0, 1);
94 t32[5] = vmlsl_lane_s16(t32[5], step1h[3], cospis0, 1);
95 t32[6] = vmlal_lane_s16(t32[6], step1l[3], cospis0, 3);
96 t32[7] = vmlal_lane_s16(t32[7], step1h[3], cospis0, 3);
97 t16[0] = vrshrn_n_s32(t32[0], 14);
98 t16[1] = vrshrn_n_s32(t32[1], 14);
99 t16[2] = vrshrn_n_s32(t32[2], 14);
100 t16[3] = vrshrn_n_s32(t32[3], 14);
101 t16[4] = vrshrn_n_s32(t32[4], 14);
102 t16[5] = vrshrn_n_s32(t32[5], 14);
103 t16[6] = vrshrn_n_s32(t32[6], 14);
104 t16[7] = vrshrn_n_s32(t32[7], 14);
105 step2[0] = vcombine_s16(t16[0], t16[1]);
106 step2[1] = vcombine_s16(t16[2], t16[3]);
107 step2[2] = vcombine_s16(t16[4], t16[5]);
108 step2[3] = vcombine_s16(t16[6], t16[7]);
109
110 step2[4] = vaddq_s16(step1[4], step1[5]);
111 step2[5] = vsubq_s16(step1[4], step1[5]);
112 step2[6] = vsubq_s16(step1[7], step1[6]);
113 step2[7] = vaddq_s16(step1[7], step1[6]);
114
115 // stage 3
116 step1[0] = vaddq_s16(step2[0], step2[3]);
117 step1[1] = vaddq_s16(step2[1], step2[2]);
118 step1[2] = vsubq_s16(step2[1], step2[2]);
119 step1[3] = vsubq_s16(step2[0], step2[3]);
120
121 t32[2] = vmull_lane_s16(vget_low_s16(step2[6]), cospis0, 2);
122 t32[3] = vmull_lane_s16(vget_high_s16(step2[6]), cospis0, 2);
123 t32[0] = vmlsl_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
124 t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
125 t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
126 t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
127 t16[0] = vrshrn_n_s32(t32[0], 14);
128 t16[1] = vrshrn_n_s32(t32[1], 14);
129 t16[2] = vrshrn_n_s32(t32[2], 14);
130 t16[3] = vrshrn_n_s32(t32[3], 14);
131 step1[5] = vcombine_s16(t16[0], t16[1]);
132 step1[6] = vcombine_s16(t16[2], t16[3]);
133
134 // stage 4
135 *io0 = vaddq_s16(step1[0], step2[7]);
136 *io1 = vaddq_s16(step1[1], step1[6]);
137 *io2 = vaddq_s16(step1[2], step1[5]);
138 *io3 = vaddq_s16(step1[3], step2[4]);
139 *io4 = vsubq_s16(step1[3], step2[4]);
140 *io5 = vsubq_s16(step1[2], step1[5]);
141 *io6 = vsubq_s16(step1[1], step1[6]);
142 *io7 = vsubq_s16(step1[0], step2[7]);
143}
144
145static INLINE void add8x8(int16x8_t a0, int16x8_t a1, int16x8_t a2,19static INLINE void add8x8(int16x8_t a0, int16x8_t a1, int16x8_t a2,
146 int16x8_t a3, int16x8_t a4, int16x8_t a5,20 int16x8_t a3, int16x8_t a4, int16x8_t a5,
147 int16x8_t a6, int16x8_t a7, uint8_t *dest,21 int16x8_t a6, int16x8_t a7, uint8_t *dest,
@@ -229,118 +103,6 @@ void vpx_idct8x8_64_add_neon(const tran_low_t *input, uint8_t *dest, · 81 unmodified lines
229 add8x8(a0, a1, a2, a3, a4, a5, a6, a7, dest, stride);103 add8x8(a0, a1, a2, a3, a4, a5, a6, a7, dest, stride);
230}104}
231 105
232static INLINE void idct8x8_12_pass1_bd8(
233 const int16x4_t cospis0, const int16x4_t cospisd0, const int16x4_t cospisd1,
234 int16x4_t *const io0, int16x4_t *const io1, int16x4_t *const io2,
235 int16x4_t *const io3, int16x4_t *const io4, int16x4_t *const io5,
236 int16x4_t *const io6, int16x4_t *const io7) {
237 int16x4_t step1[8], step2[8];
238 int32x4_t t32[2];
239
240 transpose_s16_4x4d(io0, io1, io2, io3);
241
242 // stage 1
243 step1[4] = vqrdmulh_lane_s16(*io1, cospisd1, 3);
244 step1[5] = vqrdmulh_lane_s16(*io3, cospisd1, 2);
245 step1[6] = vqrdmulh_lane_s16(*io3, cospisd1, 1);
246 step1[7] = vqrdmulh_lane_s16(*io1, cospisd1, 0);
247
248 // stage 2
249 step2[0] = vqrdmulh_lane_s16(*io0, cospisd0, 2);
250 step2[2] = vqrdmulh_lane_s16(*io2, cospisd0, 3);
251 step2[3] = vqrdmulh_lane_s16(*io2, cospisd0, 1);
252
253 step2[4] = vadd_s16(step1[4], step1[5]);
254 step2[5] = vsub_s16(step1[4], step1[5]);
255 step2[6] = vsub_s16(step1[7], step1[6]);
256 step2[7] = vadd_s16(step1[7], step1[6]);
257
258 // stage 3
259 step1[0] = vadd_s16(step2[0], step2[3]);
260 step1[1] = vadd_s16(step2[0], step2[2]);
261 step1[2] = vsub_s16(step2[0], step2[2]);
262 step1[3] = vsub_s16(step2[0], step2[3]);
263
264 t32[1] = vmull_lane_s16(step2[6], cospis0, 2);
265 t32[0] = vmlsl_lane_s16(t32[1], step2[5], cospis0, 2);
266 t32[1] = vmlal_lane_s16(t32[1], step2[5], cospis0, 2);
267 step1[5] = vrshrn_n_s32(t32[0], 14);
268 step1[6] = vrshrn_n_s32(t32[1], 14);
269
270 // stage 4
271 *io0 = vadd_s16(step1[0], step2[7]);
272 *io1 = vadd_s16(step1[1], step1[6]);
273 *io2 = vadd_s16(step1[2], step1[5]);
274 *io3 = vadd_s16(step1[3], step2[4]);
275 *io4 = vsub_s16(step1[3], step2[4]);
276 *io5 = vsub_s16(step1[2], step1[5]);
277 *io6 = vsub_s16(step1[1], step1[6]);
278 *io7 = vsub_s16(step1[0], step2[7]);
279}
280
281static INLINE void idct8x8_12_pass2_bd8(
282 const int16x4_t cospis0, const int16x4_t cospisd0, const int16x4_t cospisd1,
283 const int16x4_t input0, const int16x4_t input1, const int16x4_t input2,
284 const int16x4_t input3, const int16x4_t input4, const int16x4_t input5,
285 const int16x4_t input6, const int16x4_t input7, int16x8_t *const output0,
286 int16x8_t *const output1, int16x8_t *const output2,
287 int16x8_t *const output3, int16x8_t *const output4,
288 int16x8_t *const output5, int16x8_t *const output6,
289 int16x8_t *const output7) {
290 int16x8_t in[4];
291 int16x8_t step1[8], step2[8];
292 int32x4_t t32[8];
293 int16x4_t t16[8];
294
295 transpose_s16_4x8(input0, input1, input2, input3, input4, input5, input6,
296 input7, &in[0], &in[1], &in[2], &in[3]);
297
298 // stage 1
299 step1[4] = vqrdmulhq_lane_s16(in[1], cospisd1, 3);
300 step1[5] = vqrdmulhq_lane_s16(in[3], cospisd1, 2);
301 step1[6] = vqrdmulhq_lane_s16(in[3], cospisd1, 1);
302 step1[7] = vqrdmulhq_lane_s16(in[1], cospisd1, 0);
303
304 // stage 2
305 step2[0] = vqrdmulhq_lane_s16(in[0], cospisd0, 2);
306 step2[2] = vqrdmulhq_lane_s16(in[2], cospisd0, 3);
307 step2[3] = vqrdmulhq_lane_s16(in[2], cospisd0, 1);
308
309 step2[4] = vaddq_s16(step1[4], step1[5]);
310 step2[5] = vsubq_s16(step1[4], step1[5]);
311 step2[6] = vsubq_s16(step1[7], step1[6]);
312 step2[7] = vaddq_s16(step1[7], step1[6]);
313
314 // stage 3
315 step1[0] = vaddq_s16(step2[0], step2[3]);
316 step1[1] = vaddq_s16(step2[0], step2[2]);
317 step1[2] = vsubq_s16(step2[0], step2[2]);
318 step1[3] = vsubq_s16(step2[0], step2[3]);
319
320 t32[2] = vmull_lane_s16(vget_low_s16(step2[6]), cospis0, 2);
321 t32[3] = vmull_lane_s16(vget_high_s16(step2[6]), cospis0, 2);
322 t32[0] = vmlsl_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
323 t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
324 t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
325 t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
326 t16[0] = vrshrn_n_s32(t32[0], 14);
327 t16[1] = vrshrn_n_s32(t32[1], 14);
328 t16[2] = vrshrn_n_s32(t32[2], 14);
329 t16[3] = vrshrn_n_s32(t32[3], 14);
330 step1[5] = vcombine_s16(t16[0], t16[1]);
331 step1[6] = vcombine_s16(t16[2], t16[3]);
332
333 // stage 4
334 *output0 = vaddq_s16(step1[0], step2[7]);
335 *output1 = vaddq_s16(step1[1], step1[6]);
336 *output2 = vaddq_s16(step1[2], step1[5]);
337 *output3 = vaddq_s16(step1[3], step2[4]);
338 *output4 = vsubq_s16(step1[3], step2[4]);
339 *output5 = vsubq_s16(step1[2], step1[5]);
340 *output6 = vsubq_s16(step1[1], step1[6]);
341 *output7 = vsubq_s16(step1[0], step2[7]);
342}
343
344void vpx_idct8x8_12_add_neon(const tran_low_t *input, uint8_t *dest,106void vpx_idct8x8_12_add_neon(const tran_low_t *input, uint8_t *dest,
345 int stride) {107 int stride) {
346 const int16x8_t cospis = vld1q_s16(kCospi);108 const int16x8_t cospis = vld1q_s16(kCospi);
vpx_dsp/arm/idct_neon.h+245−0
@@ -24,6 +24,13 @@ DECLARE_ALIGNED(16, static const int16_t, kCospi[8]) = { · 23 unmodified lines
24 -9102 /* -cospi_20_64 */, 3196 /* cospi_28_64 */24 -9102 /* -cospi_20_64 */, 3196 /* cospi_28_64 */
25};25};
26 26
27DECLARE_ALIGNED(16, static const int32_t, kCospi32[8]) = {
28 16384 /* cospi_0_64 */, 15137 /* cospi_8_64 */,
29 11585 /* cospi_16_64 */, 6270 /* cospi_24_64 */,
30 16069 /* cospi_4_64 */, 13623 /* cospi_12_64 */,
31 -9102 /* -cospi_20_64 */, 3196 /* cospi_28_64 */
32};
33
27//------------------------------------------------------------------------------34//------------------------------------------------------------------------------
28// Helper functions used to load tran_low_t into int16, narrowing if necessary.35// Helper functions used to load tran_low_t into int16, narrowing if necessary.
29 36
@@ -217,4 +224,242 @@ static INLINE void idct4x4_16_kernel_bd8(const int16x4_t cospis, · 187 unmodified lines
217 *a1 = vsubq_s16(d0, d1);224 *a1 = vsubq_s16(d0, d1);
218}225}
219 226
227static INLINE void idct8x8_12_pass1_bd8(
228 const int16x4_t cospis0, const int16x4_t cospisd0, const int16x4_t cospisd1,
229 int16x4_t *const io0, int16x4_t *const io1, int16x4_t *const io2,
230 int16x4_t *const io3, int16x4_t *const io4, int16x4_t *const io5,
231 int16x4_t *const io6, int16x4_t *const io7) {
232 int16x4_t step1[8], step2[8];
233 int32x4_t t32[2];
234
235 transpose_s16_4x4d(io0, io1, io2, io3);
236
237 // stage 1
238 step1[4] = vqrdmulh_lane_s16(*io1, cospisd1, 3);
239 step1[5] = vqrdmulh_lane_s16(*io3, cospisd1, 2);
240 step1[6] = vqrdmulh_lane_s16(*io3, cospisd1, 1);
241 step1[7] = vqrdmulh_lane_s16(*io1, cospisd1, 0);
242
243 // stage 2
244 step2[1] = vqrdmulh_lane_s16(*io0, cospisd0, 2);
245 step2[2] = vqrdmulh_lane_s16(*io2, cospisd0, 3);
246 step2[3] = vqrdmulh_lane_s16(*io2, cospisd0, 1);
247
248 step2[4] = vadd_s16(step1[4], step1[5]);
249 step2[5] = vsub_s16(step1[4], step1[5]);
250 step2[6] = vsub_s16(step1[7], step1[6]);
251 step2[7] = vadd_s16(step1[7], step1[6]);
252
253 // stage 3
254 step1[0] = vadd_s16(step2[1], step2[3]);
255 step1[1] = vadd_s16(step2[1], step2[2]);
256 step1[2] = vsub_s16(step2[1], step2[2]);
257 step1[3] = vsub_s16(step2[1], step2[3]);
258
259 t32[1] = vmull_lane_s16(step2[6], cospis0, 2);
260 t32[0] = vmlsl_lane_s16(t32[1], step2[5], cospis0, 2);
261 t32[1] = vmlal_lane_s16(t32[1], step2[5], cospis0, 2);
262 step1[5] = vrshrn_n_s32(t32[0], 14);
263 step1[6] = vrshrn_n_s32(t32[1], 14);
264
265 // stage 4
266 *io0 = vadd_s16(step1[0], step2[7]);
267 *io1 = vadd_s16(step1[1], step1[6]);
268 *io2 = vadd_s16(step1[2], step1[5]);
269 *io3 = vadd_s16(step1[3], step2[4]);
270 *io4 = vsub_s16(step1[3], step2[4]);
271 *io5 = vsub_s16(step1[2], step1[5]);
272 *io6 = vsub_s16(step1[1], step1[6]);
273 *io7 = vsub_s16(step1[0], step2[7]);
274}
275
276static INLINE void idct8x8_12_pass2_bd8(
277 const int16x4_t cospis0, const int16x4_t cospisd0, const int16x4_t cospisd1,
278 const int16x4_t input0, const int16x4_t input1, const int16x4_t input2,
279 const int16x4_t input3, const int16x4_t input4, const int16x4_t input5,
280 const int16x4_t input6, const int16x4_t input7, int16x8_t *const output0,
281 int16x8_t *const output1, int16x8_t *const output2,
282 int16x8_t *const output3, int16x8_t *const output4,
283 int16x8_t *const output5, int16x8_t *const output6,
284 int16x8_t *const output7) {
285 int16x8_t in[4];
286 int16x8_t step1[8], step2[8];
287 int32x4_t t32[8];
288 int16x4_t t16[8];
289
290 transpose_s16_4x8(input0, input1, input2, input3, input4, input5, input6,
291 input7, &in[0], &in[1], &in[2], &in[3]);
292
293 // stage 1
294 step1[4] = vqrdmulhq_lane_s16(in[1], cospisd1, 3);
295 step1[5] = vqrdmulhq_lane_s16(in[3], cospisd1, 2);
296 step1[6] = vqrdmulhq_lane_s16(in[3], cospisd1, 1);
297 step1[7] = vqrdmulhq_lane_s16(in[1], cospisd1, 0);
298
299 // stage 2
300 step2[1] = vqrdmulhq_lane_s16(in[0], cospisd0, 2);
301 step2[2] = vqrdmulhq_lane_s16(in[2], cospisd0, 3);
302 step2[3] = vqrdmulhq_lane_s16(in[2], cospisd0, 1);
303
304 step2[4] = vaddq_s16(step1[4], step1[5]);
305 step2[5] = vsubq_s16(step1[4], step1[5]);
306 step2[6] = vsubq_s16(step1[7], step1[6]);
307 step2[7] = vaddq_s16(step1[7], step1[6]);
308
309 // stage 3
310 step1[0] = vaddq_s16(step2[1], step2[3]);
311 step1[1] = vaddq_s16(step2[1], step2[2]);
312 step1[2] = vsubq_s16(step2[1], step2[2]);
313 step1[3] = vsubq_s16(step2[1], step2[3]);
314
315 t32[2] = vmull_lane_s16(vget_low_s16(step2[6]), cospis0, 2);
316 t32[3] = vmull_lane_s16(vget_high_s16(step2[6]), cospis0, 2);
317 t32[0] = vmlsl_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
318 t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
319 t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
320 t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
321 t16[0] = vrshrn_n_s32(t32[0], 14);
322 t16[1] = vrshrn_n_s32(t32[1], 14);
323 t16[2] = vrshrn_n_s32(t32[2], 14);
324 t16[3] = vrshrn_n_s32(t32[3], 14);
325 step1[5] = vcombine_s16(t16[0], t16[1]);
326 step1[6] = vcombine_s16(t16[2], t16[3]);
327
328 // stage 4
329 *output0 = vaddq_s16(step1[0], step2[7]);
330 *output1 = vaddq_s16(step1[1], step1[6]);
331 *output2 = vaddq_s16(step1[2], step1[5]);
332 *output3 = vaddq_s16(step1[3], step2[4]);
333 *output4 = vsubq_s16(step1[3], step2[4]);
334 *output5 = vsubq_s16(step1[2], step1[5]);
335 *output6 = vsubq_s16(step1[1], step1[6]);
336 *output7 = vsubq_s16(step1[0], step2[7]);
337}
338
339static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
340 const int16x4_t cospis1,
341 int16x8_t *const io0, int16x8_t *const io1,
342 int16x8_t *const io2, int16x8_t *const io3,
343 int16x8_t *const io4, int16x8_t *const io5,
344 int16x8_t *const io6,
345 int16x8_t *const io7) {
346 int16x4_t input_1l, input_1h, input_3l, input_3h, input_5l, input_5h,
347 input_7l, input_7h;
348 int16x4_t step1l[4], step1h[4];
349 int16x8_t step1[8], step2[8];
350 int32x4_t t32[8];
351 int16x4_t t16[8];
352
353 transpose_s16_8x8(io0, io1, io2, io3, io4, io5, io6, io7);
354
355 // stage 1
356 input_1l = vget_low_s16(*io1);
357 input_1h = vget_high_s16(*io1);
358 input_3l = vget_low_s16(*io3);
359 input_3h = vget_high_s16(*io3);
360 input_5l = vget_low_s16(*io5);
361 input_5h = vget_high_s16(*io5);
362 input_7l = vget_low_s16(*io7);
363 input_7h = vget_high_s16(*io7);
364 step1l[0] = vget_low_s16(*io0);
365 step1h[0] = vget_high_s16(*io0);
366 step1l[1] = vget_low_s16(*io2);
367 step1h[1] = vget_high_s16(*io2);
368 step1l[2] = vget_low_s16(*io4);
369 step1h[2] = vget_high_s16(*io4);
370 step1l[3] = vget_low_s16(*io6);
371 step1h[3] = vget_high_s16(*io6);
372
373 t32[0] = vmull_lane_s16(input_1l, cospis1, 3);
374 t32[1] = vmull_lane_s16(input_1h, cospis1, 3);
375 t32[2] = vmull_lane_s16(input_3l, cospis1, 2);
376 t32[3] = vmull_lane_s16(input_3h, cospis1, 2);
377 t32[4] = vmull_lane_s16(input_3l, cospis1, 1);
378 t32[5] = vmull_lane_s16(input_3h, cospis1, 1);
379 t32[6] = vmull_lane_s16(input_1l, cospis1, 0);
380 t32[7] = vmull_lane_s16(input_1h, cospis1, 0);
381 t32[0] = vmlsl_lane_s16(t32[0], input_7l, cospis1, 0);
382 t32[1] = vmlsl_lane_s16(t32[1], input_7h, cospis1, 0);
383 t32[2] = vmlal_lane_s16(t32[2], input_5l, cospis1, 1);
384 t32[3] = vmlal_lane_s16(t32[3], input_5h, cospis1, 1);
385 t32[4] = vmlsl_lane_s16(t32[4], input_5l, cospis1, 2);
386 t32[5] = vmlsl_lane_s16(t32[5], input_5h, cospis1, 2);
387 t32[6] = vmlal_lane_s16(t32[6], input_7l, cospis1, 3);
388 t32[7] = vmlal_lane_s16(t32[7], input_7h, cospis1, 3);
389 t16[0] = vrshrn_n_s32(t32[0], 14);
390 t16[1] = vrshrn_n_s32(t32[1], 14);
391 t16[2] = vrshrn_n_s32(t32[2], 14);
392 t16[3] = vrshrn_n_s32(t32[3], 14);
393 t16[4] = vrshrn_n_s32(t32[4], 14);
394 t16[5] = vrshrn_n_s32(t32[5], 14);
395 t16[6] = vrshrn_n_s32(t32[6], 14);
396 t16[7] = vrshrn_n_s32(t32[7], 14);
397 step1[4] = vcombine_s16(t16[0], t16[1]);
398 step1[5] = vcombine_s16(t16[2], t16[3]);
399 step1[6] = vcombine_s16(t16[4], t16[5]);
400 step1[7] = vcombine_s16(t16[6], t16[7]);
401
402 // stage 2
403 t32[2] = vmull_lane_s16(step1l[0], cospis0, 2);
404 t32[3] = vmull_lane_s16(step1h[0], cospis0, 2);
405 t32[4] = vmull_lane_s16(step1l[1], cospis0, 3);
406 t32[5] = vmull_lane_s16(step1h[1], cospis0, 3);
407 t32[6] = vmull_lane_s16(step1l[1], cospis0, 1);
408 t32[7] = vmull_lane_s16(step1h[1], cospis0, 1);
409 t32[0] = vmlal_lane_s16(t32[2], step1l[2], cospis0, 2);
410 t32[1] = vmlal_lane_s16(t32[3], step1h[2], cospis0, 2);
411 t32[2] = vmlsl_lane_s16(t32[2], step1l[2], cospis0, 2);
412 t32[3] = vmlsl_lane_s16(t32[3], step1h[2], cospis0, 2);
413 t32[4] = vmlsl_lane_s16(t32[4], step1l[3], cospis0, 1);
414 t32[5] = vmlsl_lane_s16(t32[5], step1h[3], cospis0, 1);
415 t32[6] = vmlal_lane_s16(t32[6], step1l[3], cospis0, 3);
416 t32[7] = vmlal_lane_s16(t32[7], step1h[3], cospis0, 3);
417 t16[0] = vrshrn_n_s32(t32[0], 14);
418 t16[1] = vrshrn_n_s32(t32[1], 14);
419 t16[2] = vrshrn_n_s32(t32[2], 14);
420 t16[3] = vrshrn_n_s32(t32[3], 14);
421 t16[4] = vrshrn_n_s32(t32[4], 14);
422 t16[5] = vrshrn_n_s32(t32[5], 14);
423 t16[6] = vrshrn_n_s32(t32[6], 14);
424 t16[7] = vrshrn_n_s32(t32[7], 14);
425 step2[0] = vcombine_s16(t16[0], t16[1]);
426 step2[1] = vcombine_s16(t16[2], t16[3]);
427 step2[2] = vcombine_s16(t16[4], t16[5]);
428 step2[3] = vcombine_s16(t16[6], t16[7]);
429
430 step2[4] = vaddq_s16(step1[4], step1[5]);
431 step2[5] = vsubq_s16(step1[4], step1[5]);
432 step2[6] = vsubq_s16(step1[7], step1[6]);
433 step2[7] = vaddq_s16(step1[7], step1[6]);
434
435 // stage 3
436 step1[0] = vaddq_s16(step2[0], step2[3]);
437 step1[1] = vaddq_s16(step2[1], step2[2]);
438 step1[2] = vsubq_s16(step2[1], step2[2]);
439 step1[3] = vsubq_s16(step2[0], step2[3]);
440
441 t32[2] = vmull_lane_s16(vget_low_s16(step2[6]), cospis0, 2);
442 t32[3] = vmull_lane_s16(vget_high_s16(step2[6]), cospis0, 2);
443 t32[0] = vmlsl_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
444 t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
445 t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
446 t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
447 t16[0] = vrshrn_n_s32(t32[0], 14);
448 t16[1] = vrshrn_n_s32(t32[1], 14);
449 t16[2] = vrshrn_n_s32(t32[2], 14);
450 t16[3] = vrshrn_n_s32(t32[3], 14);
451 step1[5] = vcombine_s16(t16[0], t16[1]);
452 step1[6] = vcombine_s16(t16[2], t16[3]);
453
454 // stage 4
455 *io0 = vaddq_s16(step1[0], step2[7]);
456 *io1 = vaddq_s16(step1[1], step1[6]);
457 *io2 = vaddq_s16(step1[2], step1[5]);
458 *io3 = vaddq_s16(step1[3], step2[4]);
459 *io4 = vsubq_s16(step1[3], step2[4]);
460 *io5 = vsubq_s16(step1[2], step1[5]);
461 *io6 = vsubq_s16(step1[1], step1[6]);
462 *io7 = vsubq_s16(step1[0], step2[7]);
463}
464
220#endif // VPX_DSP_ARM_IDCT_NEON_H_465#endif // VPX_DSP_ARM_IDCT_NEON_H_
vpx_dsp/arm/transpose_neon.h+131−16
@@ -21,7 +21,7 @@ · 20 unmodified lines
21//21//
22// b0.val[0]: 00 01 02 03 16 17 18 1922// b0.val[0]: 00 01 02 03 16 17 18 19
23// b0.val[1]: 04 05 06 07 20 21 22 2323// b0.val[1]: 04 05 06 07 20 21 22 23
24static INLINE int16x8x2_t vpx_vtrnq_s64(int32x4_t a0, int32x4_t a1) {24static INLINE int16x8x2_t vpx_vtrnq_s64_to_s16(int32x4_t a0, int32x4_t a1) {
25 int16x8x2_t b0;25 int16x8x2_t b0;
26 b0.val[0] = vcombine_s16(vreinterpret_s16_s32(vget_low_s32(a0)),26 b0.val[0] = vcombine_s16(vreinterpret_s16_s32(vget_low_s32(a0)),
27 vreinterpret_s16_s32(vget_low_s32(a1)));27 vreinterpret_s16_s32(vget_low_s32(a1)));
@@ -37,7 +37,16 @@ static INLINE int32x4x2_t vpx_vtrnq_s64_to_s32(int32x4_t a0, int32x4_t a1) { · 9 unmodified lines
37 return b0;37 return b0;
38}38}
39 39
40static INLINE uint8x16x2_t vpx_vtrnq_u64(uint32x4_t a0, uint32x4_t a1) {40static INLINE int64x2x2_t vpx_vtrnq_s64(int32x4_t a0, int32x4_t a1) {
41 int64x2x2_t b0;
42 b0.val[0] = vcombine_s64(vreinterpret_s64_s32(vget_low_s32(a0)),
43 vreinterpret_s64_s32(vget_low_s32(a1)));
44 b0.val[1] = vcombine_s64(vreinterpret_s64_s32(vget_high_s32(a0)),
45 vreinterpret_s64_s32(vget_high_s32(a1)));
46 return b0;
47}
48
49static INLINE uint8x16x2_t vpx_vtrnq_u64_to_u8(uint32x4_t a0, uint32x4_t a1) {
41 uint8x16x2_t b0;50 uint8x16x2_t b0;
42 b0.val[0] = vcombine_u8(vreinterpret_u8_u32(vget_low_u32(a0)),51 b0.val[0] = vcombine_u8(vreinterpret_u8_u32(vget_low_u32(a0)),
43 vreinterpret_u8_u32(vget_low_u32(a1)));52 vreinterpret_u8_u32(vget_low_u32(a1)));
@@ -270,8 +279,8 @@ static INLINE void transpose_s16_4x8(const int16x4_t a0, const int16x4_t a1, · 226 unmodified lines
270 const int16x4_t a2, const int16x4_t a3,279 const int16x4_t a2, const int16x4_t a3,
271 const int16x4_t a4, const int16x4_t a5,280 const int16x4_t a4, const int16x4_t a5,
272 const int16x4_t a6, const int16x4_t a7,281 const int16x4_t a6, const int16x4_t a7,
273 int16x8_t *o0, int16x8_t *o1,282 int16x8_t *const o0, int16x8_t *const o1,
274 int16x8_t *o2, int16x8_t *o3) {283 int16x8_t *const o2, int16x8_t *const o3) {
275 // Swap 16 bit elements. Goes from:284 // Swap 16 bit elements. Goes from:
276 // a0: 00 01 02 03285 // a0: 00 01 02 03
277 // a1: 10 11 12 13286 // a1: 10 11 12 13
@@ -331,6 +340,59 @@ static INLINE void transpose_s16_4x8(const int16x4_t a0, const int16x4_t a1, · 53 unmodified lines
331 vreinterpret_s16_s32(c3.val[1]));340 vreinterpret_s16_s32(c3.val[1]));
332}341}
333 342
343static INLINE void transpose_s32_4x8(int32x4_t *const a0, int32x4_t *const a1,
344 int32x4_t *const a2, int32x4_t *const a3,
345 int32x4_t *const a4, int32x4_t *const a5,
346 int32x4_t *const a6, int32x4_t *const a7) {
347 // Swap 32 bit elements. Goes from:
348 // a0: 00 01 02 03
349 // a1: 10 11 12 13
350 // a2: 20 21 22 23
351 // a3: 30 31 32 33
352 // a4: 40 41 42 43
353 // a5: 50 51 52 53
354 // a6: 60 61 62 63
355 // a7: 70 71 72 73
356 // to:
357 // b0.val[0]: 00 10 02 12
358 // b0.val[1]: 01 11 03 13
359 // b1.val[0]: 20 30 22 32
360 // b1.val[1]: 21 31 23 33
361 // b2.val[0]: 40 50 42 52
362 // b2.val[1]: 41 51 43 53
363 // b3.val[0]: 60 70 62 72
364 // b3.val[1]: 61 71 63 73
365
366 const int32x4x2_t b0 = vtrnq_s32(*a0, *a1);
367 const int32x4x2_t b1 = vtrnq_s32(*a2, *a3);
368 const int32x4x2_t b2 = vtrnq_s32(*a4, *a5);
369 const int32x4x2_t b3 = vtrnq_s32(*a6, *a7);
370
371 // Swap 64 bit elements resulting in:
372 // c0.val[0]: 00 10 20 30
373 // c0.val[1]: 02 12 22 32
374 // c1.val[0]: 01 11 21 31
375 // c1.val[1]: 03 13 23 33
376 // c2.val[0]: 40 50 60 70
377 // c2.val[1]: 42 52 62 72
378 // c3.val[0]: 41 51 61 71
379 // c3.val[1]: 43 53 63 73
380
381 const int64x2x2_t c0 = vpx_vtrnq_s64(b0.val[0], b1.val[0]);
382 const int64x2x2_t c1 = vpx_vtrnq_s64(b0.val[1], b1.val[1]);
383 const int64x2x2_t c2 = vpx_vtrnq_s64(b2.val[0], b3.val[0]);
384 const int64x2x2_t c3 = vpx_vtrnq_s64(b2.val[1], b3.val[1]);
385
386 *a0 = vreinterpretq_s32_s64(c0.val[0]);
387 *a1 = vreinterpretq_s32_s64(c2.val[0]);
388 *a2 = vreinterpretq_s32_s64(c1.val[0]);
389 *a3 = vreinterpretq_s32_s64(c3.val[0]);
390 *a4 = vreinterpretq_s32_s64(c0.val[1]);
391 *a5 = vreinterpretq_s32_s64(c2.val[1]);
392 *a6 = vreinterpretq_s32_s64(c1.val[1]);
393 *a7 = vreinterpretq_s32_s64(c3.val[1]);
394}
395
334static INLINE void transpose_u8_8x4(uint8x8_t *a0, uint8x8_t *a1, uint8x8_t *a2,396static INLINE void transpose_u8_8x4(uint8x8_t *a0, uint8x8_t *a1, uint8x8_t *a2,
335 uint8x8_t *a3) {397 uint8x8_t *a3) {
336 // Swap 8 bit elements. Goes from:398 // Swap 8 bit elements. Goes from:
@@ -397,6 +459,59 @@ static INLINE void transpose_u16_8x4(uint16x8_t *a0, uint16x8_t *a1, · 60 unmodified lines
397 *a3 = vreinterpretq_u16_u32(c1.val[1]);459 *a3 = vreinterpretq_u16_u32(c1.val[1]);
398}460}
399 461
462static INLINE void transpose_s32_8x4(int32x4_t *const a0, int32x4_t *const a1,
463 int32x4_t *const a2, int32x4_t *const a3,
464 int32x4_t *const a4, int32x4_t *const a5,
465 int32x4_t *const a6, int32x4_t *const a7) {
466 // Swap 32 bit elements. Goes from:
467 // a0: 00 01 02 03
468 // a1: 04 05 06 07
469 // a2: 10 11 12 13
470 // a3: 14 15 16 17
471 // a4: 20 21 22 23
472 // a5: 24 25 26 27
473 // a6: 30 31 32 33
474 // a7: 34 35 36 37
475 // to:
476 // b0.val[0]: 00 10 02 12
477 // b0.val[1]: 01 11 03 13
478 // b1.val[0]: 04 14 06 16
479 // b1.val[1]: 05 15 07 17
480 // b2.val[0]: 20 30 22 32
481 // b2.val[1]: 21 31 23 33
482 // b3.val[0]: 24 34 26 36
483 // b3.val[1]: 25 35 27 37
484
485 const int32x4x2_t b0 = vtrnq_s32(*a0, *a2);
486 const int32x4x2_t b1 = vtrnq_s32(*a1, *a3);
487 const int32x4x2_t b2 = vtrnq_s32(*a4, *a6);
488 const int32x4x2_t b3 = vtrnq_s32(*a5, *a7);
489
490 // Swap 64 bit elements resulting in:
491 // c0.val[0]: 00 10 20 30
492 // c0.val[1]: 02 12 22 32
493 // c1.val[0]: 01 11 21 31
494 // c1.val[1]: 03 13 23 33
495 // c2.val[0]: 04 14 24 34
496 // c2.val[1]: 06 16 26 36
497 // c3.val[0]: 05 15 25 35
498 // c3.val[1]: 07 17 27 37
499
500 const int64x2x2_t c0 = vpx_vtrnq_s64(b0.val[0], b2.val[0]);
501 const int64x2x2_t c1 = vpx_vtrnq_s64(b0.val[1], b2.val[1]);
502 const int64x2x2_t c2 = vpx_vtrnq_s64(b1.val[0], b3.val[0]);
503 const int64x2x2_t c3 = vpx_vtrnq_s64(b1.val[1], b3.val[1]);
504
505 *a0 = vreinterpretq_s32_s64(c0.val[0]);
506 *a1 = vreinterpretq_s32_s64(c1.val[0]);
507 *a2 = vreinterpretq_s32_s64(c0.val[1]);
508 *a3 = vreinterpretq_s32_s64(c1.val[1]);
509 *a4 = vreinterpretq_s32_s64(c2.val[0]);
510 *a5 = vreinterpretq_s32_s64(c3.val[0]);
511 *a6 = vreinterpretq_s32_s64(c2.val[1]);
512 *a7 = vreinterpretq_s32_s64(c3.val[1]);
513}
514
400// Note: Using 'd' registers or 'q' registers has almost identical speed. We use515// Note: Using 'd' registers or 'q' registers has almost identical speed. We use
401// 'q' registers here to save some instructions.516// 'q' registers here to save some instructions.
402static INLINE void transpose_u8_8x8(uint8x8_t *a0, uint8x8_t *a1, uint8x8_t *a2,517static INLINE void transpose_u8_8x8(uint8x8_t *a0, uint8x8_t *a1, uint8x8_t *a2,
@@ -509,10 +624,10 @@ static INLINE void transpose_s16_8x8(int16x8_t *a0, int16x8_t *a1, · 106 unmodified lines
509 // d2.val[1]: 06 16 26 36 46 56 66 76624 // d2.val[1]: 06 16 26 36 46 56 66 76
510 // d3.val[0]: 03 13 23 33 43 53 63 73625 // d3.val[0]: 03 13 23 33 43 53 63 73
511 // d3.val[1]: 07 17 27 37 47 57 67 77626 // d3.val[1]: 07 17 27 37 47 57 67 77
512 const int16x8x2_t d0 = vpx_vtrnq_s64(c0.val[0], c2.val[0]);627 const int16x8x2_t d0 = vpx_vtrnq_s64_to_s16(c0.val[0], c2.val[0]);
513 const int16x8x2_t d1 = vpx_vtrnq_s64(c1.val[0], c3.val[0]);628 const int16x8x2_t d1 = vpx_vtrnq_s64_to_s16(c1.val[0], c3.val[0]);
514 const int16x8x2_t d2 = vpx_vtrnq_s64(c0.val[1], c2.val[1]);629 const int16x8x2_t d2 = vpx_vtrnq_s64_to_s16(c0.val[1], c2.val[1]);
515 const int16x8x2_t d3 = vpx_vtrnq_s64(c1.val[1], c3.val[1]);630 const int16x8x2_t d3 = vpx_vtrnq_s64_to_s16(c1.val[1], c3.val[1]);
516 631
517 *a0 = d0.val[0];632 *a0 = d0.val[0];
518 *a1 = d1.val[0];633 *a1 = d1.val[0];
@@ -948,14 +1063,14 @@ static INLINE void transpose_u8_16x16( · 429 unmodified lines
948 // e6.val[1]: 0E 1E 2E 3E 4E 5E 6E 7E 8E 9E AE BE CE DE EE FE1063 // e6.val[1]: 0E 1E 2E 3E 4E 5E 6E 7E 8E 9E AE BE CE DE EE FE
949 // e7.val[0]: 07 17 27 37 47 57 67 77 87 97 A7 B7 C7 D7 E7 F71064 // e7.val[0]: 07 17 27 37 47 57 67 77 87 97 A7 B7 C7 D7 E7 F7
950 // e7.val[1]: 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF1065 // e7.val[1]: 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF
951 const uint8x16x2_t e0 = vpx_vtrnq_u64(d0.val[0], d4.val[0]);1066 const uint8x16x2_t e0 = vpx_vtrnq_u64_to_u8(d0.val[0], d4.val[0]);
952 const uint8x16x2_t e1 = vpx_vtrnq_u64(d2.val[0], d6.val[0]);1067 const uint8x16x2_t e1 = vpx_vtrnq_u64_to_u8(d2.val[0], d6.val[0]);
953 const uint8x16x2_t e2 = vpx_vtrnq_u64(d1.val[0], d5.val[0]);1068 const uint8x16x2_t e2 = vpx_vtrnq_u64_to_u8(d1.val[0], d5.val[0]);
954 const uint8x16x2_t e3 = vpx_vtrnq_u64(d3.val[0], d7.val[0]);1069 const uint8x16x2_t e3 = vpx_vtrnq_u64_to_u8(d3.val[0], d7.val[0]);
955 const uint8x16x2_t e4 = vpx_vtrnq_u64(d0.val[1], d4.val[1]);1070 const uint8x16x2_t e4 = vpx_vtrnq_u64_to_u8(d0.val[1], d4.val[1]);
956 const uint8x16x2_t e5 = vpx_vtrnq_u64(d2.val[1], d6.val[1]);1071 const uint8x16x2_t e5 = vpx_vtrnq_u64_to_u8(d2.val[1], d6.val[1]);
957 const uint8x16x2_t e6 = vpx_vtrnq_u64(d1.val[1], d5.val[1]);1072 const uint8x16x2_t e6 = vpx_vtrnq_u64_to_u8(d1.val[1], d5.val[1]);
958 const uint8x16x2_t e7 = vpx_vtrnq_u64(d3.val[1], d7.val[1]);1073 const uint8x16x2_t e7 = vpx_vtrnq_u64_to_u8(d3.val[1], d7.val[1]);
959 1074
960 // Output:1075 // Output:
961 // o0 : 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F01076 // o0 : 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0
vpx_dsp/vpx_dsp.mk+1−0
@@ -216,6 +216,7 @@ DSP_SRCS-$(HAVE_DSPR2) += mips/itrans32_dspr2.c · 215 unmodified lines
216DSP_SRCS-$(HAVE_DSPR2) += mips/itrans32_cols_dspr2.c216DSP_SRCS-$(HAVE_DSPR2) += mips/itrans32_cols_dspr2.c
217else # CONFIG_VP9_HIGHBITDEPTH217else # CONFIG_VP9_HIGHBITDEPTH
218DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct4x4_add_neon.c218DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct4x4_add_neon.c
219DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct8x8_add_neon.c
219endif # !CONFIG_VP9_HIGHBITDEPTH220endif # !CONFIG_VP9_HIGHBITDEPTH
220 221
221ifeq ($(HAVE_NEON_ASM),yes)222ifeq ($(HAVE_NEON_ASM),yes)
vpx_dsp/vpx_dsp_rtcd_defs.pl+3−2
@@ -621,6 +621,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") { · 620 unmodified lines
621 specialize qw/vpx_highbd_idct4x4_1_add neon/;621 specialize qw/vpx_highbd_idct4x4_1_add neon/;
622 622
623 add_proto qw/void vpx_highbd_idct8x8_1_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";623 add_proto qw/void vpx_highbd_idct8x8_1_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
624 specialize qw/vpx_highbd_idct8x8_1_add neon/;
624 625
625 add_proto qw/void vpx_highbd_idct16x16_1_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";626 add_proto qw/void vpx_highbd_idct16x16_1_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
626 627
@@ -713,10 +714,10 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") { · 86 unmodified lines
713 specialize qw/vpx_highbd_idct4x4_16_add neon sse2/;714 specialize qw/vpx_highbd_idct4x4_16_add neon sse2/;
714 715
715 add_proto qw/void vpx_highbd_idct8x8_64_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";716 add_proto qw/void vpx_highbd_idct8x8_64_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
716 specialize qw/vpx_highbd_idct8x8_64_add sse2/;717 specialize qw/vpx_highbd_idct8x8_64_add neon sse2/;
717 718
718 add_proto qw/void vpx_highbd_idct8x8_12_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";719 add_proto qw/void vpx_highbd_idct8x8_12_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
719 specialize qw/vpx_highbd_idct8x8_12_add sse2/;720 specialize qw/vpx_highbd_idct8x8_12_add neon sse2/;
720 721
721 add_proto qw/void vpx_highbd_idct16x16_256_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";722 add_proto qw/void vpx_highbd_idct16x16_256_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
722 specialize qw/vpx_highbd_idct16x16_256_add sse2/;723 specialize qw/vpx_highbd_idct16x16_256_add sse2/;

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