Unified · Split
| @@ -15,7 +15,7 @@ · 14 unmodified lines | |||
| 15 | 15 | ||
| 16 | #if HAVE_DSPR2 | 16 | #if HAVE_DSPR2 |
| 17 | void vpx_idct4_rows_dspr2(const int16_t *input, int16_t *output) { | 17 | void vpx_idct4_rows_dspr2(const int16_t *input, int16_t *output) { |
| 18 | int16_t step_0, step_1, step_2, step_3; | 18 | int step_0, step_1, step_2, step_3; |
| 19 | int Temp0, Temp1, Temp2, Temp3; | 19 | int Temp0, Temp1, Temp2, Temp3; |
| 20 | const int const_2_power_13 = 8192; | 20 | const int const_2_power_13 = 8192; |
| 21 | int i; | 21 | int i; |
| @@ -97,22 +97,12 @@ void vpx_idct4_rows_dspr2(const int16_t *input, int16_t *output) { · 75 unmodified lines | |||
| 97 | 97 | ||
| 98 | void vpx_idct4_columns_add_blk_dspr2(int16_t *input, uint8_t *dest, | 98 | void vpx_idct4_columns_add_blk_dspr2(int16_t *input, uint8_t *dest, |
| 99 | int stride) { | 99 | int stride) { |
| 100 | int16_t step_0, step_1, step_2, step_3; | 100 | int step_0, step_1, step_2, step_3; |
| 101 | int Temp0, Temp1, Temp2, Temp3; | 101 | int Temp0, Temp1, Temp2, Temp3; |
| 102 | const int const_2_power_13 = 8192; | 102 | const int const_2_power_13 = 8192; |
| 103 | const int const_255 = 255; | ||
| 103 | int i; | 104 | int i; |
| 104 | uint8_t *dest_pix; | 105 | uint8_t *dest_pix; |
| 105 | uint8_t *cm = vpx_ff_cropTbl; | ||
| 106 | |||
| 107 | /* prefetch vpx_ff_cropTbl */ | ||
| 108 | prefetch_load(vpx_ff_cropTbl); | ||
| 109 | prefetch_load(vpx_ff_cropTbl + 32); | ||
| 110 | prefetch_load(vpx_ff_cropTbl + 64); | ||
| 111 | prefetch_load(vpx_ff_cropTbl + 96); | ||
| 112 | prefetch_load(vpx_ff_cropTbl + 128); | ||
| 113 | prefetch_load(vpx_ff_cropTbl + 160); | ||
| 114 | prefetch_load(vpx_ff_cropTbl + 192); | ||
| 115 | prefetch_load(vpx_ff_cropTbl + 224); | ||
| 116 | 106 | ||
| 117 | for (i = 0; i < 4; ++i) { | 107 | for (i = 0; i < 4; ++i) { |
| 118 | dest_pix = (dest + i); | 108 | dest_pix = (dest + i); |
| @@ -172,43 +162,55 @@ void vpx_idct4_columns_add_blk_dspr2(int16_t *input, uint8_t *dest, · 53 unmodified lines | |||
| 172 | "sra %[Temp0], %[Temp0], 4 \n\t" | 162 | "sra %[Temp0], %[Temp0], 4 \n\t" |
| 173 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" | 163 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" |
| 174 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" | 164 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" |
| 175 | "add %[Temp0], %[step_1], %[step_2] \n\t" | 165 | "slt %[Temp2], %[Temp1], %[const_255] \n\t" |
| 176 | "lbux %[Temp2], %[Temp1](%[cm]) \n\t" | 166 | "slt %[Temp3], $zero, %[Temp1] \n\t" |
| 177 | "sb %[Temp2], 0(%[dest_pix]) \n\t" | 167 | "movz %[Temp1], %[const_255], %[Temp2] \n\t" |
| 168 | "movz %[Temp1], $zero, %[Temp3] \n\t" | ||
| 169 | "sb %[Temp1], 0(%[dest_pix]) \n\t" | ||
| 178 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" | 170 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" |
| 179 | 171 | ||
| 172 | "add %[Temp0], %[step_1], %[step_2] \n\t" | ||
| 180 | "addi %[Temp0], %[Temp0], 8 \n\t" | 173 | "addi %[Temp0], %[Temp0], 8 \n\t" |
| 181 | "sra %[Temp0], %[Temp0], 4 \n\t" | 174 | "sra %[Temp0], %[Temp0], 4 \n\t" |
| 182 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" | 175 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" |
| 183 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" | 176 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" |
| 184 | "sub %[Temp0], %[step_1], %[step_2] \n\t" | 177 | "slt %[Temp2], %[Temp1], %[const_255] \n\t" |
| 185 | "lbux %[Temp2], %[Temp1](%[cm]) \n\t" | 178 | "slt %[Temp3], $zero, %[Temp1] \n\t" |
| 186 | "sb %[Temp2], 0(%[dest_pix]) \n\t" | 179 | "movz %[Temp1], %[const_255], %[Temp2] \n\t" |
| 180 | "movz %[Temp1], $zero, %[Temp3] \n\t" | ||
| 181 | "sb %[Temp1], 0(%[dest_pix]) \n\t" | ||
| 187 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" | 182 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" |
| 188 | 183 | ||
| 184 | "sub %[Temp0], %[step_1], %[step_2] \n\t" | ||
| 189 | "addi %[Temp0], %[Temp0], 8 \n\t" | 185 | "addi %[Temp0], %[Temp0], 8 \n\t" |
| 190 | "sra %[Temp0], %[Temp0], 4 \n\t" | 186 | "sra %[Temp0], %[Temp0], 4 \n\t" |
| 191 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" | 187 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" |
| 192 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" | 188 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" |
| 193 | "sub %[Temp0], %[step_0], %[step_3] \n\t" | 189 | "slt %[Temp2], %[Temp1], %[const_255] \n\t" |
| 194 | "lbux %[Temp2], %[Temp1](%[cm]) \n\t" | 190 | "slt %[Temp3], $zero, %[Temp1] \n\t" |
| 195 | "sb %[Temp2], 0(%[dest_pix]) \n\t" | 191 | "movz %[Temp1], %[const_255], %[Temp2] \n\t" |
| 192 | "movz %[Temp1], $zero, %[Temp3] \n\t" | ||
| 193 | "sb %[Temp1], 0(%[dest_pix]) \n\t" | ||
| 196 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" | 194 | "addu %[dest_pix], %[dest_pix], %[stride] \n\t" |
| 197 | 195 | ||
| 196 | "sub %[Temp0], %[step_0], %[step_3] \n\t" | ||
| 198 | "addi %[Temp0], %[Temp0], 8 \n\t" | 197 | "addi %[Temp0], %[Temp0], 8 \n\t" |
| 199 | "sra %[Temp0], %[Temp0], 4 \n\t" | 198 | "sra %[Temp0], %[Temp0], 4 \n\t" |
| 200 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" | 199 | "lbu %[Temp1], 0(%[dest_pix]) \n\t" |
| 201 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" | 200 | "add %[Temp1], %[Temp1], %[Temp0] \n\t" |
| 202 | "lbux %[Temp2], %[Temp1](%[cm]) \n\t" | 201 | "slt %[Temp2], %[Temp1], %[const_255] \n\t" |
| 203 | "sb %[Temp2], 0(%[dest_pix]) \n\t" | 202 | "slt %[Temp3], $zero, %[Temp1] \n\t" |
| 203 | "movz %[Temp1], %[const_255], %[Temp2] \n\t" | ||
| 204 | "movz %[Temp1], $zero, %[Temp3] \n\t" | ||
| 205 | "sb %[Temp1], 0(%[dest_pix]) \n\t" | ||
| 204 | 206 | ||
| 205 | : [Temp0] "=&r"(Temp0), [Temp1] "=&r"(Temp1), [Temp2] "=&r"(Temp2), | 207 | : [Temp0] "=&r"(Temp0), [Temp1] "=&r"(Temp1), [Temp2] "=&r"(Temp2), |
| 206 | [Temp3] "=&r"(Temp3), [step_0] "=&r"(step_0), [step_1] "=&r"(step_1), | 208 | [Temp3] "=&r"(Temp3), [step_0] "=&r"(step_0), [step_1] "=&r"(step_1), |
| 207 | [step_2] "=&r"(step_2), [step_3] "=&r"(step_3), | 209 | [step_2] "=&r"(step_2), [step_3] "=&r"(step_3), |
| 208 | [dest_pix] "+r"(dest_pix) | 210 | [dest_pix] "+r"(dest_pix) |
| 209 | : [const_2_power_13] "r"(const_2_power_13), | 211 | : [const_2_power_13] "r"(const_2_power_13), [const_255] "r"(const_255), |
| 210 | [cospi_8_64] "r"(cospi_8_64), [cospi_16_64] "r"(cospi_16_64), | 212 | [cospi_8_64] "r"(cospi_8_64), [cospi_16_64] "r"(cospi_16_64), |
| 211 | [cospi_24_64] "r"(cospi_24_64), [input] "r"(input), [cm] "r"(cm), | 213 | [cospi_24_64] "r"(cospi_24_64), [input] "r"(input), |
| 212 | [stride] "r"(stride)); | 214 | [stride] "r"(stride)); |
| 213 | 215 | ||
| 214 | input += 4; | 216 | input += 4; |
| @@ -274,6 +276,39 @@ void vpx_idct4x4_1_add_dspr2(const int16_t *input, uint8_t *dest, int stride) { · 59 unmodified lines | |||
| 274 | : [t2] "=&r"(t2), [vector_a] "=&r"(vector_a), [dest] "+&r"(dest) | 276 | : [t2] "=&r"(t2), [vector_a] "=&r"(vector_a), [dest] "+&r"(dest) |
| 275 | : [stride] "r"(stride), [vector_a1] "r"(vector_a1)); | 277 | : [stride] "r"(stride), [vector_a1] "r"(vector_a1)); |
| 276 | } | 278 | } |
| 279 | } else if (a1 > 255) { | ||
| 280 | int32_t a11, a12, vector_a11, vector_a12; | ||
| 281 | |||
| 282 | /* use quad-byte | ||
| 283 | * input and output memory are four byte aligned */ | ||
| 284 | a11 = a1 >> 3; | ||
| 285 | a12 = a1 - (a11 * 7); | ||
| 286 | |||
| 287 | __asm__ __volatile__( | ||
| 288 | "replv.qb %[vector_a11], %[a11] \n\t" | ||
| 289 | "replv.qb %[vector_a12], %[a12] \n\t" | ||
| 290 | |||
| 291 | : [vector_a11] "=&r"(vector_a11), [vector_a12] "=&r"(vector_a12) | ||
| 292 | : [a11] "r"(a11), [a12] "r"(a12)); | ||
| 293 | |||
| 294 | for (r = 4; r--;) { | ||
| 295 | __asm__ __volatile__( | ||
| 296 | "lw %[t2], 4(%[dest]) \n\t" | ||
| 297 | "addu_s.qb %[vector_a], %[t2], %[vector_a11] \n\t" | ||
| 298 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 299 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 300 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 301 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 302 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 303 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a11] \n\t" | ||
| 304 | "addu_s.qb %[vector_a], %[vector_a], %[vector_a12] \n\t" | ||
| 305 | "sw %[vector_a], 0(%[dest]) \n\t" | ||
| 306 | "add %[dest], %[dest], %[stride] \n\t" | ||
| 307 | |||
| 308 | : [t2] "=&r"(t2), [vector_a] "=&r"(vector_a), [dest] "+&r"(dest) | ||
| 309 | : [stride] "r"(stride), [vector_a11] "r"(vector_a11), | ||
| 310 | [vector_a12] "r"(vector_a12)); | ||
| 311 | } | ||
| 277 | } else { | 312 | } else { |
| 278 | /* use quad-byte | 313 | /* use quad-byte |
| 279 | * input and output memory are four byte aligned */ | 314 | * input and output memory are four byte aligned */ |