Unified · Split
| @@ -624,6 +624,38 @@ INSTANTIATE_TEST_CASE_P(SSSE3, PartialIDctTest, · 623 unmodified lines | ||
| 624 | 624 | ::testing::ValuesIn(ssse3_partial_idct_tests)); |
| 625 | 625 | #endif // HAVE_SSSE3 && ARCH_X86_64 && !CONFIG_EMULATE_HARDWARE |
| 626 | 626 | |
| 627 | +#if HAVE_DSPR2 && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH | |
| 628 | +const PartialInvTxfmParam dspr2_partial_idct_tests[] = { | |
| 629 | + make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>, | |
| 630 | + &wrapper<vpx_idct32x32_1024_add_dspr2>, TX_32X32, 1024, 8, 1), | |
| 631 | + make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>, | |
| 632 | + &wrapper<vpx_idct32x32_1024_add_dspr2>, TX_32X32, 135, 8, 1), | |
| 633 | + make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>, | |
| 634 | + &wrapper<vpx_idct32x32_34_add_dspr2>, TX_32X32, 34, 8, 1), | |
| 635 | + make_tuple(&vpx_fdct32x32_c, &wrapper<vpx_idct32x32_1024_add_c>, | |
| 636 | + &wrapper<vpx_idct32x32_1_add_dspr2>, TX_32X32, 1, 8, 1), | |
| 637 | + make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>, | |
| 638 | + &wrapper<vpx_idct16x16_256_add_dspr2>, TX_16X16, 256, 8, 1), | |
| 639 | + make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>, | |
| 640 | + &wrapper<vpx_idct16x16_10_add_dspr2>, TX_16X16, 10, 8, 1), | |
| 641 | + make_tuple(&vpx_fdct16x16_c, &wrapper<vpx_idct16x16_256_add_c>, | |
| 642 | + &wrapper<vpx_idct16x16_1_add_dspr2>, TX_16X16, 1, 8, 1), | |
| 643 | + make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>, | |
| 644 | + &wrapper<vpx_idct8x8_64_add_dspr2>, TX_8X8, 64, 8, 1), | |
| 645 | + make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>, | |
| 646 | + &wrapper<vpx_idct8x8_12_add_dspr2>, TX_8X8, 12, 8, 1), | |
| 647 | + make_tuple(&vpx_fdct8x8_c, &wrapper<vpx_idct8x8_64_add_c>, | |
| 648 | + &wrapper<vpx_idct8x8_1_add_dspr2>, TX_8X8, 1, 8, 1), | |
| 649 | + make_tuple(&vpx_fdct4x4_c, &wrapper<vpx_idct4x4_16_add_c>, | |
| 650 | + &wrapper<vpx_idct4x4_16_add_dspr2>, TX_4X4, 16, 8, 1), | |
| 651 | + make_tuple(&vpx_fdct4x4_c, &wrapper<vpx_idct4x4_16_add_c>, | |
| 652 | + &wrapper<vpx_idct4x4_1_add_dspr2>, TX_4X4, 1, 8, 1) | |
| 653 | +}; | |
| 654 | + | |
| 655 | +INSTANTIATE_TEST_CASE_P(DSPR2, PartialIDctTest, | |
| 656 | + ::testing::ValuesIn(dspr2_partial_idct_tests)); | |
| 657 | +#endif // HAVE_DSPR2 && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH | |
| 658 | + | |
| 627 | 659 | #if HAVE_MSA && !CONFIG_EMULATE_HARDWARE && !CONFIG_VP9_HIGHBITDEPTH |
| 628 | 660 | // 32x32_135_ is implemented using the 1024 version. |
| 629 | 661 | const PartialInvTxfmParam msa_partial_idct_tests[] = { |