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add new c and assembly functions to optimize downsampler when downscale equal 1:3/1:4

Guangwei Wang committed 11 years ago

Commit 64657d31 parent 69a62ea9 files · +1125 −8Browse files

Showing the changes to codec/processing/src/arm64 (1 of 9 files). Show all

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codec/processing/src/arm64/down_sample_aarch64_neon.S+107−1
@@ -84,7 +84,6 @@ comp_ds_bilinear_loop0: · 83 unmodified lines
8484
8585 WELS_ASM_AARCH64_FUNC_END
8686
87−
8887 WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearDownsamplerWidthx32_AArch64_neon
8988 sub w9, w3, w4
9089 sub w1, w1, w4, lsr #1
@@ -123,6 +122,113 @@ comp_ds_bilinear_w_x32_loop1: · 32 unmodified lines
123122 cbnz w5, comp_ds_bilinear_w_x32_loop0
124123 WELS_ASM_AARCH64_FUNC_END
125124
125+WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearOneThirdDownsampler_AArch64_neon
126+
127+ //Initialize the register
128+ mov x6, x2
129+ mov x8, x0
130+ mov w9, #0
131+
132+ //Save the tailer for the unasigned size
133+ smaddl x7, w1, w5, x0
134+ ld1 {v16.16b}, [x7]
135+
136+ add x7, x2, w3, sxtw
137+ //processing a colume data
138+comp_ds_bilinear_onethird_loop0:
139+
140+ ld3 {v0.16b, v1.16b, v2.16b}, [x2], #48
141+ ld3 {v4.16b, v5.16b, v6.16b}, [x7], #48
142+
143+ uaddl v2.8h, v0.8b, v1.8b
144+ uaddl2 v3.8h, v0.16b, v1.16b
145+ uaddl v6.8h, v4.8b, v5.8b
146+ uaddl2 v7.8h, v4.16b, v5.16b
147+ urshr v2.8h, v2.8h, #1
148+ urshr v3.8h, v3.8h, #1
149+ urshr v6.8h, v6.8h, #1
150+ urshr v7.8h, v7.8h, #1
151+
152+ urhadd v0.8h, v2.8h, v6.8h
153+ urhadd v1.8h, v3.8h, v7.8h
154+ xtn v0.8b, v0.8h
155+ xtn v1.8b, v1.8h
156+ st1 {v0.8b,v1.8b}, [x0], #16
157+
158+ add w9, w9, #48
159+
160+ cmp w9, w4
161+ b.cc comp_ds_bilinear_onethird_loop0
162+
163+ mov w9, #0
164+ add x6, x6, w3, sxtw #1
165+ add x6, x6, w3, sxtw
166+ mov x2, x6
167+ add x7, x2, w3, sxtw
168+ add x8, x8, w1, sxtw
169+ mov x0, x8
170+ sub w5, w5, #1
171+
172+ cbnz w5, comp_ds_bilinear_onethird_loop0
173+
174+ //restore the tailer for the unasigned size
175+ st1 {v16.16b}, [x0]
176+WELS_ASM_AARCH64_FUNC_END
177+
178+WELS_ASM_AARCH64_FUNC_BEGIN DyadicBilinearQuarterDownsampler_AArch64_neon
179+ //Initialize the register
180+ mov x6, x2
181+ mov x8, x0
182+ mov w9, #0
183+ lsr w5, w5, #2
184+
185+ //Save the tailer for the unasigned size
186+ smaddl x7, w1, w5, x0
187+ ld1 {v16.16b}, [x7]
188+
189+ add x7, x2, w3, sxtw
190+ //processing a colume data
191+comp_ds_bilinear_quarter_loop0:
192+
193+ ld2 {v0.8h, v1.8h}, [x2], #32
194+ ld2 {v2.8h, v3.8h}, [x2], #32
195+ ld2 {v4.8h, v5.8h}, [x7], #32
196+ ld2 {v6.8h, v7.8h}, [x7], #32
197+
198+ uaddlp v0.8h, v0.16b
199+ uaddlp v1.8h, v2.16b
200+ uaddlp v4.8h, v4.16b
201+ uaddlp v5.8h, v6.16b
202+ urshr v0.8h, v0.8h, #1
203+ urshr v1.8h, v1.8h, #1
204+ urshr v4.8h, v4.8h, #1
205+ urshr v5.8h, v5.8h, #1
206+
207+ urhadd v0.8h, v0.8h, v4.8h
208+ urhadd v1.8h, v1.8h, v5.8h
209+ xtn v0.8b, v0.8h
210+ xtn v1.8b, v1.8h
211+ st1 {v0.8b,v1.8b}, [x0], #16
212+
213+ add w9, w9, #64
214+
215+ cmp w9, w4
216+ b.cc comp_ds_bilinear_quarter_loop0
217+
218+ mov w9, #0
219+ add x6, x6, w3, sxtw #2
220+ mov x2, x6
221+ add x7, x2, w3, sxtw
222+ add x8, x8, w1, sxtw
223+ mov x0, x8
224+ sub w5, w5, #1
225+
226+ cbnz w5, comp_ds_bilinear_quarter_loop0
227+
228+ //restore the tailer for the unasigned size
229+ st1 {v16.16b}, [x0]
230+WELS_ASM_AARCH64_FUNC_END
231+
126232 WELS_ASM_AARCH64_FUNC_BEGIN GeneralBilinearAccurateDownsampler_AArch64_neon
127233 mov w10, #32767
128234 and w8, w6, w10

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