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Merge pull request #1218 from zhilwang/arm64_vaa

Arm64 vaa

huili2 committed 12 years ago

Commit 8e2d92e2 parents 91bbd18 79328455 files · +592 −0Browse files

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  1. codec/processing/src/arm64/vaa_calc_aarch64_neon.S +567 −0
  2. codec/processing/src/vaacalc/vaacalculation.cpp +10 −0
  3. codec/processing/src/vaacalc/vaacalculation.h +10 −0
codec/processing/src/arm64/vaa_calc_aarch64_neon.S+567−0
@@ -0,0 +1,567 @@
1+/*!
2+ * \copy
3+ * Copyright (c) 2013, Cisco Systems
4+ * All rights reserved.
5+ *
6+ * Redistribution and use in source and binary forms, with or without
7+ * modification, are permitted provided that the following conditions
8+ * are met:
9+ *
10+ * * Redistributions of source code must retain the above copyright
11+ * notice, this list of conditions and the following disclaimer.
12+ *
13+ * * Redistributions in binary form must reproduce the above copyright
14+ * notice, this list of conditions and the following disclaimer in
15+ * the documentation and/or other materials provided with the
16+ * distribution.
17+ *
18+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29+ * POSSIBILITY OF SUCH DAMAGE.
30+ *
31+ */
32+
33+#ifdef HAVE_NEON_AARCH64
34+.text
35+#include "arm_arch64_common_macro.S"
36+
37+#ifdef __APPLE__
38+.macro ABS_SUB_SUM_16BYTES
39+ ld1 {v0.16b}, [x0], x4
40+ ld1 {v1.16b}, [x1], x4
41+ uabal $0, v0.8b, v1.8b
42+ uabal2 $1, v0.16b,v1.16b
43+.endm
44+
45+.macro ABS_SUB_SUM_8x16BYTES
46+ ld1 {v0.16b}, [x0], x4
47+ ld1 {v1.16b}, [x1], x4
48+ uabdl $0, v0.8b, v1.8b
49+ uabdl2 $1, v0.16b,v1.16b
50+
51+ ABS_SUB_SUM_16BYTES $0, $1
52+ ABS_SUB_SUM_16BYTES $0, $1
53+ ABS_SUB_SUM_16BYTES $0, $1
54+ ABS_SUB_SUM_16BYTES $0, $1
55+ ABS_SUB_SUM_16BYTES $0, $1
56+ ABS_SUB_SUM_16BYTES $0, $1
57+ ABS_SUB_SUM_16BYTES $0, $1
58+.endm
59+#else
60+.macro ABS_SUB_SUM_16BYTES arg0, arg1
61+ ld1 {v0.16b}, [x0], x4
62+ ld1 {v1.16b}, [x1], x4
63+ uabal \arg0, v0.8b, v1.8b
64+ uabal2 \arg1, v0.16b,v1.16b
65+.endm
66+
67+.macro ABS_SUB_SUM_8x16BYTES arg0, arg1
68+ ld1 {v0.16b}, [x0], x4
69+ ld1 {v1.16b}, [x1], x4
70+ uabdl \arg0, v0.8b, v1.8b
71+ uabdl2 \arg1, v0.16b,v1.16b
72+
73+ ABS_SUB_SUM_16BYTES \arg0, \arg1
74+ ABS_SUB_SUM_16BYTES \arg0, \arg1
75+ ABS_SUB_SUM_16BYTES \arg0, \arg1
76+ ABS_SUB_SUM_16BYTES \arg0, \arg1
77+ ABS_SUB_SUM_16BYTES \arg0, \arg1
78+ ABS_SUB_SUM_16BYTES \arg0, \arg1
79+ ABS_SUB_SUM_16BYTES \arg0, \arg1
80+#endif
81+
82+/*
83+ * void vaa_calc_sad_neon(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
84+ * int32_t *psadframe, int32_t *psad8x8)
85+ */
86+WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSad_AArch64_neon
87+ eor v31.16b, v31.16b, v31.16b
88+ lsl x9, x4, #4
89+ sub x10, x9, #16 //x10 keep the 16*pic_stride-16
90+ sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
91+vaa_calc_sad_loop0:
92+ mov w11, w2
93+vaa_calc_sad_loop1:
94+ ABS_SUB_SUM_8x16BYTES v2.8h, v3.8h
95+ ABS_SUB_SUM_8x16BYTES v4.8h, v5.8h
96+
97+ uaddlv s2, v2.8h
98+ uaddlv s3, v3.8h
99+ uaddlv s4, v4.8h
100+ uaddlv s5, v5.8h
101+
102+ st4 {v2.s, v3.s, v4.s, v5.s}[0], [x6], #16
103+ sub x0, x0, x10
104+ sub x1, x1, x10
105+ sub w11, w11, #16
106+ add v6.2s, v2.2s, v3.2s
107+ add v7.2s, v4.2s, v5.2s
108+ add v6.2s, v6.2s, v7.2s
109+ add v31.2s, v31.2s, v6.2s
110+ cbnz w11, vaa_calc_sad_loop1
111+
112+ add x0, x0, x9
113+ add x1, x1, x9
114+ sub w3, w3, #16
115+ cbnz w3, vaa_calc_sad_loop0
116+
117+ str s31, [x5]
118+
119+WELS_ASM_AARCH64_FUNC_END
120+
121+.macro SAD_SD_MAD_8x16BYTES
122+ ld1 {v0.16b}, [x0], x4
123+ ld1 {v1.16b}, [x1], x4
124+ uabd v31.16b, v0.16b, v1.16b
125+ uaddlp v2.8h, v31.16b
126+ uaddlp v4.8h, v0.16b
127+ uaddlp v5.8h, v1.16b
128+.rept 7
129+ ld1 {v0.16b}, [x0], x4
130+ ld1 {v1.16b}, [x1], x4
131+ uabd v30.16b, v0.16b, v1.16b
132+ umax v31.16b, v31.16b,v30.16b
133+ uadalp v2.8h, v30.16b
134+ uadalp v4.8h, v0.16b
135+ uadalp v5.8h, v1.16b
136+.endr
137+.endm
138+/*
139+ * void vaa_calc_sad_bgd_neon(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
140+ * int32_t *psadframe, int32_t *psad8x8, int32_t *p_sd8x8, uint8_t *p_mad8x8)
141+ */
142+WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadBgd_AArch64_neon
143+ ldr x15, [sp, #0]
144+ eor v28.16b, v28.16b, v28.16b
145+
146+ lsl x9, x4, #4
147+ sub x10, x9, #16 //x10 keep the 16*pic_stride-16
148+ sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
149+vaa_calc_sad_bgd_loop0:
150+ mov w11, w2
151+vaa_calc_sad_bgd_loop1:
152+ SAD_SD_MAD_8x16BYTES
153+ umaxv b24, v31.8b
154+ ins v31.d[0], v31.d[1]
155+ umaxv b25, v31.8b
156+ uaddlv s20, v2.4h
157+ ins v2.d[0], v2.d[1]
158+ uaddlv s21, v2.4h
159+ usubl v6.4s, v4.4h, v5.4h
160+ usubl2 v7.4s, v4.8h, v5.8h
161+ addv s16, v6.4s
162+ addv s17, v7.4s
163+
164+ SAD_SD_MAD_8x16BYTES
165+ umaxv b26, v31.8b
166+ ins v31.d[0], v31.d[1]
167+ umaxv b27, v31.8b
168+ uaddlv s22, v2.4h
169+ ins v2.d[0], v2.d[1]
170+ uaddlv s23, v2.4h
171+ usubl v6.4s, v4.4h, v5.4h
172+ usubl2 v7.4s, v4.8h, v5.8h
173+ addv s18, v6.4s
174+ addv s19, v7.4s
175+ st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
176+
177+ sub x0, x0, x10
178+ sub x1, x1, x10
179+ st4 {v16.s, v17.s, v18.s, v19.s}[0], [x7], #16
180+ sub w11, w11, #16
181+ st4 {v24.b, v25.b, v26.b, v27.b}[0], [x15], #4
182+ add v29.2s, v20.2s, v21.2s
183+ add v30.2s, v22.2s, v23.2s
184+ add v29.2s, v29.2s, v30.2s
185+ add v28.2s, v28.2s, v29.2s
186+ cbnz w11, vaa_calc_sad_bgd_loop1
187+
188+ add x0, x0, x9
189+ add x1, x1, x9
190+ sub w3, w3, #16
191+ cbnz w3, vaa_calc_sad_bgd_loop0
192+ str s28, [x5]
193+
194+WELS_ASM_AARCH64_FUNC_END
195+
196+.macro SAD_SSD_BGD_8x16BYTES_1
197+ ld1 {v0.16b}, [x0], x4
198+ ld1 {v1.16b}, [x1], x4
199+ uabd v31.16b, v0.16b, v1.16b
200+ umull v30.8h, v31.8b, v31.8b
201+ uaddlp v29.4s, v30.8h
202+ umull2 v30.8h, v31.16b, v31.16b
203+ uadalp v29.4s, v30.8h // p_sqdiff
204+
205+ uaddlp v28.8h, v0.16b // p_sum
206+ umull v30.8h, v0.8b, v0.8b
207+ uaddlp v27.4s, v30.8h
208+ umull2 v30.8h, v0.16b, v0.16b
209+ uadalp v27.4s, v30.8h // p_sqsum
210+
211+ uaddlp v2.8h, v31.16b // p_sad
212+ uaddlp v4.8h, v0.16b
213+ uaddlp v5.8h, v1.16b
214+.rept 7
215+ ld1 {v0.16b}, [x0], x4
216+ ld1 {v1.16b}, [x1], x4
217+ uabd v3.16b, v0.16b, v1.16b
218+ umax v31.16b, v31.16b,v3.16b //p_mad
219+ umull v30.8h, v3.8b, v3.8b
220+ uadalp v29.4s, v30.8h
221+ umull2 v30.8h, v3.16b, v3.16b
222+ uadalp v29.4s, v30.8h // p_sqdiff
223+
224+ uadalp v28.8h, v0.16b // p_sum
225+ umull v30.8h, v0.8b, v0.8b
226+ uadalp v27.4s, v30.8h
227+ umull2 v30.8h, v0.16b, v0.16b
228+ uadalp v27.4s, v30.8h // p_sqsum
229+
230+ uadalp v2.8h, v3.16b //p_sad
231+ uadalp v4.8h, v0.16b
232+ uadalp v5.8h, v1.16b //p_sd
233+.endr
234+.endm
235+
236+.macro SAD_SSD_BGD_8x16BYTES_2
237+ ld1 {v0.16b}, [x0], x4
238+ ld1 {v1.16b}, [x1], x4
239+ uabd v26.16b, v0.16b, v1.16b
240+ umull v30.8h, v26.8b, v26.8b
241+ uadalp v29.4s, v30.8h
242+ umull2 v30.8h, v26.16b, v26.16b
243+ uadalp v29.4s, v30.8h // p_sqdiff
244+
245+ uadalp v28.8h, v0.16b // p_sum
246+ umull v30.8h, v0.8b, v0.8b
247+ uadalp v27.4s, v30.8h
248+ umull2 v30.8h, v0.16b, v0.16b
249+ uadalp v27.4s, v30.8h // p_sqsum
250+
251+ uaddlp v16.8h,v26.16b // p_sad
252+ uaddlp v6.8h, v0.16b
253+ uaddlp v7.8h, v1.16b
254+.rept 7
255+ ld1 {v0.16b}, [x0], x4
256+ ld1 {v1.16b}, [x1], x4
257+ uabd v3.16b, v0.16b, v1.16b
258+ umax v26.16b, v26.16b,v3.16b //p_mad
259+ umull v30.8h, v3.8b, v3.8b
260+ uadalp v29.4s, v30.8h
261+ umull2 v30.8h, v3.16b, v3.16b
262+ uadalp v29.4s, v30.8h // p_sqdiff
263+
264+ uadalp v28.8h, v0.16b // p_sum
265+ umull v30.8h, v0.8b, v0.8b
266+ uadalp v27.4s, v30.8h
267+ umull2 v30.8h, v0.16b, v0.16b
268+ uadalp v27.4s, v30.8h // p_sqsum
269+
270+ uadalp v16.8h, v3.16b //p_sad
271+ uadalp v6.8h, v0.16b
272+ uadalp v7.8h, v1.16b //p_sd
273+.endr
274+.endm
275+
276+/*
277+ * void vaa_calc_sad_ssd_bgd_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
278+ * int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16, int32_t *psqdiff16x16, int32_t *p_sd8x8, uint8_t *p_mad8x8)
279+ */
280+WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadSsdBgd_AArch64_neon
281+ ldr x12, [sp, #0] //psqsum16x16
282+ ldr x13, [sp, #8] //psqdiff16x16
283+ ldr x14, [sp, #16] //p_sd8x8
284+ ldr x15, [sp, #24] //p_mad8x8
285+ eor v17.16b, v17.16b, v17.16b
286+
287+ lsl x9, x4, #4
288+ sub x10, x9, #16 //x10 keep the 16*pic_stride-16
289+ sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
290+
291+vaa_calc_sad_ssd_bgd_height_loop:
292+ mov w11, w2
293+vaa_calc_sad_ssd_bgd_width_loop:
294+ SAD_SSD_BGD_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27, psqdiff:v29, psd:v4, v5, v6, v7, pmad:v31, v26
295+ SAD_SSD_BGD_8x16BYTES_2
296+
297+ umaxv b22, v31.8b
298+ ins v31.d[0], v31.d[1]
299+ umaxv b23, v31.8b
300+ umaxv b24, v26.8b
301+ ins v26.d[0], v26.d[1]
302+ umaxv b25, v26.8b
303+ st4 {v22.b, v23.b, v24.b, v25.b}[0], [x15], #4
304+
305+ usubl v20.4s, v4.4h, v5.4h
306+ usubl2 v21.4s, v4.8h, v5.8h
307+ addv s20, v20.4s
308+ addv s21, v21.4s
309+ usubl v22.4s, v6.4h, v7.4h
310+ usubl2 v23.4s, v6.8h, v7.8h
311+ addv s22, v22.4s
312+ addv s23, v23.4s
313+ st4 {v20.s, v21.s, v22.s, v23.s}[0], [x14], #16
314+
315+ uaddlv s20, v2.4h
316+ ins v2.d[0], v2.d[1]
317+ uaddlv s21, v2.4h
318+ uaddlv s22, v16.4h
319+ ins v16.d[0], v16.d[1]
320+ uaddlv s23, v16.4h
321+ st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
322+
323+ uaddlv s28, v28.8h
324+ str s28, [x7], #4
325+ addv s27, v27.4s
326+ str s27, [x12], #4
327+ addv s29, v29.4s
328+ str s29, [x13], #4
329+
330+ sub x0, x0, x10
331+ sub x1, x1, x10
332+ sub w11, w11, #16
333+ add v29.2s, v20.2s, v21.2s
334+ add v30.2s, v22.2s, v23.2s
335+ add v29.2s, v29.2s, v30.2s
336+ add v17.2s, v17.2s, v29.2s
337+ cbnz w11, vaa_calc_sad_ssd_bgd_width_loop
338+
339+ add x0, x0, x9
340+ add x1, x1, x9
341+ sub w3, w3, #16
342+ cbnz w3, vaa_calc_sad_ssd_bgd_height_loop
343+ str s17, [x5]
344+WELS_ASM_AARCH64_FUNC_END
345+
346+
347+.macro SAD_SSD_8x16BYTES_1
348+ ld1 {v0.16b}, [x0], x4
349+ ld1 {v1.16b}, [x1], x4
350+ uabd v31.16b, v0.16b, v1.16b
351+ umull v30.8h, v31.8b, v31.8b
352+ uaddlp v29.4s, v30.8h
353+ umull2 v30.8h, v31.16b, v31.16b
354+ uadalp v29.4s, v30.8h // p_sqdiff
355+
356+ uaddlp v28.8h, v0.16b // p_sum
357+ umull v30.8h, v0.8b, v0.8b
358+ uaddlp v27.4s, v30.8h
359+ umull2 v30.8h, v0.16b, v0.16b
360+ uadalp v27.4s, v30.8h // p_sqsum
361+
362+ uaddlp v2.8h, v31.16b // p_sad
363+.rept 7
364+ ld1 {v0.16b}, [x0], x4
365+ ld1 {v1.16b}, [x1], x4
366+ uabd v3.16b, v0.16b, v1.16b
367+ umull v30.8h, v3.8b, v3.8b
368+ uadalp v29.4s, v30.8h
369+ umull2 v30.8h, v3.16b, v3.16b
370+ uadalp v29.4s, v30.8h // p_sqdiff
371+
372+ uadalp v28.8h, v0.16b // p_sum
373+ umull v30.8h, v0.8b, v0.8b
374+ uadalp v27.4s, v30.8h
375+ umull2 v30.8h, v0.16b, v0.16b
376+ uadalp v27.4s, v30.8h // p_sqsum
377+
378+ uadalp v2.8h, v3.16b //p_sad
379+.endr
380+.endm
381+
382+.macro SAD_SSD_8x16BYTES_2
383+ ld1 {v0.16b}, [x0], x4
384+ ld1 {v1.16b}, [x1], x4
385+ uabd v26.16b, v0.16b, v1.16b
386+ umull v30.8h, v26.8b, v26.8b
387+ uadalp v29.4s, v30.8h
388+ umull2 v30.8h, v26.16b, v26.16b
389+ uadalp v29.4s, v30.8h // p_sqdiff
390+
391+ uadalp v28.8h, v0.16b // p_sum
392+ umull v30.8h, v0.8b, v0.8b
393+ uadalp v27.4s, v30.8h
394+ umull2 v30.8h, v0.16b, v0.16b
395+ uadalp v27.4s, v30.8h // p_sqsum
396+
397+ uaddlp v16.8h,v26.16b // p_sad
398+ uaddlp v6.8h, v0.16b
399+ uaddlp v7.8h, v1.16b
400+.rept 7
401+ ld1 {v0.16b}, [x0], x4
402+ ld1 {v1.16b}, [x1], x4
403+ uabd v3.16b, v0.16b, v1.16b
404+ umull v30.8h, v3.8b, v3.8b
405+ uadalp v29.4s, v30.8h
406+ umull2 v30.8h, v3.16b, v3.16b
407+ uadalp v29.4s, v30.8h // p_sqdiff
408+
409+ uadalp v28.8h, v0.16b // p_sum
410+ umull v30.8h, v0.8b, v0.8b
411+ uadalp v27.4s, v30.8h
412+ umull2 v30.8h, v0.16b, v0.16b
413+ uadalp v27.4s, v30.8h // p_sqsum
414+
415+ uadalp v16.8h, v3.16b //p_sad
416+.endr
417+.endm
418+/*
419+ * void vaa_calc_sad_ssd_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
420+ * int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16, int32_t *psqdiff16x16)
421+ */
422+WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadSsd_AArch64_neon
423+ ldr x12, [sp, #0] //psqsum16x16
424+ ldr x13, [sp, #8] //psqdiff16x16
425+ eor v17.16b, v17.16b, v17.16b
426+
427+ lsl x9, x4, #4
428+ sub x10, x9, #16 //x10 keep the 16*pic_stride-16
429+ sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
430+
431+vaa_calc_sad_ssd_height_loop:
432+ mov w11, w2
433+vaa_calc_sad_ssd_width_loop:
434+ SAD_SSD_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27, psqdiff:v29
435+ SAD_SSD_8x16BYTES_2
436+
437+ uaddlv s20, v2.4h
438+ ins v2.d[0], v2.d[1]
439+ uaddlv s21, v2.4h
440+ uaddlv s22, v16.4h
441+ ins v16.d[0], v16.d[1]
442+ uaddlv s23, v16.4h
443+ st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
444+
445+ uaddlv s28, v28.8h
446+ str s28, [x7], #4
447+ addv s27, v27.4s
448+ str s27, [x12], #4
449+ addv s29, v29.4s
450+ str s29, [x13], #4
451+
452+ sub x0, x0, x10
453+ sub x1, x1, x10
454+ sub w11, w11, #16
455+ add v29.2s, v20.2s, v21.2s
456+ add v30.2s, v22.2s, v23.2s
457+ add v29.2s, v29.2s, v30.2s
458+ add v17.2s, v17.2s, v29.2s
459+ cbnz w11, vaa_calc_sad_ssd_width_loop
460+
461+ add x0, x0, x9
462+ add x1, x1, x9
463+ sub w3, w3, #16
464+ cbnz w3, vaa_calc_sad_ssd_height_loop
465+ str s17, [x5]
466+WELS_ASM_AARCH64_FUNC_END
467+
468+
469+.macro SAD_VAR_8x16BYTES_1
470+ ld1 {v0.16b}, [x0], x4
471+ ld1 {v1.16b}, [x1], x4
472+ uabd v31.16b, v0.16b, v1.16b
473+ uaddlp v2.8h, v31.16b // p_sad
474+
475+ uaddlp v28.8h, v0.16b // p_sum
476+ umull v30.8h, v0.8b, v0.8b
477+ uaddlp v27.4s, v30.8h
478+ umull2 v30.8h, v0.16b, v0.16b
479+ uadalp v27.4s, v30.8h // p_sqsum
480+
481+.rept 7
482+ ld1 {v0.16b}, [x0], x4
483+ ld1 {v1.16b}, [x1], x4
484+ uabd v3.16b, v0.16b, v1.16b
485+ uadalp v2.8h, v3.16b //p_sad
486+
487+ uadalp v28.8h, v0.16b // p_sum
488+ umull v30.8h, v0.8b, v0.8b
489+ uadalp v27.4s, v30.8h
490+ umull2 v30.8h, v0.16b, v0.16b
491+ uadalp v27.4s, v30.8h // p_sqsum
492+.endr
493+.endm
494+.macro SAD_VAR_8x16BYTES_2
495+ ld1 {v0.16b}, [x0], x4
496+ ld1 {v1.16b}, [x1], x4
497+ uabd v26.16b, v0.16b, v1.16b
498+ uaddlp v16.8h,v26.16b // p_sad
499+
500+ uadalp v28.8h, v0.16b // p_sum
501+ umull v30.8h, v0.8b, v0.8b
502+ uadalp v27.4s, v30.8h
503+ umull2 v30.8h, v0.16b, v0.16b
504+ uadalp v27.4s, v30.8h // p_sqsum
505+.rept 7
506+ ld1 {v0.16b}, [x0], x4
507+ ld1 {v1.16b}, [x1], x4
508+ uabd v3.16b, v0.16b, v1.16b
509+ uadalp v16.8h, v3.16b //p_sad
510+
511+ uadalp v28.8h, v0.16b // p_sum
512+ umull v30.8h, v0.8b, v0.8b
513+ uadalp v27.4s, v30.8h
514+ umull2 v30.8h, v0.16b, v0.16b
515+ uadalp v27.4s, v30.8h // p_sqsum
516+.endr
517+.endm
518+
519+/*
520+ * void vaa_calc_sad_var_c(uint8_t *cur_data, uint8_t *ref_data, int32_t pic_width, int32_t pic_height, int32_t pic_stride,
521+ * int32_t *psadframe,int32_t *psad8x8, int32_t *psum16x16, int32_t *psqsum16x16)
522+ */
523+WELS_ASM_AARCH64_FUNC_BEGIN VAACalcSadVar_AArch64_neon
524+ ldr x12, [sp, #0] //psqsum16x16
525+ eor v17.16b, v17.16b, v17.16b
526+
527+ lsl x9, x4, #4
528+ sub x10, x9, #16 //x10 keep the 16*pic_stride-16
529+ sub x9, x9, x2 //x9 keep the 16*pic_stride-pic_width
530+
531+vaa_calc_sad_var_height_loop:
532+ mov w11, w2
533+vaa_calc_sad_var_width_loop:
534+ SAD_VAR_8x16BYTES_1 //psad:v2, v16, psum:v28, psqsum:v27
535+ SAD_VAR_8x16BYTES_2
536+
537+ uaddlv s20, v2.4h
538+ ins v2.d[0], v2.d[1]
539+ uaddlv s21, v2.4h
540+ uaddlv s22, v16.4h
541+ ins v16.d[0], v16.d[1]
542+ uaddlv s23, v16.4h
543+ st4 {v20.s, v21.s, v22.s, v23.s}[0], [x6], #16
544+
545+ uaddlv s28, v28.8h
546+ str s28, [x7], #4
547+ addv s27, v27.4s
548+ str s27, [x12], #4
549+
550+ sub x0, x0, x10
551+ sub x1, x1, x10
552+ sub w11, w11, #16
553+ add v29.2s, v20.2s, v21.2s
554+ add v30.2s, v22.2s, v23.2s
555+ add v29.2s, v29.2s, v30.2s
556+ add v17.2s, v17.2s, v29.2s
557+
558+ cbnz w11, vaa_calc_sad_var_width_loop
559+
560+ add x0, x0, x9
561+ add x1, x1, x9
562+ sub w3, w3, #16
563+ cbnz w3, vaa_calc_sad_var_height_loop
564+ str s17, [x5]
565+WELS_ASM_AARCH64_FUNC_END
566+
567+#endif
codec/processing/src/vaacalc/vaacalculation.cpp+10−0
@@ -74,6 +74,16 @@ void CVAACalculation::InitVaaFuncs (SVaaFuncs& sVaaFuncs, int32_t iCpuFlag) { · 73 unmodified lines
7474 sVaaFuncs.pfVAACalcSadVar = VAACalcSadVar_neon;
7575 }
7676 #endif//HAVE_NEON
77+
78+#ifdef HAVE_NEON_AARCH64
79+ if ((iCpuFlag & WELS_CPU_NEON) == WELS_CPU_NEON) {
80+ sVaaFuncs.pfVAACalcSad = VAACalcSad_AArch64_neon;
81+ sVaaFuncs.pfVAACalcSadBgd = VAACalcSadBgd_AArch64_neon;
82+ sVaaFuncs.pfVAACalcSadSsd = VAACalcSadSsd_AArch64_neon;
83+ sVaaFuncs.pfVAACalcSadSsdBgd = VAACalcSadSsdBgd_AArch64_neon;
84+ sVaaFuncs.pfVAACalcSadVar = VAACalcSadVar_AArch64_neon;
85+ }
86+#endif//HAVE_NEON_AARCH64
7787 }
7888
7989 EResult CVAACalculation::Process (int32_t iType, SPixMap* pSrcPixMap, SPixMap* pRefPixMap) {
codec/processing/src/vaacalc/vaacalculation.h+10−0
@@ -117,6 +117,16 @@ VAACalcSadSsdFunc VAACalcSadSsd_neon; · 116 unmodified lines
117117 WELSVP_EXTERN_C_END
118118 #endif
119119
120+#ifdef HAVE_NEON_AARCH64
121+WELSVP_EXTERN_C_BEGIN
122+VAACalcSadBgdFunc VAACalcSadBgd_AArch64_neon;
123+VAACalcSadSsdBgdFunc VAACalcSadSsdBgd_AArch64_neon;
124+VAACalcSadFunc VAACalcSad_AArch64_neon;
125+VAACalcSadVarFunc VAACalcSadVar_AArch64_neon;
126+VAACalcSadSsdFunc VAACalcSadSsd_AArch64_neon;
127+WELSVP_EXTERN_C_END
128+#endif
129+
120130 class CVAACalculation : public IStrategy {
121131 public:
122132 CVAACalculation (int32_t iCpuFlag);

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