At lower bitrates, it is overall faster to conditionally do one block at a time with SSE2 on Haswell and likely other common architectures. At higher bitrates, it is faster to use the wider routine that IDCTs four blocks at a time. To avoid potential performance regressions as compared to MMX, stick with single-block IDCTs with SSE2. There is still a performance advantage as compared to MMX because the single-block SSE2 routine is faster than the corresponding MMX routine. Stick with four blocks at a time with AVX2 for which that appears to be consistently faster on Haswell.
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| @@ -139,7 +139,6 @@ GENERATE_IDCTRESADDPRED (IdctResAddPred_c, 0) · 138 unmodified lines | ||
| 139 | 139 | GENERATE_IDCTRESADDPRED (IdctResAddPred_mmx, WELS_CPU_MMXEXT) |
| 140 | 140 | GENERATE_IDCTRESADDPRED (IdctResAddPred_sse2, WELS_CPU_SSE2) |
| 141 | 141 | GENERATE_IDCTRESADDPRED (IdctResAddPred_avx2, WELS_CPU_AVX2) |
| 142 | −GENERATE_IDCTFOURRESADDPRED (IdctFourResAddPred_sse2, WELS_CPU_SSE2) | |
| 143 | 142 | GENERATE_IDCTFOURRESADDPRED (IdctFourResAddPred_avx2, WELS_CPU_AVX2) |
| 144 | 143 | #endif |
| 145 | 144 | |