At lower bitrates, it is overall faster to conditionally do one block at a time with SSE2 on Haswell and likely other common architectures. At higher bitrates, it is faster to use the wider routine that IDCTs four blocks at a time. To avoid potential performance regressions as compared to MMX, stick with single-block IDCTs with SSE2. There is still a performance advantage as compared to MMX because the single-block SSE2 routine is faster than the corresponding MMX routine. Stick with four blocks at a time with AVX2 for which that appears to be consistently faster on Haswell.
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| @@ -992,7 +992,7 @@ void InitPredFunc (PWelsDecoderContext pCtx, uint32_t uiCpuFlag) { · 991 unmodified lines | ||
| 992 | 992 | } |
| 993 | 993 | if (uiCpuFlag & WELS_CPU_SSE2) { |
| 994 | 994 | pCtx->pIdctResAddPredFunc = IdctResAddPred_sse2; |
| 995 | − pCtx->pIdctFourResAddPredFunc = IdctFourResAddPred_sse2; | |
| 995 | + pCtx->pIdctFourResAddPredFunc = IdctFourResAddPred_<IdctResAddPred_sse2>; | |
| 996 | 996 | |
| 997 | 997 | pCtx->pGetI16x16LumaPredFunc[I16_PRED_DC] = WelsDecoderI16x16LumaPredDc_sse2; |
| 998 | 998 | pCtx->pGetI16x16LumaPredFunc[I16_PRED_P] = WelsDecoderI16x16LumaPredPlane_sse2; |