Partly add arm asm code to encoder.

Licai Guo committed 12 years ago

Commit bb244d71 parent 7150adc28 files · +7914 −1Browse files

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codec/processing/src/arm/.DS_Store +0 −0
codec/processing/src/arm/adaptive_quantization.S +120 −0
codec/processing/src/arm/down_sample_neon.S +342 −0
codec/processing/src/arm/pixel_sad_neon.S +68 −0
codec/processing/src/arm/vaa_calc_neon.S +1143 −0

codec/processing/src/arm/.DS_Store+0−0

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codec/processing/src/arm/adaptive_quantization.S+120−0

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	1	+/*!
	2	+ * \copy
	3	+ * Copyright (c) 2013, Cisco Systems
	4	+ * All rights reserved.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions
	8	+ * are met:
	9	+ *
	10	+ * * Redistributions of source code must retain the above copyright
	11	+ * notice, this list of conditions and the following disclaimer.
	12	+ *
	13	+ * * Redistributions in binary form must reproduce the above copyright
	14	+ * notice, this list of conditions and the following disclaimer in
	15	+ * the documentation and/or other materials provided with the
	16	+ * distribution.
	17	+ *
	18	+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	19	+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	20	+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	21	+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	22	+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	23	+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	24	+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	26	+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	27	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
	28	+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	+ * POSSIBILITY OF SUCH DAMAGE.
	30	+ *
	31	+ */
	32	+
	33	+#ifdef HAVE_NEON
	34	+.text
	35	+#include "arm_arch_common_macro.S"
	36	+
	37	+#ifdef APPLE_IOS
	38	+.macro SQR_ADD_16BYTES
	39	+ vmull.u8 q3, $0, $0
	40	+ vmull.u8 q8, $1, $1
	41	+ vpadal.u16 $2, q3
	42	+ vpadal.u16 $2, q8
	43	+.endm
	44	+#else
	45	+.macro SQR_ADD_16BYTES arg0, arg1, arg2
	46	+ vmull.u8 q3, \arg0, \arg0
	47	+ vmull.u8 q8, \arg1, \arg1
	48	+ vpadal.u16 \arg2, q3
	49	+ vpadal.u16 \arg2, q8
	50	+.endm
	51	+#endif
	52	+
	53	+
	54	+WELS_ASM_FUNC_BEGIN pixel_var_16x16_neon
	55	+ stmdb sp!, {r4}
	56	+
	57	+ vld1.8 {q15}, [r0], r1 //save the ref data (16bytes)
	58	+ vld1.8 {q14}, [r2], r3 //save the src data (16bytes)
	59	+
	60	+
	61	+ vabd.u8 q13, q14, q15
	62	+ vmull.u8 q12, d27, d27
	63	+ vmull.u8 q11, d26, d26
	64	+ vaddl.u16 q12, d24, d25
	65	+ vpadal.u16 q12, q11 //sqr
	66	+
	67	+ vaddl.u8 q13, d26, d27 //sum
	68	+
	69	+ vaddl.u8 q10, d28, d29 //sum_cur
	70	+
	71	+ vmull.u8 q9, d29, d29
	72	+ vmull.u8 q8, d28, d28
	73	+ vaddl.u16 q9, d18, d19 //sqr_cur
	74	+ vpadal.u16 q9, q8
	75	+
	76	+ mov r4, #15
	77	+pixel_var_16x16_loop0:
	78	+
	79	+ vld1.8 {q0}, [r0], r1 //save the ref data (16bytes)
	80	+ vld1.8 {q1}, [r2], r3 //save the src data (16bytes)
	81	+
	82	+ vabd.u8 q2, q0, q1
	83	+
	84	+ //q10 save sum_cur
	85	+ vpadal.u8 q10, q1
	86	+
	87	+ //q12 save sqr
	88	+ SQR_ADD_16BYTES d4, d5, q12
	89	+
	90	+ //q13 save sum
	91	+ vpadal.u8 q13, q2
	92	+
	93	+ subs r4, #1
	94	+
	95	+ //q9 save sqr_cur
	96	+ SQR_ADD_16BYTES d2, d3, q9
	97	+
	98	+ bne pixel_var_16x16_loop0
	99	+
	100	+ vadd.u16 d0, d26, d27 //sum
	101	+ vadd.u16 d1, d20, d21 //sum_cur
	102	+ vpaddl.u16 q0, q0
	103	+ vadd.u32 d2, d24, d25 //sqr
	104	+ vadd.u32 d3, d18, d19 //sqr_cur
	105	+ vpadd.u32 d0, d0, d1
	106	+ vpadd.u32 d1, d2, d3
	107	+
	108	+ ldr r4, [sp, #4]
	109	+
	110	+ vshr.u32 q0, q0, #8
	111	+ vmul.u32 d0, d0
	112	+ vsub.u32 d0, d1, d0
	113	+ vmovl.u32 q0, d0
	114	+ vst2.16 {d0[0], d1[0]}, [r4]
	115	+
	116	+ ldmia sp!, {r4}
	117	+
	118	+WELS_ASM_FUNC_END
	119	+
	120	+#endif

codec/processing/src/arm/down_sample_neon.S+342−0

@@ -0,0 +1,342 @@
	1	+/*!
	2	+ * \copy
	3	+ * Copyright (c) 2013, Cisco Systems
	4	+ * All rights reserved.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions
	8	+ * are met:
	9	+ *
	10	+ * * Redistributions of source code must retain the above copyright
	11	+ * notice, this list of conditions and the following disclaimer.
	12	+ *
	13	+ * * Redistributions in binary form must reproduce the above copyright
	14	+ * notice, this list of conditions and the following disclaimer in
	15	+ * the documentation and/or other materials provided with the
	16	+ * distribution.
	17	+ *
	18	+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	19	+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	20	+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	21	+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	22	+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	23	+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	24	+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	26	+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	27	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
	28	+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	+ * POSSIBILITY OF SUCH DAMAGE.
	30	+ *
	31	+ */
	32	+
	33	+#ifdef HAVE_NEON
	34	+.text
	35	+#include "arm_arch_common_macro.S"
	36	+
	37	+
	38	+WELS_ASM_FUNC_BEGIN comp_ds_bilinear_neon
	39	+ stmdb sp!, {r4-r8, lr}
	40	+
	41	+ //Get the width and height
	42	+ ldr r4, [sp, #24] //src_width
	43	+ ldr r5, [sp, #28] //src_height
	44	+
	45	+ //Initialize the register
	46	+ mov r6, r2
	47	+ mov r8, r0
	48	+ mov lr, #0
	49	+ lsr r5, #1
	50	+
	51	+ //Save the tailer for the unasigned size
	52	+ mla r7, r1, r5, r0
	53	+ vld1.32 {q15}, [r7]
	54	+
	55	+ add r7, r2, r3
	56	+ //processing a colume data
	57	+comp_ds_bilinear_loop0:
	58	+
	59	+ vld1.8 {q0,q1}, [r2]!
	60	+ vld1.8 {q2,q3}, [r7]!
	61	+ vpaddl.u8 q0, q0
	62	+ vpaddl.u8 q1, q1
	63	+ vpaddl.u8 q2, q2
	64	+ vpaddl.u8 q3, q3
	65	+ vrshr.u16 q0, #1
	66	+ vrshr.u16 q1, #1
	67	+ vrshr.u16 q2, #1
	68	+ vrshr.u16 q3, #1
	69	+ vrhadd.u16 q0, q2
	70	+ vrhadd.u16 q1, q3
	71	+ vmovn.u16 d0, q0
	72	+ vmovn.u16 d1, q1
	73	+ vst1.32 {q0}, [r0]!
	74	+ add lr, #32
	75	+
	76	+ cmp lr, r4
	77	+ movcs lr, #0
	78	+ addcs r6, r3, lsl #1
	79	+ movcs r2, r6
	80	+ addcs r7, r2, r3
	81	+ addcs r8, r1
	82	+ movcs r0, r8
	83	+ subscs r5, #1
	84	+ bne comp_ds_bilinear_loop0
	85	+
	86	+ //restore the tailer for the unasigned size
	87	+ vst1.32 {q15}, [r0]
	88	+
	89	+ ldmia sp!, {r4-r8,lr}
	90	+WELS_ASM_FUNC_END
	91	+
	92	+
	93	+WELS_ASM_FUNC_BEGIN comp_ds_bilinear_w_x8_neon
	94	+ stmdb sp!, {r4-r7, lr}
	95	+
	96	+ //Get the width and height
	97	+ ldr r4, [sp, #20] //src_width
	98	+ ldr r5, [sp, #24] //src_height
	99	+
	100	+ //Get the difference
	101	+ sub lr, r3, r4
	102	+ sub r1, r1, r4, lsr #1
	103	+
	104	+ lsr r5, #1
	105	+
	106	+ //processing a colume data
	107	+comp_ds_bilinear_w_x8_loop0:
	108	+
	109	+ lsr r6, r4, #3
	110	+ add r7, r2, r3
	111	+ //processing a line data
	112	+comp_ds_bilinear_w_x8_loop1:
	113	+
	114	+ vld1.8 {d0}, [r2]!
	115	+ vld1.8 {d1}, [r7]!
	116	+ vpaddl.u8 q0, q0
	117	+ vrshr.u16 q0, #1
	118	+ vrhadd.u16 d0, d1
	119	+
	120	+ vmovn.u16 d0, q0
	121	+ vst1.32 {d0[0]}, [r0]!
	122	+ subs r6, #1
	123	+ bne comp_ds_bilinear_w_x8_loop1
	124	+
	125	+ add r2, r7, lr
	126	+ add r0, r1
	127	+ subs r5, #1
	128	+ bne comp_ds_bilinear_w_x8_loop0
	129	+
	130	+ ldmia sp!, {r4-r7,lr}
	131	+WELS_ASM_FUNC_END
	132	+
	133	+
	134	+WELS_ASM_FUNC_BEGIN comp_ds_bilinear_w_x16_neon
	135	+ stmdb sp!, {r4-r7, lr}
	136	+
	137	+ //Get the width and height
	138	+ ldr r4, [sp, #20] //src_width
	139	+ ldr r5, [sp, #24] //src_height
	140	+
	141	+ //Get the difference
	142	+ sub lr, r3, r4
	143	+ sub r1, r1, r4, lsr #1
	144	+
	145	+ lsr r5, #1
	146	+
	147	+ //processing a colume data
	148	+comp_ds_bilinear_w_x16_loop0:
	149	+
	150	+ lsr r6, r4, #4
	151	+ add r7, r2, r3
	152	+ //processing a line data
	153	+comp_ds_bilinear_w_x16_loop1:
	154	+
	155	+ vld1.8 {q0}, [r2]!
	156	+ vld1.8 {q1}, [r7]!
	157	+ vpaddl.u8 q0, q0
	158	+ vpaddl.u8 q1, q1
	159	+ vrshr.u16 q0, #1
	160	+ vrshr.u16 q1, #1
	161	+ vrhadd.u16 q0, q1
	162	+
	163	+ vmovn.u16 d0, q0
	164	+ vst1.32 {d0}, [r0]!
	165	+ subs r6, #1
	166	+ bne comp_ds_bilinear_w_x16_loop1
	167	+
	168	+ add r2, r7, lr
	169	+ add r0, r1
	170	+ subs r5, #1
	171	+ bne comp_ds_bilinear_w_x16_loop0
	172	+
	173	+ ldmia sp!, {r4-r7,lr}
	174	+WELS_ASM_FUNC_END
	175	+
	176	+
	177	+WELS_ASM_FUNC_BEGIN comp_ds_bilinear_w_x32_neon
	178	+ stmdb sp!, {r4-r7, lr}
	179	+
	180	+ //Get the width and height
	181	+ ldr r4, [sp, #20] //src_width
	182	+ ldr r5, [sp, #24] //src_height
	183	+
	184	+ //Get the difference
	185	+ sub lr, r3, r4
	186	+ sub r1, r1, r4, lsr #1
	187	+
	188	+ lsr r5, #1
	189	+
	190	+ //processing a colume data
	191	+comp_ds_bilinear_w_x32_loop0:
	192	+
	193	+ lsr r6, r4, #5
	194	+ add r7, r2, r3
	195	+ //processing a line data
	196	+comp_ds_bilinear_w_x32_loop1:
	197	+
	198	+ vld1.8 {q0,q1}, [r2]!
	199	+ vld1.8 {q2,q3}, [r7]!
	200	+ vpaddl.u8 q0, q0
	201	+ vpaddl.u8 q1, q1
	202	+ vpaddl.u8 q2, q2
	203	+ vpaddl.u8 q3, q3
	204	+ vrshr.u16 q0, #1
	205	+ vrshr.u16 q1, #1
	206	+ vrshr.u16 q2, #1
	207	+ vrshr.u16 q3, #1
	208	+ vrhadd.u16 q0, q2
	209	+ vrhadd.u16 q1, q3
	210	+
	211	+ vmovn.u16 d0, q0
	212	+ vmovn.u16 d1, q1
	213	+ vst1.32 {q0}, [r0]!
	214	+ subs r6, #1
	215	+ bne comp_ds_bilinear_w_x32_loop1
	216	+
	217	+ add r2, r7, lr
	218	+ add r0, r1
	219	+ subs r5, #1
	220	+ bne comp_ds_bilinear_w_x32_loop0
	221	+
	222	+ ldmia sp!, {r4-r7,lr}
	223	+WELS_ASM_FUNC_END
	224	+
	225	+
	226	+WELS_ASM_FUNC_BEGIN general_ds_bilinear_accurate_neon
	227	+ stmdb sp!, {r4-r12, lr}
	228	+
	229	+ //Get the data from stack
	230	+ ldr r4, [sp, #40] //the addr of src
	231	+ ldr r5, [sp, #44] //the value of src_stride
	232	+ ldr r6, [sp, #48] //the value of scaleX
	233	+ ldr r7, [sp, #52] //the value of scaleY
	234	+
	235	+ mov r10, #32768
	236	+ sub r10, #1
	237	+ and r8, r6, r10 // r8 uinc(scaleX mod 32767)
	238	+ mov r11, #-1
	239	+ mul r11, r8 // r11 -uinc
	240	+
	241	+ vdup.s16 d2, r8
	242	+ vdup.s16 d0, r11
	243	+ vzip.s16 d0, d2 // uinc -uinc uinc -uinc
	244	+
	245	+ and r9, r7, r10 // r9 vinc(scaleY mod 32767)
	246	+ mov r11, #-1
	247	+ mul r11, r9 // r11 -vinc
	248	+
	249	+ vdup.s16 d2, r9
	250	+ vdup.s16 d3, r11
	251	+ vext.8 d5, d3, d2, #4 // vinc vinc -vinc -vinc
	252	+
	253	+ mov r11, #0x40000000
	254	+ mov r12, #0x4000
	255	+ sub r12, #1
	256	+ add r11, r12
	257	+ vdup.s32 d1, r11; //init u 16384 16383 16384 16383
	258	+
	259	+ mov r11, #16384
	260	+ vdup.s16 d8, r11
	261	+ sub r11, #1
	262	+ vdup.s16 d9, r11
	263	+ vext.8 d7, d9, d8, #4 //init v 16384 16384 16383 16383
	264	+
	265	+ veor q14, q14
	266	+ sub r1, r2 // stride - width
	267	+ mov r8, #16384 // yInverse
	268	+ sub r3, #1
	269	+
	270	+_HEIGHT:
	271	+ ldr r4, [sp, #40] //the addr of src
	272	+ mov r11, r8
	273	+ lsr r11, #15
	274	+ mul r11, r5
	275	+ add r11, r4 // get current row address
	276	+ mov r12, r11
	277	+ add r12, r5
	278	+
	279	+ mov r9, #16384 // xInverse
	280	+ sub r10, r2, #1
	281	+ vmov.s16 d6, d1
	282	+
	283	+_WIDTH:
	284	+ mov lr, r9
	285	+ lsr lr, #15
	286	+ add r4, r11,lr
	287	+ vld2.8 {d28[0],d29[0]}, [r4] //q14: 0000000b0000000a;
	288	+ add r4, r12,lr
	289	+ vld2.8 {d28[4],d29[4]}, [r4] //q14: 000d000b000c000a;
	290	+ vzip.32 d28, d29 //q14: 000d000c000b000a;
	291	+
	292	+ vmull.u16 q13, d6, d7 //q13: init u * init v
	293	+ vmull.u32 q12, d26,d28
	294	+ vmlal.u32 q12, d27,d29
	295	+ vqadd.u64 d24, d24,d25
	296	+ vrshr.u64 d24, #30
	297	+
	298	+ vst1.8 {d24[0]}, [r0]!
	299	+ add r9, r6
	300	+ vadd.u16 d6, d0 // inc u
	301	+ vshl.u16 d6, #1
	302	+ vshr.u16 d6, #1
	303	+ subs r10, #1
	304	+ bne _WIDTH
	305	+
	306	+WIDTH_END:
	307	+ lsr r9, #15
	308	+ add r4,r11,r9
	309	+ vld1.8 {d24[0]}, [r4]
	310	+ vst1.8 {d24[0]}, [r0]
	311	+ add r0, #1
	312	+ add r8, r7
	313	+ add r0, r1
	314	+ vadd.s16 d7, d5 // inc v
	315	+ vshl.u16 d7, #1
	316	+ vshr.u16 d7, #1
	317	+ subs r3, #1
	318	+ bne _HEIGHT
	319	+
	320	+LAST_ROW:
	321	+ ldr r4, [sp, #40] //the addr of src
	322	+ lsr r8, #15
	323	+ mul r8, r5
	324	+ add r4, r8 // get current row address
	325	+ mov r9, #16384
	326	+
	327	+_LAST_ROW_WIDTH:
	328	+ mov r11, r9
	329	+ lsr r11, #15
	330	+
	331	+ add r3, r4,r11
	332	+ vld1.8 {d0[0]}, [r3]
	333	+ vst1.8 {d0[0]}, [r0]
	334	+ add r0, #1
	335	+ add r9, r6
	336	+ subs r2, #1
	337	+ bne _LAST_ROW_WIDTH
	338	+
	339	+ ldmia sp!, {r4-r12, lr}
	340	+WELS_ASM_FUNC_END
	341	+
	342	+#endif

codec/processing/src/arm/pixel_sad_neon.S+68−0

@@ -0,0 +1,68 @@
	1	+/*!
	2	+ * \copy
	3	+ * Copyright (c) 2013, Cisco Systems
	4	+ * All rights reserved.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions
	8	+ * are met:
	9	+ *
	10	+ * * Redistributions of source code must retain the above copyright
	11	+ * notice, this list of conditions and the following disclaimer.
	12	+ *
	13	+ * * Redistributions in binary form must reproduce the above copyright
	14	+ * notice, this list of conditions and the following disclaimer in
	15	+ * the documentation and/or other materials provided with the
	16	+ * distribution.
	17	+ *
	18	+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	19	+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	20	+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	21	+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	22	+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	23	+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	24	+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	26	+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	27	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
	28	+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	+ * POSSIBILITY OF SUCH DAMAGE.
	30	+ *
	31	+ */
	32	+
	33	+#ifdef HAVE_NEON
	34	+.text
	35	+#include "arm_arch_common_macro.S"
	36	+
	37	+
	38	+WELS_ASM_FUNC_BEGIN pixel_sad_8x8_neon
	39	+ stmdb sp!, {lr}
	40	+ //Loading a horizontal line data (8 bytes)
	41	+ vld1.8 {d0}, [r0], r1
	42	+ vld1.8 {d1}, [r2], r3
	43	+
	44	+ //Do the SAD for 8 bytes
	45	+ vabdl.u8 q1, d0, d1
	46	+
	47	+ mov lr, #7
	48	+pixel_sad_8x8_loop0:
	49	+
	50	+ //Loading a horizontal line data (8 bytes)
	51	+ vld1.8 {d0}, [r0], r1
	52	+ vld1.8 {d1}, [r2], r3
	53	+
	54	+ subs lr, #1
	55	+
	56	+ //Do the SAD for 8 bytes
	57	+ vabal.u8 q1, d0, d1
	58	+ bne pixel_sad_8x8_loop0
	59	+
	60	+ vadd.u16 d2, d3
	61	+ vpaddl.u16 d2, d2
	62	+ vpaddl.u32 d2, d2
	63	+ vmov.u32 r0, d2[0]//TBO...
	64	+
	65	+ ldmia sp!, {lr}
	66	+WELS_ASM_FUNC_END
	67	+
	68	+#endif

codec/processing/src/arm/vaa_calc_neon.S+1143−0

@@ -0,0 +1,1143 @@
	1	+/*!
	2	+ * \copy
	3	+ * Copyright (c) 2013, Cisco Systems
	4	+ * All rights reserved.
	5	+ *
	6	+ * Redistribution and use in source and binary forms, with or without
	7	+ * modification, are permitted provided that the following conditions
	8	+ * are met:
	9	+ *
	10	+ * * Redistributions of source code must retain the above copyright
	11	+ * notice, this list of conditions and the following disclaimer.
	12	+ *
	13	+ * * Redistributions in binary form must reproduce the above copyright
	14	+ * notice, this list of conditions and the following disclaimer in
	15	+ * the documentation and/or other materials provided with the
	16	+ * distribution.
	17	+ *
	18	+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	19	+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	20	+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	21	+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	22	+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	23	+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	24	+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	25	+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
	26	+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	27	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
	28	+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	+ * POSSIBILITY OF SUCH DAMAGE.
	30	+ *
	31	+ */
	32	+
	33	+#ifdef HAVE_NEON
	34	+.text
	35	+#include "arm_arch_common_macro.S"
	36	+
	37	+#ifdef APPLE_IOS
	38	+
	39	+.macro ABS_SUB_SUM_16BYTES
	40	+ vld1.32 {q15}, [$0], $2
	41	+ vld1.32 {q14}, [$1], $2
	42	+ vabal.u8 $3, d30, d28
	43	+ vabal.u8 $4, d31, d29
	44	+.endm
	45	+
	46	+.macro ABS_SUB_SUM_8x16BYTES
	47	+ vld1.32 {q15}, [$0], $2
	48	+ vld1.32 {q14}, [$1], $2
	49	+ vabdl.u8 $3, d30, d28
	50	+ vabdl.u8 $4, d31, d29
	51	+
	52	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	53	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	54	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	55	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	56	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	57	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	58	+ ABS_SUB_SUM_16BYTES $0, $1, $2, $3, $4
	59	+.endm
	60	+
	61	+.macro SAD_8X16BITS
	62	+ vadd.u16 d31, $0, $1
	63	+ vpaddl.u16 d31, d31
	64	+ vpaddl.u32 $2, d31
	65	+.endm
	66	+
	67	+#else
	68	+
	69	+.macro ABS_SUB_SUM_16BYTES arg0, arg1, arg2, arg3, arg4
	70	+ vld1.32 {q15}, [\arg0], \arg2
	71	+ vld1.32 {q14}, [\arg1], \arg2
	72	+ vabal.u8 \arg3, d30, d28
	73	+ vabal.u8 \arg4, d31, d29
	74	+.endm
	75	+
	76	+.macro ABS_SUB_SUM_8x16BYTES arg0, arg1, arg2, arg3, arg4
	77	+ vld1.32 {q15}, [\arg0], \arg2
	78	+ vld1.32 {q14}, [\arg1], \arg2
	79	+ vabdl.u8 \arg3, d30, d28
	80	+ vabdl.u8 \arg4, d31, d29
	81	+
	82	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	83	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	84	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	85	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	86	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	87	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	88	+ ABS_SUB_SUM_16BYTES \arg0, \arg1, \arg2, \arg3, \arg4
	89	+.endm
	90	+
	91	+.macro SAD_8X16BITS arg0, arg1, arg2
	92	+ vadd.u16 d31, \arg0, \arg1
	93	+ vpaddl.u16 d31, d31
	94	+ vpaddl.u32 \arg2, d31
	95	+.endm
	96	+#endif
	97	+
	98	+
	99	+WELS_ASM_FUNC_BEGIN vaa_calc_sad_neon
	100	+
	101	+ stmdb sp!, {r4-r8}
	102	+
	103	+ ldr r4, [sp, #20] //load pic_stride
	104	+ ldr r5, [sp, #28] //load psad8x8
	105	+
	106	+ //Initial the Q4 register for save the "psadframe"
	107	+ vmov.s64 q4, #0
	108	+
	109	+ //Get the jump distance to use on loop codes
	110	+ lsl r8, r4, #4
	111	+ sub r7, r8, #16 //R7 keep the 16*pic_stride-16
	112	+ sub r8, r2 //R8 keep the 16*pic_stride-pic_width
	113	+
	114	+vaa_calc_sad_loop0:
	115	+
	116	+ //R6 keep the pic_width
	117	+ mov r6, r2
	118	+
	119	+vaa_calc_sad_loop1:
	120	+
	121	+ //Process the 16x16 bytes
	122	+ ABS_SUB_SUM_8x16BYTES r0, r1, r4, q0, q1
	123	+ ABS_SUB_SUM_8x16BYTES r0, r1, r4, q2, q3
	124	+
	125	+ //Do the SAD
	126	+ SAD_8X16BITS d0, d1, d0
	127	+ SAD_8X16BITS d2, d3, d1
	128	+ SAD_8X16BITS d4, d5, d2
	129	+ SAD_8X16BITS d6, d7, d3
	130	+
	131	+ //Write to "psad8x8" buffer
	132	+ vst4.32 {d0[0],d1[0],d2[0],d3[0]}, [r5]!
	133	+
	134	+
	135	+ //Adjust the input address
	136	+ sub r0, r7
	137	+ sub r1, r7
	138	+
	139	+ subs r6, #16
	140	+
	141	+ //Save to calculate "psadframe"
	142	+ vadd.u32 q0, q1
	143	+ vadd.u32 q4, q0
	144	+
	145	+ bne vaa_calc_sad_loop1
	146	+
	147	+ //Adjust the input address
	148	+ add r0, r8
	149	+ add r1, r8
	150	+
	151	+ subs r3, #16
	152	+ bne vaa_calc_sad_loop0
	153	+
	154	+ ldr r6, [sp, #24] //load psadframe
	155	+ vadd.u32 d8, d9
	156	+ vst1.32 {d8[0]}, [r6]
	157	+
	158	+ ldmia sp!, {r4-r8}
	159	+
	160	+WELS_ASM_FUNC_END
	161	+
	162	+
	163	+#ifdef APPLE_IOS
	164	+.macro SAD_SD_MAD_16BYTES
	165	+ vld1.32 {q0}, [$0], $2
	166	+ vld1.32 {q1}, [$1], $2
	167	+
	168	+ vpadal.u8 $3, q0
	169	+ vpadal.u8 $4, q1
	170	+
	171	+ vabd.u8 q0, q0, q1
	172	+ vmax.u8 $5, q0
	173	+ vpadal.u8 $6, q0
	174	+.endm
	175	+
	176	+.macro SAD_SD_MAD_8x16BYTES
	177	+ vld1.32 {q0}, [$0], $2
	178	+ vld1.32 {q1}, [$1], $2
	179	+
	180	+ vpaddl.u8 q2, q0
	181	+ vpaddl.u8 q3, q1
	182	+
	183	+ vabd.u8 $3, q0, q1
	184	+ vpaddl.u8 $4, $3 //abs_diff
	185	+
	186	+
	187	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	188	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	189	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	190	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	191	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	192	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	193	+ SAD_SD_MAD_16BYTES $0,$1,$2,q2,q3,$3,$4
	194	+
	195	+ vsub.u16 $5, q2, q3
	196	+.endm
	197	+
	198	+.macro SAD_SD_MAD_CALC
	199	+ vpmax.u8 d0, $0, $1 //8bytes
	200	+ vpmax.u8 d0, d0, d0 //4bytes
	201	+ vpmax.u8 $2, d0, d0 //2bytes
	202	+
	203	+ vpaddl.u16 $3, $3
	204	+ vpaddl.u32 $3, $3
	205	+ vpaddl.s16 $4, $4
	206	+ vpaddl.s32 $4, $4
	207	+.endm
	208	+#else
	209	+.macro SAD_SD_MAD_16BYTES arg0, arg1, arg2, arg3, arg4, arg5, arg6
	210	+ vld1.32 {q0}, [\arg0], \arg2
	211	+ vld1.32 {q1}, [\arg1], \arg2
	212	+
	213	+ vpadal.u8 \arg3, q0
	214	+ vpadal.u8 \arg4, q1
	215	+
	216	+ vabd.u8 q0, q0, q1
	217	+ vmax.u8 \arg5, q0
	218	+ vpadal.u8 \arg6, q0
	219	+.endm
	220	+
	221	+.macro SAD_SD_MAD_8x16BYTES arg0, arg1, arg2, arg3, arg4, arg5
	222	+ vld1.32 {q0}, [\arg0], \arg2
	223	+ vld1.32 {q1}, [\arg1], \arg2
	224	+
	225	+ vpaddl.u8 q2, q0
	226	+ vpaddl.u8 q3, q1
	227	+
	228	+ vabd.u8 \arg3, q0, q1
	229	+ vpaddl.u8 \arg4, \arg3 //abs_diff
	230	+
	231	+
	232	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	233	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	234	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	235	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	236	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	237	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	238	+ SAD_SD_MAD_16BYTES \arg0,\arg1,\arg2,q2,q3,\arg3,\arg4
	239	+
	240	+ vsub.u16 \arg5, q2, q3
	241	+.endm
	242	+
	243	+.macro SAD_SD_MAD_CALC arg0, arg1, arg2, arg3, arg4
	244	+ vpmax.u8 d0, \arg0, \arg1 //8bytes
	245	+ vpmax.u8 d0, d0, d0 //4bytes
	246	+ vpmax.u8 \arg2, d0, d0 //2bytes
	247	+
	248	+ vpaddl.u16 \arg3, \arg3
	249	+ vpaddl.u32 \arg3, \arg3
	250	+ vpaddl.s16 \arg4, \arg4
	251	+ vpaddl.s32 \arg4, \arg4
	252	+.endm
	253	+#endif
	254	+
	255	+WELS_ASM_FUNC_BEGIN vaa_calc_sad_bgd_neon
	256	+
	257	+ stmdb sp!, {r4-r10}
	258	+
	259	+ ldr r4, [sp, #28] //load pic_stride
	260	+ ldr r5, [sp, #36] //load psad8x8
	261	+ ldr r6, [sp, #40] //load psd8x8
	262	+ ldr r7, [sp, #44] //load pmad8x8
	263	+
	264	+ //Initial the Q4 register for save the "psadframe"
	265	+ vmov.s64 q15, #0
	266	+
	267	+ //Get the jump distance to use on loop codes
	268	+ lsl r10, r4, #4
	269	+ sub r9, r10, #16 //R9 keep the 16*pic_stride-16
	270	+ sub r10, r2 //R10 keep the 16*pic_stride-pic_width
	271	+
	272	+vaa_calc_sad_bgd_loop0:
	273	+
	274	+ //R6 keep the pic_width
	275	+ mov r8, r2
	276	+
	277	+vaa_calc_sad_bgd_loop1:
	278	+
	279	+ //Process the 16x16 bytes pmad psad psd
	280	+ SAD_SD_MAD_8x16BYTES r0, r1, r4, q13, q11, q9
	281	+ SAD_SD_MAD_8x16BYTES r0, r1, r4, q14, q12, q10
	282	+
	283	+ SAD_SD_MAD_CALC d26, d27, d16, q11, q9
	284	+ SAD_SD_MAD_CALC d28, d29, d17, q12, q10
	285	+
	286	+ //Write to "psad8x8" buffer
	287	+ vst4.32 {d22[0],d23[0],d24[0],d25[0]}, [r5]!
	288	+ //Adjust the input address
	289	+ sub r0, r9
	290	+ sub r1, r9
	291	+ //Write to "psd8x8" buffer
	292	+ vst4.32 {d18[0],d19[0],d20[0],d21[0]}, [r6]!
	293	+ subs r8, #16
	294	+ //Write to "pmad8x8" buffer
	295	+ vst2.16 {d16[0],d17[0]}, [r7]!
	296	+ //Save to calculate "psadframe"
	297	+ vadd.u32 q11, q12
	298	+ vadd.u32 q15, q11
	299	+
	300	+ bne vaa_calc_sad_bgd_loop1
	301	+
	302	+ //Adjust the input address
	303	+ add r0, r10
	304	+ add r1, r10
	305	+
	306	+ subs r3, #16
	307	+ bne vaa_calc_sad_bgd_loop0
	308	+
	309	+ ldr r8, [sp, #32] //load psadframe
	310	+ vadd.u32 d30, d31
	311	+ vst1.32 {d30[0]}, [r8]
	312	+ ldmia sp!, {r4-r10}
	313	+
	314	+WELS_ASM_FUNC_END
	315	+
	316	+
	317	+#ifdef APPLE_IOS
	318	+.macro SSD_MUL_SUM_16BYTES_RESET
	319	+ vmull.u8 $3, $0, $0
	320	+ vpaddl.u16 $2, $3
	321	+
	322	+ vmull.u8 $3, $1, $1
	323	+ vpadal.u16 $2, $3
	324	+.endm
	325	+
	326	+.macro SSD_MUL_SUM_16BYTES
	327	+ vmull.u8 $3, $0, $0
	328	+ vpadal.u16 $2, $3
	329	+
	330	+ vmull.u8 $3, $1, $1
	331	+ vpadal.u16 $2, $3
	332	+.endm
	333	+
	334	+.macro SAD_SSD_BGD_16
	335	+ vld1.8 {q0}, [$0], $2 //load cur_row
	336	+
	337	+ vpadal.u8 q3, q0 //add cur_row together
	338	+ vpadal.u8 q4, q1 //add ref_row together
	339	+
	340	+ vabd.u8 q2, q0, q1 //abs_diff
	341	+
	342	+ vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
	343	+
	344	+ vpadal.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	345	+
	346	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	347	+
	348	+ vld1.8 {q1}, [$1], $2 //load ref_row
	349	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	350	+
	351	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	352	+.endm
	353	+
	354	+//the last row of a 16x16 block
	355	+.macro SAD_SSD_BGD_16_end
	356	+ vld1.8 {q0}, [$0], $1 //load cur_row
	357	+
	358	+ vpadal.u8 q3, q0 //add cur_row together
	359	+ vpadal.u8 q4, q1 //add ref_row together
	360	+
	361	+ vabd.u8 q2, q0, q1 //abs_diff
	362	+
	363	+ vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
	364	+
	365	+ vpadal.u8 $2, q2 //l_sad for 16 bytes reset for every 8x16
	366	+
	367	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	368	+
	369	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	370	+
	371	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	372	+.endm
	373	+
	374	+//for the begin of a 8x16 block, use some instructions to reset the register
	375	+.macro SAD_SSD_BGD_16_RESET_8x8
	376	+ vld1.8 {q0}, [$0], $2 //load cur_row
	377	+
	378	+ vpaddl.u8 q3, q0 //add cur_row together
	379	+ vpaddl.u8 q4, q1 //add ref_row together
	380	+
	381	+ vabd.u8 q2, q0, q1 //abs_diff
	382	+
	383	+ vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
	384	+
	385	+ vpaddl.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	386	+
	387	+
	388	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	389	+
	390	+ vld1.8 {q1}, [$1], $2 //load ref_row
	391	+
	392	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	393	+
	394	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	395	+.endm
	396	+
	397	+//for the begin of a 16x16 block, use some instructions to reset the register
	398	+.macro SAD_SSD_BGD_16_RESET_16x16
	399	+ vld1.8 {q0}, [$0], $2 //load cur_row
	400	+ vld1.8 {q1}, [$1], $2 //load ref_row
	401	+
	402	+ vpaddl.u8 q3, q0 //add cur_row together
	403	+ vpaddl.u8 q4, q1 //add ref_row together
	404	+
	405	+ vabd.u8 q2, q0, q1 //abs_diff
	406	+
	407	+ vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
	408	+
	409	+ vpaddl.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	410	+
	411	+ SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	412	+
	413	+ vld1.8 {q1}, [$1], $2 //load ref_row
	414	+
	415	+ vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
	416	+
	417	+ SSD_MUL_SUM_16BYTES_RESET d0,d1,q10,q11 //q10 for lsqsum reset for every 16x16
	418	+.endm
	419	+
	420	+//for each 8x16 block
	421	+.macro SAD_SSD_BGD_CALC_8x16
	422	+
	423	+ vpmax.u8 d10, d10, d11 //4 numbers
	424	+ vpmax.u8 d10, d10, d10 //2 numbers
	425	+ vpmax.u8 d10, d10, d10 //1 number1
	426	+
	427	+ vmov $0, d10 //d26 d27 keeps the l_mad
	428	+
	429	+ //p_sd8x8 fix me
	430	+ vpaddl.u16 q3, q3
	431	+ vpaddl.u16 q4, q4
	432	+
	433	+ vsub.i32 $1, q3, q4
	434	+ vpaddl.u32 $1, $1
	435	+
	436	+ //psad8x8
	437	+ vpaddl.u16 $2, $2
	438	+ vpaddl.u32 $2, $2
	439	+
	440	+ //psadframe
	441	+ vadd.i32 q12, $2
	442	+.endm
	443	+
	444	+.macro SAD_SSD_BGD_16x16
	445	+ //for one 8x16
	446	+ SAD_SSD_BGD_16_RESET_16x16 $0, $1, $2, q6
	447	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	448	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	449	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	450	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	451	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	452	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	453	+ SAD_SSD_BGD_16 $0, $1, $2, q6
	454	+
	455	+ SAD_SSD_BGD_CALC_8x16 d26, q14, q6
	456	+
	457	+ //for another 8x16
	458	+ SAD_SSD_BGD_16_RESET_8x8 $0, $1, $2, q7
	459	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	460	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	461	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	462	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	463	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	464	+ SAD_SSD_BGD_16 $0, $1, $2, q7
	465	+ SAD_SSD_BGD_16_end $0, $2, q7
	466	+
	467	+ SAD_SSD_BGD_CALC_8x16 d27, q15, q7
	468	+.endm
	469	+
	470	+.macro SSD_SAD_SD_MAD_PADDL
	471	+ vpaddl.s16 $0, $0
	472	+ vpaddl.s32 $0, $0
	473	+ vadd.i32 $1, $1, $2
	474	+.endm
	475	+#else
	476	+.macro SSD_MUL_SUM_16BYTES_RESET arg0, arg1, arg2, arg3
	477	+ vmull.u8 \arg3, \arg0, \arg0
	478	+ vpaddl.u16 \arg2, \arg3
	479	+
	480	+ vmull.u8 \arg3, \arg1, \arg1
	481	+ vpadal.u16 \arg2, \arg3
	482	+.endm
	483	+
	484	+.macro SSD_MUL_SUM_16BYTES arg0, arg1, arg2, arg3
	485	+ vmull.u8 \arg3, \arg0, \arg0
	486	+ vpadal.u16 \arg2, \arg3
	487	+
	488	+ vmull.u8 \arg3, \arg1, \arg1
	489	+ vpadal.u16 \arg2, \arg3
	490	+.endm
	491	+
	492	+.macro SAD_SSD_BGD_16 arg0, arg1, arg2, arg3
	493	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	494	+
	495	+ vpadal.u8 q3, q0 //add cur_row together
	496	+ vpadal.u8 q4, q1 //add ref_row together
	497	+
	498	+ vabd.u8 q2, q0, q1 //abs_diff
	499	+
	500	+ vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
	501	+
	502	+ vpadal.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	503	+
	504	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	505	+
	506	+ vld1.8 {q1}, [\arg1], \arg2 //load ref_row
	507	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	508	+
	509	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	510	+.endm
	511	+
	512	+//the last row of a 16x16 block
	513	+.macro SAD_SSD_BGD_16_end arg0, arg1, arg2
	514	+ vld1.8 {q0}, [\arg0], \arg1 //load cur_row
	515	+
	516	+ vpadal.u8 q3, q0 //add cur_row together
	517	+ vpadal.u8 q4, q1 //add ref_row together
	518	+
	519	+ vabd.u8 q2, q0, q1 //abs_diff
	520	+
	521	+ vmax.u8 q5, q2 //l_mad for 16 bytes reset for every 8x16
	522	+
	523	+ vpadal.u8 \arg2, q2 //l_sad for 16 bytes reset for every 8x16
	524	+
	525	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	526	+
	527	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	528	+
	529	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	530	+.endm
	531	+
	532	+//for the begin of a 8x16 block, use some instructions to reset the register
	533	+.macro SAD_SSD_BGD_16_RESET_8x8 arg0, arg1, arg2, arg3
	534	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	535	+
	536	+ vpaddl.u8 q3, q0 //add cur_row together
	537	+ vpaddl.u8 q4, q1 //add ref_row together
	538	+
	539	+ vabd.u8 q2, q0, q1 //abs_diff
	540	+
	541	+ vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
	542	+
	543	+ vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	544	+
	545	+
	546	+ SSD_MUL_SUM_16BYTES d4,d5, q8, q11 //q8 for l_sqiff reset for every 16x16
	547	+
	548	+ vld1.8 {q1}, [\arg1], \arg2 //load ref_row
	549	+
	550	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	551	+
	552	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	553	+.endm
	554	+
	555	+//for the begin of a 16x16 block, use some instructions to reset the register
	556	+.macro SAD_SSD_BGD_16_RESET_16x16 arg0, arg1, arg2, arg3
	557	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	558	+ vld1.8 {q1}, [\arg1], \arg2 //load ref_row
	559	+
	560	+ vpaddl.u8 q3, q0 //add cur_row together
	561	+ vpaddl.u8 q4, q1 //add ref_row together
	562	+
	563	+ vabd.u8 q2, q0, q1 //abs_diff
	564	+
	565	+ vmov q5,q2 //calculate max and avoid reset to zero, l_mad for 16 bytes reset for every 8x16
	566	+
	567	+ vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	568	+
	569	+ SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	570	+
	571	+ vld1.8 {q1}, [\arg1], \arg2 //load ref_row
	572	+
	573	+ vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
	574	+
	575	+ SSD_MUL_SUM_16BYTES_RESET d0,d1,q10,q11 //q10 for lsqsum reset for every 16x16
	576	+.endm
	577	+
	578	+//for each 8x16 block
	579	+.macro SAD_SSD_BGD_CALC_8x16 arg0, arg1, arg2
	580	+
	581	+ vpmax.u8 d10, d10, d11 //4 numbers
	582	+ vpmax.u8 d10, d10, d10 //2 numbers
	583	+ vpmax.u8 d10, d10, d10 //1 number1
	584	+
	585	+ vmov \arg0, d10 //d26 d27 keeps the l_mad
	586	+
	587	+ //p_sd8x8
	588	+ vpaddl.u16 q3, q3
	589	+ vpaddl.u16 q4, q4
	590	+
	591	+ vsub.i32 \arg1, q3, q4
	592	+ vpaddl.u32 \arg1, \arg1
	593	+
	594	+ //psad8x8
	595	+ vpaddl.u16 \arg2, \arg2
	596	+ vpaddl.u32 \arg2, \arg2
	597	+
	598	+ //psadframe
	599	+ vadd.i32 q12, \arg2
	600	+.endm
	601	+
	602	+.macro SAD_SSD_BGD_16x16 arg0, arg1, arg2
	603	+ //for one 8x16
	604	+ SAD_SSD_BGD_16_RESET_16x16 \arg0, \arg1, \arg2, q6
	605	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	606	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	607	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	608	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	609	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	610	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	611	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q6
	612	+
	613	+ SAD_SSD_BGD_CALC_8x16 d26, q14, q6
	614	+
	615	+ //for another 8x16
	616	+ SAD_SSD_BGD_16_RESET_8x8 \arg0, \arg1, \arg2, q7
	617	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	618	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	619	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	620	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	621	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	622	+ SAD_SSD_BGD_16 \arg0, \arg1, \arg2, q7
	623	+ SAD_SSD_BGD_16_end \arg0, \arg2, q7
	624	+
	625	+ SAD_SSD_BGD_CALC_8x16 d27, q15, q7
	626	+.endm
	627	+
	628	+.macro SSD_SAD_SD_MAD_PADDL arg0, arg1, arg2
	629	+ vpaddl.s16 \arg0, \arg0
	630	+ vpaddl.s32 \arg0, \arg0
	631	+ vadd.i32 \arg1, \arg1, \arg2
	632	+.endm
	633	+#endif
	634	+
	635	+
	636	+WELS_ASM_FUNC_BEGIN vaa_calc_sad_ssd_bgd_neon
	637	+ stmdb sp!, {r0-r12, r14}
	638	+
	639	+ ldr r4, [sp, #56] //r4 keeps the pic_stride
	640	+
	641	+ sub r5, r4, #1
	642	+ lsl r5, r5, #4 //r5 keeps the little step
	643	+
	644	+ lsl r6, r4, #4
	645	+ sub r6, r2, r6 //r6 keeps the big step
	646	+
	647	+
	648	+ ldr r8, [sp, #64]//psad8x8
	649	+ ldr r9, [sp, #68]//psum16x16
	650	+ ldr r10, [sp, #72]//psqsum16x16
	651	+ ldr r11, [sp, #76]//psqdiff16x16
	652	+ ldr r12, [sp, #80]//p_sd8x8
	653	+ ldr r14, [sp, #84]//p_mad8x8
	654	+
	655	+ vmov.i8 q12, #0
	656	+
	657	+vaa_calc_sad_ssd_bgd_height_loop:
	658	+
	659	+ mov r7, r2
	660	+vaa_calc_sad_ssd_bgd_width_loop:
	661	+
	662	+ //l_sd q14&q15, l_mad q13, l_sad q6 & q7, l_sqdiff q8, l_sum q9, l_sqsum q10
	663	+ SAD_SSD_BGD_16x16 r0,r1,r4
	664	+
	665	+ //psad8x8
	666	+ vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
	667	+
	668	+ sub r0, r0, r5 //jump to next 16x16
	669	+ sub r1, r1, r5 //jump to next 16x16
	670	+
	671	+ //p_sd8x8
	672	+ vst4.32 {d28[0], d29[0],d30[0], d31[0]}, [r12]!
	673	+
	674	+ //p_mad8x8
	675	+ vst2.16 {d26[0], d27[0]}, [r14]!
	676	+
	677	+ //psqdiff16x16
	678	+ vpaddl.s32 q8, q8
	679	+ vadd.i32 d16, d16, d17
	680	+
	681	+ vst1.32 {d16[0]}, [r11]! //psqdiff16x16
	682	+
	683	+ //psum16x16
	684	+ SSD_SAD_SD_MAD_PADDL q9, d18, d19
	685	+ vst1.32 {d18[0]}, [r9]! //psum16x16
	686	+
	687	+ //psqsum16x16
	688	+ vpaddl.s32 q10, q10
	689	+ vadd.i32 d20, d20, d21
	690	+ vst1.32 {d20[0]}, [r10]! //psqsum16x16
	691	+
	692	+ subs r7, #16
	693	+
	694	+ bne vaa_calc_sad_ssd_bgd_width_loop
	695	+
	696	+ sub r0, r0, r6 //jump to next 16 x width
	697	+ sub r1, r1, r6 //jump to next 16 x width
	698	+
	699	+ subs r3, #16
	700	+bne vaa_calc_sad_ssd_bgd_height_loop
	701	+
	702	+ //psadframe
	703	+ ldr r7, [sp, #60]//psadframe
	704	+
	705	+ vadd.i32 d24, d24, d25
	706	+ vst1.32 {d24[0]}, [r7]
	707	+
	708	+ ldmia sp!, {r0-r12, r14}
	709	+
	710	+WELS_ASM_FUNC_END
	711	+
	712	+
	713	+#ifdef APPLE_IOS
	714	+.macro SAD_VAR_16
	715	+ vld1.8 {q0}, [$0], $2 //load cur_row
	716	+
	717	+ vpadal.u8 q3, q0 //add cur_row together
	718	+ vpadal.u8 q4, q1 //add ref_row together
	719	+
	720	+ vabd.u8 q2, q0, q1 //abs_diff
	721	+
	722	+ vpadal.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	723	+
	724	+ vld1.8 {q1}, [$1], $2
	725	+
	726	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	727	+
	728	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	729	+.endm
	730	+
	731	+.macro SAD_VAR_16_END
	732	+ vld1.8 {q0}, [$0], $1 //load cur_row
	733	+
	734	+ vpadal.u8 q3, q0 //add cur_row together
	735	+ vpadal.u8 q4, q1 //add ref_row together
	736	+
	737	+ vabd.u8 q2, q0, q1 //abs_diff
	738	+
	739	+ vpadal.u8 $2, q2 //l_sad for 16 bytes reset for every 8x16
	740	+
	741	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	742	+
	743	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	744	+.endm
	745	+
	746	+.macro SAD_VAR_16_RESET_16x16
	747	+ vld1.8 {q0}, [$0], $2 //load cur_row
	748	+ vld1.8 {q1}, [$1], $2
	749	+
	750	+ vpaddl.u8 q3, q0 //add cur_row together
	751	+ vpaddl.u8 q4, q1 //add ref_row together
	752	+
	753	+ vabd.u8 q2, q0, q1 //abs_diff
	754	+
	755	+ vpaddl.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	756	+
	757	+ vld1.8 {q1}, [$1], $2
	758	+
	759	+ vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
	760	+
	761	+ SSD_MUL_SUM_16BYTES_RESET d0,d1, q10, q11
	762	+.endm
	763	+
	764	+.macro SAD_VAR_16_RESET_8x8
	765	+ vld1.8 {q0}, [$0], $2 //load cur_row
	766	+
	767	+ vpaddl.u8 q3, q0 //add cur_row together
	768	+ vpaddl.u8 q4, q1 //add ref_row together
	769	+
	770	+ vabd.u8 q2, q0, q1 //abs_diff
	771	+
	772	+ vpaddl.u8 $3, q2 //l_sad for 16 bytes reset for every 8x16
	773	+
	774	+ vld1.8 {q1}, [$1], $2
	775	+
	776	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	777	+
	778	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	779	+.endm
	780	+
	781	+.macro SAD_VAR_16x16
	782	+ //for one 8x16
	783	+ SAD_VAR_16_RESET_16x16 $0, $1, $2, q6
	784	+ SAD_VAR_16 $0, $1, $2, q6
	785	+ SAD_VAR_16 $0, $1, $2, q6
	786	+ SAD_VAR_16 $0, $1, $2, q6
	787	+ SAD_VAR_16 $0, $1, $2, q6
	788	+ SAD_VAR_16 $0, $1, $2, q6
	789	+ SAD_VAR_16 $0, $1, $2, q6
	790	+ SAD_VAR_16 $0, $1, $2, q6
	791	+
	792	+ vpaddl.u16 q6, q6
	793	+ vpaddl.u32 q6, q6
	794	+ vadd.i32 q12, q6
	795	+
	796	+ //for another 8x16
	797	+ SAD_VAR_16_RESET_8x8 $0, $1, $2, q7
	798	+ SAD_VAR_16 $0, $1, $2, q7
	799	+ SAD_VAR_16 $0, $1, $2, q7
	800	+ SAD_VAR_16 $0, $1, $2, q7
	801	+ SAD_VAR_16 $0, $1, $2, q7
	802	+ SAD_VAR_16 $0, $1, $2, q7
	803	+ SAD_VAR_16 $0, $1, $2, q7
	804	+ SAD_VAR_16_END $0, $2, q7
	805	+
	806	+ vpaddl.u16 q7, q7
	807	+ vpaddl.u32 q7, q7
	808	+
	809	+ vadd.i32 q12, q7
	810	+.endm
	811	+#else
	812	+.macro SAD_VAR_16 arg0, arg1, arg2, arg3
	813	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	814	+
	815	+ vpadal.u8 q3, q0 //add cur_row together
	816	+ vpadal.u8 q4, q1 //add ref_row together
	817	+
	818	+ vabd.u8 q2, q0, q1 //abs_diff
	819	+
	820	+ vpadal.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	821	+
	822	+ vld1.8 {q1}, [\arg1], \arg2
	823	+
	824	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	825	+
	826	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	827	+.endm
	828	+
	829	+.macro SAD_VAR_16_END arg0, arg1, arg2
	830	+ vld1.8 {q0}, [\arg0], \arg1 //load cur_row
	831	+
	832	+ vpadal.u8 q3, q0 //add cur_row together
	833	+ vpadal.u8 q4, q1 //add ref_row together
	834	+
	835	+ vabd.u8 q2, q0, q1 //abs_diff
	836	+
	837	+ vpadal.u8 \arg2, q2 //l_sad for 16 bytes reset for every 8x16
	838	+
	839	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	840	+
	841	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	842	+.endm
	843	+
	844	+
	845	+.macro SAD_VAR_16_RESET_16x16 arg0, arg1, arg2, arg3
	846	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	847	+ vld1.8 {q1}, [\arg1], \arg2
	848	+
	849	+ vpaddl.u8 q3, q0 //add cur_row together
	850	+ vpaddl.u8 q4, q1 //add ref_row together
	851	+
	852	+ vabd.u8 q2, q0, q1 //abs_diff
	853	+
	854	+ vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	855	+
	856	+ vld1.8 {q1}, [\arg1], \arg2
	857	+
	858	+ vpaddl.u8 q9, q0 //q9 for l_sum reset for every 16x16
	859	+
	860	+ SSD_MUL_SUM_16BYTES_RESET d0,d1, q10, q11
	861	+.endm
	862	+
	863	+.macro SAD_VAR_16_RESET_8x8 arg0, arg1, arg2, arg3
	864	+ vld1.8 {q0}, [\arg0], \arg2 //load cur_row
	865	+
	866	+ vpaddl.u8 q3, q0 //add cur_row together
	867	+ vpaddl.u8 q4, q1 //add ref_row together
	868	+
	869	+ vabd.u8 q2, q0, q1 //abs_diff
	870	+
	871	+ vpaddl.u8 \arg3, q2 //l_sad for 16 bytes reset for every 8x16
	872	+
	873	+ vld1.8 {q1}, [\arg1], \arg2
	874	+
	875	+ vpadal.u8 q9, q0 //q9 for l_sum reset for every 16x16
	876	+
	877	+ SSD_MUL_SUM_16BYTES d0,d1, q10, q11 //q10 for lsqsum reset for every 16x16
	878	+.endm
	879	+
	880	+.macro SAD_VAR_16x16 arg0, arg1, arg2
	881	+ //for one 8x16
	882	+ SAD_VAR_16_RESET_16x16 \arg0, \arg1, \arg2, q6
	883	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	884	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	885	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	886	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	887	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	888	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	889	+ SAD_VAR_16 \arg0, \arg1, \arg2, q6
	890	+
	891	+ vpaddl.u16 q6, q6
	892	+ vpaddl.u32 q6, q6
	893	+ vadd.i32 q12, q6
	894	+
	895	+ //for another 8x16
	896	+ SAD_VAR_16_RESET_8x8 \arg0, \arg1, \arg2, q7
	897	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	898	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	899	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	900	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	901	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	902	+ SAD_VAR_16 \arg0, \arg1, \arg2, q7
	903	+ SAD_VAR_16_END \arg0, \arg2, q7
	904	+
	905	+ vpaddl.u16 q7, q7
	906	+ vpaddl.u32 q7, q7
	907	+
	908	+ vadd.i32 q12, q7
	909	+.endm
	910	+#endif
	911	+
	912	+
	913	+WELS_ASM_FUNC_BEGIN vaa_calc_sad_var_neon
	914	+ stmdb sp!, {r4-r11}
	915	+
	916	+ ldr r4, [sp, #32] //r4 keeps the pic_stride
	917	+
	918	+ sub r5, r4, #1
	919	+ lsl r5, r5, #4 //r5 keeps the little step
	920	+
	921	+ lsl r6, r4, #4
	922	+ sub r6, r2, r6 //r6 keeps the big step
	923	+
	924	+ ldr r7, [sp, #36] //psadframe
	925	+ ldr r8, [sp, #40] //psad8x8
	926	+ ldr r9, [sp, #44] //psum16x16
	927	+ ldr r10, [sp, #48] //psqsum16x16
	928	+
	929	+ vmov.i8 q12, #0
	930	+vaa_calc_sad_var_height_loop:
	931	+
	932	+ mov r11, r2
	933	+vaa_calc_sad_var_width_loop:
	934	+
	935	+
	936	+ SAD_VAR_16x16 r0,r1,r4
	937	+ //psad8x8
	938	+ vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
	939	+
	940	+ sub r0, r0, r5 //jump to next 16x16
	941	+ sub r1, r1, r5 //jump to next 16x16
	942	+
	943	+ //psum16x16
	944	+ SSD_SAD_SD_MAD_PADDL q9, d18, d19
	945	+ vst1.32 {d18[0]}, [r9]! //psum16x16
	946	+
	947	+ //psqsum16x16
	948	+ vpaddl.s32 q10, q10
	949	+ subs r11, #16
	950	+ vadd.i32 d20, d20, d21
	951	+ vst1.32 {d20[0]}, [r10]! //psqsum16x16
	952	+
	953	+ bne vaa_calc_sad_var_width_loop
	954	+
	955	+ sub r0, r0, r6 //jump to next 16 x width
	956	+ sub r1, r1, r6 //jump to next 16 x width
	957	+
	958	+ subs r3, #16
	959	+bne vaa_calc_sad_var_height_loop
	960	+
	961	+ vadd.i32 d24, d24, d25
	962	+ vst1.32 {d24[0]}, [r7]
	963	+
	964	+ ldmia sp!, {r4-r11}
	965	+WELS_ASM_FUNC_END
	966	+
	967	+
	968	+#ifdef APPLE_IOS
	969	+.macro SAD_SSD_16
	970	+ SAD_VAR_16 $0, $1, $2, $3
	971	+
	972	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11
	973	+.endm
	974	+
	975	+.macro SAD_SSD_16_END
	976	+ SAD_VAR_16_END $0, $1, $2, $3
	977	+
	978	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	979	+.endm
	980	+
	981	+.macro SAD_SSD_16_RESET_16x16
	982	+ SAD_VAR_16_RESET_16x16 $0, $1, $2, $3
	983	+
	984	+ SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	985	+.endm
	986	+
	987	+.macro SAD_SSD_16_RESET_8x8
	988	+ SAD_VAR_16_RESET_8x8 $0, $1, $2, $3
	989	+
	990	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	991	+.endm
	992	+
	993	+.macro SAD_SSD_16x16
	994	+ //for one 8x16
	995	+ SAD_SSD_16_RESET_16x16 $0, $1, $2, q6
	996	+ SAD_SSD_16 $0, $1, $2, q6
	997	+ SAD_SSD_16 $0, $1, $2, q6
	998	+ SAD_SSD_16 $0, $1, $2, q6
	999	+ SAD_SSD_16 $0, $1, $2, q6
	1000	+ SAD_SSD_16 $0, $1, $2, q6
	1001	+ SAD_SSD_16 $0, $1, $2, q6
	1002	+ SAD_SSD_16 $0, $1, $2, q6
	1003	+
	1004	+ vpaddl.u16 q6, q6
	1005	+ vpaddl.u32 q6, q6
	1006	+ vadd.i32 q12, q6
	1007	+
	1008	+ //for another 8x16
	1009	+ SAD_SSD_16_RESET_8x8 $0, $1, $2, q7
	1010	+ SAD_SSD_16 $0, $1, $2, q7
	1011	+ SAD_SSD_16 $0, $1, $2, q7
	1012	+ SAD_SSD_16 $0, $1, $2, q7
	1013	+ SAD_SSD_16 $0, $1, $2, q7
	1014	+ SAD_SSD_16 $0, $1, $2, q7
	1015	+ SAD_SSD_16 $0, $1, $2, q7
	1016	+ SAD_SSD_16_END $0, $2, q7
	1017	+
	1018	+ vpaddl.u16 q7, q7
	1019	+ vpaddl.u32 q7, q7
	1020	+
	1021	+ vadd.i32 q12, q7
	1022	+.endm
	1023	+#else
	1024	+.macro SAD_SSD_16 arg0, arg1, arg2, arg3
	1025	+ SAD_VAR_16 \arg0, \arg1, \arg2, \arg3
	1026	+
	1027	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11
	1028	+.endm
	1029	+
	1030	+.macro SAD_SSD_16_END arg0, arg1, arg2, arg3
	1031	+ SAD_VAR_16_END \arg0, \arg1, \arg2, \arg3
	1032	+
	1033	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	1034	+.endm
	1035	+
	1036	+.macro SAD_SSD_16_RESET_16x16 arg0, arg1, arg2, arg3
	1037	+ SAD_VAR_16_RESET_16x16 \arg0, \arg1, \arg2, \arg3
	1038	+
	1039	+ SSD_MUL_SUM_16BYTES_RESET d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	1040	+.endm
	1041	+
	1042	+.macro SAD_SSD_16_RESET_8x8 arg0, arg1, arg2, arg3
	1043	+ SAD_VAR_16_RESET_8x8 \arg0, \arg1, \arg2, \arg3
	1044	+
	1045	+ SSD_MUL_SUM_16BYTES d4,d5,q8, q11 //q8 for l_sqiff reset for every 16x16
	1046	+.endm
	1047	+
	1048	+.macro SAD_SSD_16x16 arg0, arg1, arg2
	1049	+ //for one 8x16
	1050	+ SAD_SSD_16_RESET_16x16 \arg0, \arg1, \arg2, q6
	1051	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1052	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1053	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1054	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1055	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1056	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1057	+ SAD_SSD_16 \arg0, \arg1, \arg2, q6
	1058	+
	1059	+ vpaddl.u16 q6, q6
	1060	+ vpaddl.u32 q6, q6
	1061	+ vadd.i32 q12, q6
	1062	+
	1063	+ //for another 8x16
	1064	+ SAD_SSD_16_RESET_8x8 \arg0, \arg1, \arg2, q7
	1065	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1066	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1067	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1068	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1069	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1070	+ SAD_SSD_16 \arg0, \arg1, \arg2, q7
	1071	+ SAD_SSD_16_END \arg0, \arg2, q7
	1072	+
	1073	+ vpaddl.u16 q7, q7
	1074	+ vpaddl.u32 q7, q7
	1075	+
	1076	+ vadd.i32 q12, q7
	1077	+.endm
	1078	+#endif
	1079	+
	1080	+
	1081	+WELS_ASM_FUNC_BEGIN vaa_calc_sad_ssd_neon
	1082	+ stmdb sp!, {r4-r12}
	1083	+
	1084	+ ldr r4, [sp, #36] //r4 keeps the pic_stride
	1085	+
	1086	+ sub r5, r4, #1
	1087	+ lsl r5, r5, #4 //r5 keeps the little step
	1088	+
	1089	+ lsl r6, r4, #4
	1090	+ sub r6, r2, r6 //r6 keeps the big step
	1091	+
	1092	+ ldr r7, [sp, #40] //psadframe
	1093	+ ldr r8, [sp, #44] //psad8x8
	1094	+ ldr r9, [sp, #48] //psum16x16
	1095	+ ldr r10, [sp, #52] //psqsum16x16
	1096	+ ldr r11, [sp, #56] //psqdiff16x16
	1097	+
	1098	+ vmov.i8 q12, #0
	1099	+vaa_calc_sad_ssd_height_loop:
	1100	+
	1101	+ mov r12, r2
	1102	+vaa_calc_sad_ssd_width_loop:
	1103	+
	1104	+
	1105	+ SAD_SSD_16x16 r0,r1,r4
	1106	+ //psad8x8
	1107	+ vst4.32 {d12[0], d13[0], d14[0], d15[0]}, [r8]!
	1108	+
	1109	+ sub r0, r0, r5 //jump to next 16x16
	1110	+ sub r1, r1, r5 //jump to next 16x16
	1111	+
	1112	+ //psum16x16
	1113	+ vpaddl.s16 q9, q9
	1114	+ vpaddl.s32 q9, q9
	1115	+ vadd.i32 d18, d18, d19
	1116	+ vst1.32 {d18[0]}, [r9]! //psum16x16
	1117	+
	1118	+ //psqsum16x16
	1119	+ vpaddl.s32 q10, q10
	1120	+ vadd.i32 d20, d20, d21
	1121	+ vst1.32 {d20[0]}, [r10]! //psqsum16x16
	1122	+
	1123	+ //psqdiff16x16
	1124	+ vpaddl.s32 q8, q8
	1125	+ vadd.i32 d16, d16, d17
	1126	+ subs r12, #16
	1127	+ vst1.32 {d16[0]}, [r11]! //psqdiff16x16
	1128	+
	1129	+ bne vaa_calc_sad_ssd_width_loop
	1130	+
	1131	+ sub r0, r0, r6 //jump to next 16 x width
	1132	+ sub r1, r1, r6 //jump to next 16 x width
	1133	+
	1134	+ subs r3, #16
	1135	+ bne vaa_calc_sad_ssd_height_loop
	1136	+
	1137	+ vadd.i32 d24, d24, d25
	1138	+ vst1.32 {d24[0]}, [r7]
	1139	+
	1140	+ ldmia sp!, {r4-r12}
	1141	+WELS_ASM_FUNC_END
	1142	+
	1143	+#endif

Partly add arm asm code to encoder.

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