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| 1 | /*! | ||
| 2 | * \copy | ||
| 3 | * Copyright (c) 2009-2013, Cisco Systems | ||
| 4 | * All rights reserved. | ||
| 5 | * | ||
| 6 | * Redistribution and use in source and binary forms, with or without | ||
| 7 | * modification, are permitted provided that the following conditions | ||
| 8 | * are met: | ||
| 9 | * | ||
| 10 | * * Redistributions of source code must retain the above copyright | ||
| 11 | * notice, this list of conditions and the following disclaimer. | ||
| 12 | * | ||
| 13 | * * Redistributions in binary form must reproduce the above copyright | ||
| 14 | * notice, this list of conditions and the following disclaimer in | ||
| 15 | * the documentation and/or other materials provided with the | ||
| 16 | * distribution. | ||
| 17 | * | ||
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | ||
| 19 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | ||
| 20 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS | ||
| 21 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | ||
| 22 | * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 23 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, | ||
| 24 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | ||
| 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | ||
| 26 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | ||
| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN | ||
| 28 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||
| 29 | * POSSIBILITY OF SUCH DAMAGE. | ||
| 30 | * | ||
| 31 | * \file cpu.c | ||
| 32 | * | ||
| 33 | * \brief CPU compatibility detection | ||
| 34 | * | ||
| 35 | * \date 04/29/2009 Created | ||
| 36 | * | ||
| 37 | ************************************************************************************* | ||
| 38 | */ | ||
| 39 | |||
| 40 | #include "util.h" | ||
| 41 | #include "cpu.h" | ||
| 42 | |||
| 43 | WELSVP_NAMESPACE_BEGIN | ||
| 44 | |||
| 45 | #define CPU_Vender_AMD "AuthenticAMD" | ||
| 46 | #define CPU_Vender_INTEL "GenuineIntel" | ||
| 47 | #define CPU_Vender_CYRIX "CyrixInstead" | ||
| 48 | |||
| 49 | |||
| 50 | #if defined(X86_ASM) | ||
| 51 | |||
| 52 | uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) { | ||
| 53 | uint32_t uiCPU = 0; | ||
| 54 | uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0; | ||
| 55 | int32_t CacheLineSize = 0; | ||
| 56 | int8_t chVenderName[16] = { 0 }; | ||
| 57 | |||
| 58 | if (!WelsCPUIdVerify()) { | ||
| 59 | /* cpuid is not supported in cpu */ | ||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | |||
| 63 | WelsCPUId (0, &uiFeatureA, (uint32_t*)&chVenderName[0], (uint32_t*)&chVenderName[8], (uint32_t*)&chVenderName[4]); | ||
| 64 | if (uiFeatureA == 0) { | ||
| 65 | /* maximum input value for basic cpuid information */ | ||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | ||
| 70 | if ((uiFeatureD & 0x00800000) == 0) { | ||
| 71 | /* Basic MMX technology is not support in cpu, mean nothing for us so return here */ | ||
| 72 | return 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | uiCPU = WELS_CPU_MMX; | ||
| 76 | if (uiFeatureD & 0x02000000) { | ||
| 77 | /* SSE technology is identical to AMD MMX extensions */ | ||
| 78 | uiCPU |= WELS_CPU_MMXEXT | WELS_CPU_SSE; | ||
| 79 | } | ||
| 80 | if (uiFeatureD & 0x04000000) { | ||
| 81 | /* SSE2 support here */ | ||
| 82 | uiCPU |= WELS_CPU_SSE2; | ||
| 83 | } | ||
| 84 | if (uiFeatureD & 0x00000001) { | ||
| 85 | /* x87 FPU on-chip checking */ | ||
| 86 | uiCPU |= WELS_CPU_FPU; | ||
| 87 | } | ||
| 88 | if (uiFeatureD & 0x00008000) { | ||
| 89 | /* CMOV instruction checking */ | ||
| 90 | uiCPU |= WELS_CPU_CMOV; | ||
| 91 | } | ||
| 92 | if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage | ||
| 93 | if (uiFeatureD & 0x10000000) { | ||
| 94 | /* Multi-Threading checking: contains of multiple logic processors */ | ||
| 95 | uiCPU |= WELS_CPU_HTT; | ||
| 96 | } | ||
| 97 | } | ||
| 98 | |||
| 99 | if (uiFeatureC & 0x00000001) { | ||
| 100 | /* SSE3 support here */ | ||
| 101 | uiCPU |= WELS_CPU_SSE3; | ||
| 102 | } | ||
| 103 | if (uiFeatureC & 0x00000200) { | ||
| 104 | /* SSSE3 support here */ | ||
| 105 | uiCPU |= WELS_CPU_SSSE3; | ||
| 106 | } | ||
| 107 | if (uiFeatureC & 0x00080000) { | ||
| 108 | /* SSE4.1 support here, 45nm Penryn processor */ | ||
| 109 | uiCPU |= WELS_CPU_SSE41; | ||
| 110 | } | ||
| 111 | if (uiFeatureC & 0x00100000) { | ||
| 112 | /* SSE4.2 support here, next generation Nehalem processor */ | ||
| 113 | uiCPU |= WELS_CPU_SSE42; | ||
| 114 | } | ||
| 115 | if (WelsCPUSupportAVX (uiFeatureA, uiFeatureC)) { // | ||
| 116 | /* AVX supported */ | ||
| 117 | uiCPU |= WELS_CPU_AVX; | ||
| 118 | } | ||
| 119 | if (WelsCPUSupportFMA (uiFeatureA, uiFeatureC)) { // | ||
| 120 | /* AVX FMA supported */ | ||
| 121 | uiCPU |= WELS_CPU_FMA; | ||
| 122 | } | ||
| 123 | if (uiFeatureC & 0x02000000) { | ||
| 124 | /* AES checking */ | ||
| 125 | uiCPU |= WELS_CPU_AES; | ||
| 126 | } | ||
| 127 | if (uiFeatureC & 0x00400000) { | ||
| 128 | /* MOVBE checking */ | ||
| 129 | uiCPU |= WELS_CPU_MOVBE; | ||
| 130 | } | ||
| 131 | |||
| 132 | if (pNumberOfLogicProcessors != NULL) { | ||
| 133 | // HTT enabled on chip | ||
| 134 | *pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX | ||
| 135 | } | ||
| 136 | |||
| 137 | WelsCPUId (0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | ||
| 138 | |||
| 139 | if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_AMD)) | ||
| 140 | && (uiFeatureA >= 0x80000001)) { // confirmed_safe_unsafe_usage | ||
| 141 | WelsCPUId (0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | ||
| 142 | if (uiFeatureD & 0x00400000) { | ||
| 143 | uiCPU |= WELS_CPU_MMXEXT; | ||
| 144 | } | ||
| 145 | if (uiFeatureD & 0x80000000) { | ||
| 146 | uiCPU |= WELS_CPU_3DNOW; | ||
| 147 | } | ||
| 148 | } | ||
| 149 | |||
| 150 | if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage | ||
| 151 | int32_t family, model; | ||
| 152 | |||
| 153 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | ||
| 154 | family = ((uiFeatureA >> 8) & 0xf) + ((uiFeatureA >> 20) & 0xff); | ||
| 155 | model = ((uiFeatureA >> 4) & 0xf) + ((uiFeatureA >> 12) & 0xf0); | ||
| 156 | |||
| 157 | if ((family == 6) && (model == 9 || model == 13 || model == 14)) { | ||
| 158 | uiCPU &= ~ (WELS_CPU_SSE2 | WELS_CPU_SSE3); | ||
| 159 | } | ||
| 160 | } | ||
| 161 | |||
| 162 | // get cache line size | ||
| 163 | if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) | ||
| 164 | || ! (strcmp ((const str_t*)chVenderName, CPU_Vender_CYRIX))) { // confirmed_safe_unsafe_usage | ||
| 165 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | ||
| 166 | |||
| 167 | CacheLineSize = (uiFeatureB & 0xff00) >> | ||
| 168 | 5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte | ||
| 169 | |||
| 170 | if (CacheLineSize == 128) { | ||
| 171 | uiCPU |= WELS_CPU_CACHELINE_128; | ||
| 172 | } else if (CacheLineSize == 64) { | ||
| 173 | uiCPU |= WELS_CPU_CACHELINE_64; | ||
| 174 | } else if (CacheLineSize == 32) { | ||
| 175 | uiCPU |= WELS_CPU_CACHELINE_32; | ||
| 176 | } else if (CacheLineSize == 16) { | ||
| 177 | uiCPU |= WELS_CPU_CACHELINE_16; | ||
| 178 | } | ||
| 179 | } | ||
| 180 | |||
| 181 | return uiCPU; | ||
| 182 | } | ||
| 183 | |||
| 184 | |||
| 185 | void WelsCPURestore (const uint32_t kuiCPU) { | ||
| 186 | if (kuiCPU & (WELS_CPU_MMX | WELS_CPU_MMXEXT | WELS_CPU_3DNOW | WELS_CPU_3DNOWEXT)) { | ||
| 187 | WelsEmms(); | ||
| 188 | } | ||
| 189 | } | ||
| 190 | |||
| 191 | #endif | ||
| 192 | |||
| 193 | |||
| 194 | WELSVP_NAMESPACE_END | ||
| 195 | |||
| 196 | |||