Showing the changes to codec/decoder/core/src/cpu.cpp (1 of 225 files). Show all
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| @@ -50,160 +50,143 @@ namespace WelsDec { · 49 unmodified lines | |||
| 50 | 50 | ||
| 51 | #if defined(X86_ASM) | 51 | #if defined(X86_ASM) |
| 52 | 52 | ||
| 53 | uint32_t WelsCPUFeatureDetect( int32_t *pNumberOfLogicProcessors ) | 53 | uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) { |
| 54 | { | 54 | uint32_t uiCPU = 0; |
| 55 | uint32_t uiCPU = 0; | 55 | uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0; |
| 56 | uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0; | 56 | int32_t CacheLineSize = 0; |
| 57 | int32_t CacheLineSize = 0; | 57 | int8_t chVenderName[16] = { 0 }; |
| 58 | int8_t chVenderName[16] = { 0 }; | 58 | |
| 59 | 59 | if (!WelsCPUIdVerify()) { | |
| 60 | if( !WelsCPUIdVerify() ) | 60 | /* cpuid is not supported in cpu */ |
| 61 | { | 61 | return 0; |
| 62 | /* cpuid is not supported in cpu */ | 62 | } |
| 63 | return 0; | 63 | |
| 64 | } | 64 | WelsCPUId (0, &uiFeatureA, (uint32_t*)&chVenderName[0], (uint32_t*)&chVenderName[8], (uint32_t*)&chVenderName[4]); |
| 65 | 65 | if (uiFeatureA == 0) { | |
| 66 | WelsCPUId( 0, &uiFeatureA, (uint32_t*)&chVenderName[0],(uint32_t*)&chVenderName[8],(uint32_t*)&chVenderName[4] ); | 66 | /* maximum input value for basic cpuid information */ |
| 67 | if( uiFeatureA == 0 ) | 67 | return 0; |
| 68 | { | 68 | } |
| 69 | /* maximum input value for basic cpuid information */ | 69 | |
| 70 | return 0; | 70 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); |
| 71 | } | 71 | if ((uiFeatureD & 0x00800000) == 0) { |
| 72 | 72 | /* Basic MMX technology is not support in cpu, mean nothing for us so return here */ | |
| 73 | WelsCPUId( 1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD ); | 73 | return 0; |
| 74 | if( (uiFeatureD & 0x00800000) == 0 ) | 74 | } |
| 75 | { | 75 | |
| 76 | /* Basic MMX technology is not support in cpu, mean nothing for us so return here */ | 76 | uiCPU = WELS_CPU_MMX; |
| 77 | return 0; | 77 | if (uiFeatureD & 0x02000000) { |
| 78 | } | 78 | /* SSE technology is identical to AMD MMX extensions */ |
| 79 | 79 | uiCPU |= WELS_CPU_MMXEXT | WELS_CPU_SSE; | |
| 80 | uiCPU = WELS_CPU_MMX; | 80 | } |
| 81 | if( uiFeatureD & 0x02000000 ) | 81 | if (uiFeatureD & 0x04000000) { |
| 82 | { | 82 | /* SSE2 support here */ |
| 83 | /* SSE technology is identical to AMD MMX extensions */ | 83 | uiCPU |= WELS_CPU_SSE2; |
| 84 | uiCPU |= WELS_CPU_MMXEXT|WELS_CPU_SSE; | 84 | } |
| 85 | } | 85 | if (uiFeatureD & 0x00000001) { |
| 86 | if( uiFeatureD & 0x04000000 ) | 86 | /* x87 FPU on-chip checking */ |
| 87 | { | 87 | uiCPU |= WELS_CPU_FPU; |
| 88 | /* SSE2 support here */ | 88 | } |
| 89 | uiCPU |= WELS_CPU_SSE2; | 89 | if (uiFeatureD & 0x00008000) { |
| 90 | } | 90 | /* CMOV instruction checking */ |
| 91 | if ( uiFeatureD & 0x00000001 ) | 91 | uiCPU |= WELS_CPU_CMOV; |
| 92 | { | 92 | } |
| 93 | /* x87 FPU on-chip checking */ | 93 | if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage |
| 94 | uiCPU |= WELS_CPU_FPU; | 94 | if (uiFeatureD & 0x10000000) { |
| 95 | } | 95 | /* Multi-Threading checking: contains of multiple logic processors */ |
| 96 | if ( uiFeatureD & 0x00008000 ) | 96 | uiCPU |= WELS_CPU_HTT; |
| 97 | { | 97 | } |
| 98 | /* CMOV instruction checking */ | 98 | } |
| 99 | uiCPU |= WELS_CPU_CMOV; | 99 | |
| 100 | } | 100 | if (uiFeatureC & 0x00000001) { |
| 101 | if ( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ) // confirmed_safe_unsafe_usage | 101 | /* SSE3 support here */ |
| 102 | { | 102 | uiCPU |= WELS_CPU_SSE3; |
| 103 | if ( uiFeatureD & 0x10000000 ) | 103 | } |
| 104 | { | 104 | if (uiFeatureC & 0x00000200) { |
| 105 | /* Multi-Threading checking: contains of multiple logic processors */ | 105 | /* SSSE3 support here */ |
| 106 | uiCPU |= WELS_CPU_HTT; | 106 | uiCPU |= WELS_CPU_SSSE3; |
| 107 | } | 107 | } |
| 108 | } | 108 | if (uiFeatureC & 0x00080000) { |
| 109 | 109 | /* SSE4.1 support here, 45nm Penryn processor */ | |
| 110 | if( uiFeatureC & 0x00000001 ){ | 110 | uiCPU |= WELS_CPU_SSE41; |
| 111 | /* SSE3 support here */ | 111 | } |
| 112 | uiCPU |= WELS_CPU_SSE3; | 112 | if (uiFeatureC & 0x00100000) { |
| 113 | } | 113 | /* SSE4.2 support here, next generation Nehalem processor */ |
| 114 | if( uiFeatureC & 0x00000200 ){ | 114 | uiCPU |= WELS_CPU_SSE42; |
| 115 | /* SSSE3 support here */ | 115 | } |
| 116 | uiCPU |= WELS_CPU_SSSE3; | 116 | if (WelsCPUSupportAVX (uiFeatureA, uiFeatureC)) { |
| 117 | } | 117 | /* AVX supported */ |
| 118 | if( uiFeatureC & 0x00080000 ){ | 118 | uiCPU |= WELS_CPU_AVX; |
| 119 | /* SSE4.1 support here, 45nm Penryn processor */ | 119 | } |
| 120 | uiCPU |= WELS_CPU_SSE41; | 120 | if (WelsCPUSupportFMA (uiFeatureA, uiFeatureC)) { |
| 121 | } | 121 | /* AVX FMA supported */ |
| 122 | if( uiFeatureC & 0x00100000 ){ | 122 | uiCPU |= WELS_CPU_FMA; |
| 123 | /* SSE4.2 support here, next generation Nehalem processor */ | 123 | } |
| 124 | uiCPU |= WELS_CPU_SSE42; | 124 | if (uiFeatureC & 0x02000000) { |
| 125 | } | 125 | /* AES checking */ |
| 126 | if ( WelsCPUSupportAVX( uiFeatureA, uiFeatureC ) ) | 126 | uiCPU |= WELS_CPU_AES; |
| 127 | { | 127 | } |
| 128 | /* AVX supported */ | 128 | if (uiFeatureC & 0x00400000) { |
| 129 | uiCPU |= WELS_CPU_AVX; | 129 | /* MOVBE checking */ |
| 130 | } | 130 | uiCPU |= WELS_CPU_MOVBE; |
| 131 | if ( WelsCPUSupportFMA( uiFeatureA, uiFeatureC ) ) | 131 | } |
| 132 | { | 132 | |
| 133 | /* AVX FMA supported */ | 133 | if (pNumberOfLogicProcessors != NULL) { |
| 134 | uiCPU |= WELS_CPU_FMA; | 134 | // HTT enabled on chip |
| 135 | } | 135 | *pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX |
| 136 | if ( uiFeatureC & 0x02000000 ) | 136 | } |
| 137 | { | 137 | |
| 138 | /* AES checking */ | 138 | WelsCPUId (0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); |
| 139 | uiCPU |= WELS_CPU_AES; | 139 | |
| 140 | } | 140 | if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_AMD)) |
| 141 | if ( uiFeatureC & 0x00400000 ) | 141 | && (uiFeatureA >= 0x80000001)) { // confirmed_safe_unsafe_usage |
| 142 | { | 142 | WelsCPUId (0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); |
| 143 | /* MOVBE checking */ | 143 | if (uiFeatureD & 0x00400000) { |
| 144 | uiCPU |= WELS_CPU_MOVBE; | 144 | uiCPU |= WELS_CPU_MMXEXT; |
| 145 | } | 145 | } |
| 146 | 146 | if (uiFeatureD & 0x80000000) { | |
| 147 | if ( pNumberOfLogicProcessors != NULL ) | 147 | uiCPU |= WELS_CPU_3DNOW; |
| 148 | { | 148 | } |
| 149 | // HTT enabled on chip | 149 | } |
| 150 | *pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX | 150 | |
| 151 | } | 151 | if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage |
| 152 | 152 | int32_t family, model; | |
| 153 | WelsCPUId( 0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD ); | 153 | |
| 154 | 154 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | |
| 155 | if( (!strcmp((const str_t*)chVenderName,CPU_Vender_AMD)) && (uiFeatureA>=0x80000001) ){ // confirmed_safe_unsafe_usage | 155 | family = ((uiFeatureA >> 8) & 0xf) + ((uiFeatureA >> 20) & 0xff); |
| 156 | WelsCPUId(0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD ); | 156 | model = ((uiFeatureA >> 4) & 0xf) + ((uiFeatureA >> 12) & 0xf0); |
| 157 | if( uiFeatureD&0x00400000 ){ | 157 | |
| 158 | uiCPU |= WELS_CPU_MMXEXT; | 158 | if ((family == 6) && (model == 9 || model == 13 || model == 14)) { |
| 159 | } | 159 | uiCPU &= ~ (WELS_CPU_SSE2 | WELS_CPU_SSE3); |
| 160 | if( uiFeatureD&0x80000000 ){ | 160 | } |
| 161 | uiCPU |= WELS_CPU_3DNOW; | 161 | } |
| 162 | } | 162 | |
| 163 | } | 163 | // get cache line size |
| 164 | 164 | if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) | |
| 165 | if( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ){ // confirmed_safe_unsafe_usage | 165 | || ! (strcmp ((const str_t*)chVenderName, CPU_Vender_CYRIX))) { // confirmed_safe_unsafe_usage |
| 166 | int32_t family, model; | 166 | WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); |
| 167 | 167 | ||
| 168 | WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | 168 | CacheLineSize = (uiFeatureB & 0xff00) >> |
| 169 | family = ((uiFeatureA>>8)&0xf) + ((uiFeatureA>>20)&0xff); | 169 | 5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte |
| 170 | model = ((uiFeatureA>>4)&0xf) + ((uiFeatureA>>12)&0xf0); | 170 | |
| 171 | 171 | if (CacheLineSize == 128) { | |
| 172 | if( (family==6) && (model==9 || model==13 || model==14) ){ | 172 | uiCPU |= WELS_CPU_CACHELINE_128; |
| 173 | uiCPU &= ~(WELS_CPU_SSE2|WELS_CPU_SSE3); | 173 | } else if (CacheLineSize == 64) { |
| 174 | } | 174 | uiCPU |= WELS_CPU_CACHELINE_64; |
| 175 | } | 175 | } else if (CacheLineSize == 32) { |
| 176 | 176 | uiCPU |= WELS_CPU_CACHELINE_32; | |
| 177 | // get cache line size | 177 | } else if (CacheLineSize == 16) { |
| 178 | if( (!strcmp((const str_t*)chVenderName,CPU_Vender_INTEL)) || !(strcmp((const str_t*)chVenderName,CPU_Vender_CYRIX)) ){ // confirmed_safe_unsafe_usage | 178 | uiCPU |= WELS_CPU_CACHELINE_16; |
| 179 | WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD); | 179 | } |
| 180 | 180 | } | |
| 181 | CacheLineSize = (uiFeatureB&0xff00)>>5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte | 181 | |
| 182 | 182 | return uiCPU; | |
| 183 | if( CacheLineSize == 128 ){ | 183 | } |
| 184 | uiCPU |= WELS_CPU_CACHELINE_128; | 184 | |
| 185 | } | 185 | |
| 186 | else if( CacheLineSize == 64 ){ | 186 | void WelsCPURestore (const uint32_t kuiCPU) { |
| 187 | uiCPU |= WELS_CPU_CACHELINE_64; | 187 | if (kuiCPU & (WELS_CPU_MMX | WELS_CPU_MMXEXT | WELS_CPU_3DNOW | WELS_CPU_3DNOWEXT)) { |
| 188 | } | 188 | WelsEmms(); |
| 189 | else if( CacheLineSize == 32 ){ | 189 | } |
| 190 | uiCPU |= WELS_CPU_CACHELINE_32; | ||
| 191 | } | ||
| 192 | else if( CacheLineSize == 16 ){ | ||
| 193 | uiCPU |= WELS_CPU_CACHELINE_16; | ||
| 194 | } | ||
| 195 | } | ||
| 196 | |||
| 197 | return uiCPU; | ||
| 198 | } | ||
| 199 | |||
| 200 | |||
| 201 | void WelsCPURestore( const uint32_t kuiCPU ) | ||
| 202 | { | ||
| 203 | if( kuiCPU & (WELS_CPU_MMX|WELS_CPU_MMXEXT|WELS_CPU_3DNOW|WELS_CPU_3DNOWEXT) ) | ||
| 204 | { | ||
| 205 | WelsEmms(); | ||
| 206 | } | ||
| 207 | } | 190 | } |
| 208 | 191 | ||
| 209 | #endif | 192 | #endif |