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Pretty printed the C++ code with astyle

Ethan Hugg committed 12 years ago

Commit ff6b6691 parent 063709c225 files · +48457 −51954Browse files

Showing the changes to codec/decoder/core/src/cpu.cpp (1 of 225 files). Show all

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codec/decoder/core/src/cpu.cpp+137−154
@@ -50,160 +50,143 @@ namespace WelsDec { · 49 unmodified lines
5050
5151 #if defined(X86_ASM)
5252
53−uint32_t WelsCPUFeatureDetect( int32_t *pNumberOfLogicProcessors )
54−{
55− uint32_t uiCPU = 0;
56− uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0;
57− int32_t CacheLineSize = 0;
58− int8_t chVenderName[16] = { 0 };
59−
60− if( !WelsCPUIdVerify() )
61− {
62− /* cpuid is not supported in cpu */
63− return 0;
64− }
65−
66− WelsCPUId( 0, &uiFeatureA, (uint32_t*)&chVenderName[0],(uint32_t*)&chVenderName[8],(uint32_t*)&chVenderName[4] );
67− if( uiFeatureA == 0 )
68− {
69− /* maximum input value for basic cpuid information */
70− return 0;
71− }
72−
73− WelsCPUId( 1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
74− if( (uiFeatureD & 0x00800000) == 0 )
75− {
76− /* Basic MMX technology is not support in cpu, mean nothing for us so return here */
77− return 0;
78− }
79−
80− uiCPU = WELS_CPU_MMX;
81− if( uiFeatureD & 0x02000000 )
82− {
83− /* SSE technology is identical to AMD MMX extensions */
84− uiCPU |= WELS_CPU_MMXEXT|WELS_CPU_SSE;
85− }
86− if( uiFeatureD & 0x04000000 )
87− {
88− /* SSE2 support here */
89− uiCPU |= WELS_CPU_SSE2;
90− }
91− if ( uiFeatureD & 0x00000001 )
92− {
93− /* x87 FPU on-chip checking */
94− uiCPU |= WELS_CPU_FPU;
95− }
96− if ( uiFeatureD & 0x00008000 )
97− {
98− /* CMOV instruction checking */
99− uiCPU |= WELS_CPU_CMOV;
100− }
101− if ( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ) // confirmed_safe_unsafe_usage
102− {
103− if ( uiFeatureD & 0x10000000 )
104− {
105− /* Multi-Threading checking: contains of multiple logic processors */
106− uiCPU |= WELS_CPU_HTT;
107− }
108− }
109−
110− if( uiFeatureC & 0x00000001 ){
111− /* SSE3 support here */
112− uiCPU |= WELS_CPU_SSE3;
113− }
114− if( uiFeatureC & 0x00000200 ){
115− /* SSSE3 support here */
116− uiCPU |= WELS_CPU_SSSE3;
117− }
118− if( uiFeatureC & 0x00080000 ){
119− /* SSE4.1 support here, 45nm Penryn processor */
120− uiCPU |= WELS_CPU_SSE41;
121− }
122− if( uiFeatureC & 0x00100000 ){
123− /* SSE4.2 support here, next generation Nehalem processor */
124− uiCPU |= WELS_CPU_SSE42;
125− }
126− if ( WelsCPUSupportAVX( uiFeatureA, uiFeatureC ) )
127− {
128− /* AVX supported */
129− uiCPU |= WELS_CPU_AVX;
130− }
131− if ( WelsCPUSupportFMA( uiFeatureA, uiFeatureC ) )
132− {
133− /* AVX FMA supported */
134− uiCPU |= WELS_CPU_FMA;
135− }
136− if ( uiFeatureC & 0x02000000 )
137− {
138− /* AES checking */
139− uiCPU |= WELS_CPU_AES;
140− }
141− if ( uiFeatureC & 0x00400000 )
142− {
143− /* MOVBE checking */
144− uiCPU |= WELS_CPU_MOVBE;
145− }
146−
147− if ( pNumberOfLogicProcessors != NULL )
148− {
149− // HTT enabled on chip
150− *pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX
151− }
152−
153− WelsCPUId( 0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
154−
155− if( (!strcmp((const str_t*)chVenderName,CPU_Vender_AMD)) && (uiFeatureA>=0x80000001) ){ // confirmed_safe_unsafe_usage
156− WelsCPUId(0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD );
157− if( uiFeatureD&0x00400000 ){
158− uiCPU |= WELS_CPU_MMXEXT;
159− }
160− if( uiFeatureD&0x80000000 ){
161− uiCPU |= WELS_CPU_3DNOW;
162− }
163− }
164−
165− if( !strcmp((const str_t*)chVenderName,CPU_Vender_INTEL) ){ // confirmed_safe_unsafe_usage
166− int32_t family, model;
167−
168− WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
169− family = ((uiFeatureA>>8)&0xf) + ((uiFeatureA>>20)&0xff);
170− model = ((uiFeatureA>>4)&0xf) + ((uiFeatureA>>12)&0xf0);
171−
172− if( (family==6) && (model==9 || model==13 || model==14) ){
173− uiCPU &= ~(WELS_CPU_SSE2|WELS_CPU_SSE3);
174− }
175− }
176−
177− // get cache line size
178− if( (!strcmp((const str_t*)chVenderName,CPU_Vender_INTEL)) || !(strcmp((const str_t*)chVenderName,CPU_Vender_CYRIX)) ){ // confirmed_safe_unsafe_usage
179− WelsCPUId(1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
180−
181− CacheLineSize = (uiFeatureB&0xff00)>>5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte
182−
183− if( CacheLineSize == 128 ){
184− uiCPU |= WELS_CPU_CACHELINE_128;
185− }
186− else if( CacheLineSize == 64 ){
187− uiCPU |= WELS_CPU_CACHELINE_64;
188− }
189− else if( CacheLineSize == 32 ){
190− uiCPU |= WELS_CPU_CACHELINE_32;
191− }
192− else if( CacheLineSize == 16 ){
193− uiCPU |= WELS_CPU_CACHELINE_16;
194− }
195− }
196−
197− return uiCPU;
198−}
199−
200−
201−void WelsCPURestore( const uint32_t kuiCPU )
202−{
203− if( kuiCPU & (WELS_CPU_MMX|WELS_CPU_MMXEXT|WELS_CPU_3DNOW|WELS_CPU_3DNOWEXT) )
204− {
205− WelsEmms();
206− }
53+uint32_t WelsCPUFeatureDetect (int32_t* pNumberOfLogicProcessors) {
54+ uint32_t uiCPU = 0;
55+ uint32_t uiFeatureA = 0, uiFeatureB = 0, uiFeatureC = 0, uiFeatureD = 0;
56+ int32_t CacheLineSize = 0;
57+ int8_t chVenderName[16] = { 0 };
58+
59+ if (!WelsCPUIdVerify()) {
60+ /* cpuid is not supported in cpu */
61+ return 0;
62+ }
63+
64+ WelsCPUId (0, &uiFeatureA, (uint32_t*)&chVenderName[0], (uint32_t*)&chVenderName[8], (uint32_t*)&chVenderName[4]);
65+ if (uiFeatureA == 0) {
66+ /* maximum input value for basic cpuid information */
67+ return 0;
68+ }
69+
70+ WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
71+ if ((uiFeatureD & 0x00800000) == 0) {
72+ /* Basic MMX technology is not support in cpu, mean nothing for us so return here */
73+ return 0;
74+ }
75+
76+ uiCPU = WELS_CPU_MMX;
77+ if (uiFeatureD & 0x02000000) {
78+ /* SSE technology is identical to AMD MMX extensions */
79+ uiCPU |= WELS_CPU_MMXEXT | WELS_CPU_SSE;
80+ }
81+ if (uiFeatureD & 0x04000000) {
82+ /* SSE2 support here */
83+ uiCPU |= WELS_CPU_SSE2;
84+ }
85+ if (uiFeatureD & 0x00000001) {
86+ /* x87 FPU on-chip checking */
87+ uiCPU |= WELS_CPU_FPU;
88+ }
89+ if (uiFeatureD & 0x00008000) {
90+ /* CMOV instruction checking */
91+ uiCPU |= WELS_CPU_CMOV;
92+ }
93+ if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage
94+ if (uiFeatureD & 0x10000000) {
95+ /* Multi-Threading checking: contains of multiple logic processors */
96+ uiCPU |= WELS_CPU_HTT;
97+ }
98+ }
99+
100+ if (uiFeatureC & 0x00000001) {
101+ /* SSE3 support here */
102+ uiCPU |= WELS_CPU_SSE3;
103+ }
104+ if (uiFeatureC & 0x00000200) {
105+ /* SSSE3 support here */
106+ uiCPU |= WELS_CPU_SSSE3;
107+ }
108+ if (uiFeatureC & 0x00080000) {
109+ /* SSE4.1 support here, 45nm Penryn processor */
110+ uiCPU |= WELS_CPU_SSE41;
111+ }
112+ if (uiFeatureC & 0x00100000) {
113+ /* SSE4.2 support here, next generation Nehalem processor */
114+ uiCPU |= WELS_CPU_SSE42;
115+ }
116+ if (WelsCPUSupportAVX (uiFeatureA, uiFeatureC)) {
117+ /* AVX supported */
118+ uiCPU |= WELS_CPU_AVX;
119+ }
120+ if (WelsCPUSupportFMA (uiFeatureA, uiFeatureC)) {
121+ /* AVX FMA supported */
122+ uiCPU |= WELS_CPU_FMA;
123+ }
124+ if (uiFeatureC & 0x02000000) {
125+ /* AES checking */
126+ uiCPU |= WELS_CPU_AES;
127+ }
128+ if (uiFeatureC & 0x00400000) {
129+ /* MOVBE checking */
130+ uiCPU |= WELS_CPU_MOVBE;
131+ }
132+
133+ if (pNumberOfLogicProcessors != NULL) {
134+ // HTT enabled on chip
135+ *pNumberOfLogicProcessors = (uiFeatureB & 0x00ff0000) >> 16; // feature bits: 23-16 on returned EBX
136+ }
137+
138+ WelsCPUId (0x80000000, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
139+
140+ if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_AMD))
141+ && (uiFeatureA >= 0x80000001)) { // confirmed_safe_unsafe_usage
142+ WelsCPUId (0x80000001, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
143+ if (uiFeatureD & 0x00400000) {
144+ uiCPU |= WELS_CPU_MMXEXT;
145+ }
146+ if (uiFeatureD & 0x80000000) {
147+ uiCPU |= WELS_CPU_3DNOW;
148+ }
149+ }
150+
151+ if (!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL)) { // confirmed_safe_unsafe_usage
152+ int32_t family, model;
153+
154+ WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
155+ family = ((uiFeatureA >> 8) & 0xf) + ((uiFeatureA >> 20) & 0xff);
156+ model = ((uiFeatureA >> 4) & 0xf) + ((uiFeatureA >> 12) & 0xf0);
157+
158+ if ((family == 6) && (model == 9 || model == 13 || model == 14)) {
159+ uiCPU &= ~ (WELS_CPU_SSE2 | WELS_CPU_SSE3);
160+ }
161+ }
162+
163+ // get cache line size
164+ if ((!strcmp ((const str_t*)chVenderName, CPU_Vender_INTEL))
165+ || ! (strcmp ((const str_t*)chVenderName, CPU_Vender_CYRIX))) { // confirmed_safe_unsafe_usage
166+ WelsCPUId (1, &uiFeatureA, &uiFeatureB, &uiFeatureC, &uiFeatureD);
167+
168+ CacheLineSize = (uiFeatureB & 0xff00) >>
169+ 5; // ((clflush_line_size >> 8) << 3), CLFLUSH_line_size * 8 = CacheLineSize_in_byte
170+
171+ if (CacheLineSize == 128) {
172+ uiCPU |= WELS_CPU_CACHELINE_128;
173+ } else if (CacheLineSize == 64) {
174+ uiCPU |= WELS_CPU_CACHELINE_64;
175+ } else if (CacheLineSize == 32) {
176+ uiCPU |= WELS_CPU_CACHELINE_32;
177+ } else if (CacheLineSize == 16) {
178+ uiCPU |= WELS_CPU_CACHELINE_16;
179+ }
180+ }
181+
182+ return uiCPU;
183+}
184+
185+
186+void WelsCPURestore (const uint32_t kuiCPU) {
187+ if (kuiCPU & (WELS_CPU_MMX | WELS_CPU_MMXEXT | WELS_CPU_3DNOW | WELS_CPU_3DNOWEXT)) {
188+ WelsEmms();
189+ }
207190 }
208191
209192 #endif

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