Revert "switch from binutils only to binutils-gdb, tag gdb-10.1-release"

This reverts commit 6c5c652ee12028f75cf95f9901979e53fbe22f8b.

Wolfgang Thaller committed 4 years ago

Commit 6ea1bcd1 parent 6c5c65220676 files · +514858 −5012976Browse files

Showing the changes to binutils/include/opcode (71 of 20676 files). Show all

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71 files

binutils/include/opcode/aarch64.h +44 −189
binutils/include/opcode/alpha.h +1 −1
binutils/include/opcode/arc-attrs.h +1 −1
binutils/include/opcode/arc-func.h +1 −1
binutils/include/opcode/arc.h +1 −6
binutils/include/opcode/arm.h +252 −328
binutils/include/opcode/avr.h +1 −1
binutils/include/opcode/bfin.h +1 −1
binutils/include/opcode/cgen.h +3 −10
binutils/include/opcode/convex.h +1 −1
binutils/include/opcode/cr16.h +1 −1
binutils/include/opcode/cris.h +1 −1
binutils/include/opcode/crx.h +2 −2
binutils/include/opcode/csky.h +0 −123
binutils/include/opcode/d10v.h +1 −1
binutils/include/opcode/d30v.h +2 −2
binutils/include/opcode/dlx.h +1 −1
binutils/include/opcode/ft32.h +1 −1
binutils/include/opcode/h8300.h +48 −48
binutils/include/opcode/hppa.h +1 −1
binutils/include/opcode/i386.h +1 −2
binutils/include/opcode/ia64.h +1 −1
binutils/include/opcode/m68hc11.h +1 −1
binutils/include/opcode/m68k.h +1 −1
binutils/include/opcode/metag.h +1 −1
binutils/include/opcode/mips.h +10 −24
binutils/include/opcode/mmix.h +9 −9
binutils/include/opcode/mn10200.h +1 −1
binutils/include/opcode/mn10300.h +1 −1
binutils/include/opcode/moxie.h +1 −1
binutils/include/opcode/msp430-decode.h +1 −1
binutils/include/opcode/msp430.h +1 −16
binutils/include/opcode/nds32.h +27 −186
binutils/include/opcode/nfp.h +1 −1
binutils/include/opcode/nios2.h +1 −1
binutils/include/opcode/nios2r1.h +1 −1
binutils/include/opcode/nios2r2.h +1 −1
binutils/include/opcode/np1.h +1 −1
binutils/include/opcode/ns32k.h +1 −1
binutils/include/opcode/pdp11.h +1 −1
binutils/include/opcode/pj.h +1 −1
binutils/include/opcode/pn.h +1 −1
binutils/include/opcode/ppc.h +42 −67
binutils/include/opcode/pru.h +1 −1
binutils/include/opcode/pyr.h +1 −1
binutils/include/opcode/riscv-opc.h +293 −305
binutils/include/opcode/riscv.h +7 −137
binutils/include/opcode/rl78.h +1 −1
binutils/include/opcode/rx.h +1 −33
binutils/include/opcode/s12z.h +0 −75
binutils/include/opcode/s390.h +1 −2
binutils/include/opcode/score-datadep.h +1 −1
binutils/include/opcode/score-inst.h +1 −1
binutils/include/opcode/sparc.h +1 −1
binutils/include/opcode/spu-insns.h +1 −1
binutils/include/opcode/spu.h +18 −21
binutils/include/opcode/tic30.h +1 −1
binutils/include/opcode/tic4x.h +6 −8
binutils/include/opcode/tic54x.h +1 −1
binutils/include/opcode/tic6x-control-registers.h +1 −1
binutils/include/opcode/tic6x-insn-formats.h +1 −1
binutils/include/opcode/tic6x-opcode-table.h +1 −1
binutils/include/opcode/tic6x.h +1 −1
binutils/include/opcode/tic80.h +283 −0
binutils/include/opcode/tilegx.h +1 −1
binutils/include/opcode/tilepro.h +4 −2
binutils/include/opcode/v850.h +2 −2
binutils/include/opcode/vax.h +1 −1
binutils/include/opcode/visium.h +1 −1
binutils/include/opcode/wasm.h +1 −1
binutils/include/opcode/xgate.h +1 −1

binutils/include/opcode/aarch64.h+44−189

@@ -1,6 +1,6 @@
1	1	/* AArch64 assembler/disassembler support.
2	2
3		− Copyright (C) 2009-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2009-2018 Free Software Foundation, Inc.
4	4	Contributed by ARM Ltd.
5	5
6	6	This file is part of GNU Binutils.
@@ -37,63 +37,35 @@ extern "C" { · 30 unmodified lines
37	37	typedef uint32_t aarch64_insn;
38	38
39	39	/* The following bitmasks control CPU features. */
40		−#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
41		−#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
42		−#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
43		−#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
44		−#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
45		−#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
46		−#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
47		−#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
48		−#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
49		−#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
50		−#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
51		−#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
52		−#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
53		−#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
54		−#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
55		−#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
56		−#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
57		−#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
58		−#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
59		−#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
60		−#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
61		−#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
62		−#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
63		−#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
64		−#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
65		−#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
66		−#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
67		−#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
68		−#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
69		−#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
70		−#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
71		−#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
72		−#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
73		−#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
74		−#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
75		−#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
76		−#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
77		−#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
78		−#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
79		−#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
80		−#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
81		−#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
82		−#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
83		−#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
84		−#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
85		−#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
86		−#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
87		−#define AARCH64_FEATURE_F32MM (1ULL << 53)
88		−#define AARCH64_FEATURE_F64MM (1ULL << 54)
89		−
90		−/* Crypto instructions are the combination of AES and SHA2. */
91		−#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 \| AARCH64_FEATURE_AES)
	40	+#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
	41	+#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
	42	+#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
	43	+#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
	44	+#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
	45	+#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
	46	+#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
	47	+#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
	48	+#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
	49	+#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
	50	+#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
	51	+#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
	52	+#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
	53	+#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
	54	+#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
	55	+#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
	56	+#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
	57	+#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
	58	+#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
	59	+#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
	60	+#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
	61	+#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
	62	+#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
	63	+#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
	64	+#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
92	65
93	66	/* Architectures are the sum of the base and extensions. */
94	67	#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
95		− AARCH64_FEATURE_V8_A \
96		− \| AARCH64_FEATURE_FP \
	68	+ AARCH64_FEATURE_FP \
97	69	\| AARCH64_FEATURE_SIMD)
98	70	#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
99	71	AARCH64_FEATURE_CRC \
@@ -113,24 +85,6 @@ typedef uint32_t aarch64_insn; · 13 unmodified lines
113	85	AARCH64_FEATURE_V8_4 \
114	86	\| AARCH64_FEATURE_DOTPROD \
115	87	\| AARCH64_FEATURE_F16_FML)
116		−#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
117		− AARCH64_FEATURE_V8_5 \
118		− \| AARCH64_FEATURE_FLAGMANIP \
119		− \| AARCH64_FEATURE_FRINTTS \
120		− \| AARCH64_FEATURE_SB \
121		− \| AARCH64_FEATURE_PREDRES \
122		− \| AARCH64_FEATURE_CVADP \
123		− \| AARCH64_FEATURE_BTI \
124		− \| AARCH64_FEATURE_SCXTNUM \
125		− \| AARCH64_FEATURE_ID_PFR2 \
126		− \| AARCH64_FEATURE_SSBS)
127		−#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
128		− AARCH64_FEATURE_V8_6 \
129		− \| AARCH64_FEATURE_BFLOAT16 \
130		− \| AARCH64_FEATURE_I8MM)
131		−#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
132		− AARCH64_FEATURE_V8_R) \
133		− & ~(AARCH64_FEATURE_V8_A \| AARCH64_FEATURE_LOR))
134	88
135	89	#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
136	90	#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
@@ -193,7 +147,6 @@ enum aarch64_opnd · 56 unmodified lines
193	147	AARCH64_OPND_Rm, /* Integer register as source. */
194	148	AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
195	149	AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
196		− AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
197	150	AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
198	151	AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
199	152	AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
@@ -256,12 +209,9 @@ enum aarch64_opnd · 56 unmodified lines
256	209	AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
257	210	AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
258	211	AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
259		− AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
260	212	AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
261		− AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
262	213	AARCH64_OPND_BIT_NUM, /* Immediate. */
263	214	AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
264		− AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
265	215	AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
266	216	AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
267	217	AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
@@ -297,11 +247,7 @@ enum aarch64_opnd · 29 unmodified lines
297	247	the mnemonic name for LDUR/STUR instructions
298	248	wherever there is no ambiguity. */
299	249	AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
300		− AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
301		− 16) immediate. */
302	250	AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
303		− AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
304		− 16) immediate. */
305	251	AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
306	252	AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
307	253	AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
@@ -312,15 +258,12 @@ enum aarch64_opnd · 4 unmodified lines
312	258	AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
313	259	AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
314	260	AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
315		− AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
316	261	AARCH64_OPND_BARRIER, /* Barrier operand. */
317	262	AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
318	263	AARCH64_OPND_PRFOP, /* Prefetch operation. */
319	264	AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
320		− AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
321	265
322	266	AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn\|SP>, #<simm4>16]. /
323		− AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn\|SP>, #<simm4>32]. /
324	267	AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn\|SP>, #<simm4>, MUL VL]. */
325	268	AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn\|SP>, #<simm4>2, MUL VL]. /
326	269	AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn\|SP>, #<simm4>3, MUL VL]. /
@@ -340,7 +283,6 @@ enum aarch64_opnd · 13 unmodified lines
340	283	AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn\|SP>, <Xm>, LSL #1]. */
341	284	AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn\|SP>, <Xm>, LSL #2]. */
342	285	AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn\|SP>, <Xm>, LSL #3]. */
343		− AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
344	286	AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn\|SP>, Zm.D]. */
345	287	AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn\|SP>, Zm.D, LSL #1]. */
346	288	AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn\|SP>, Zm.D, LSL #2]. */
@@ -376,7 +318,6 @@ enum aarch64_opnd · 29 unmodified lines
376	318	AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
377	319	AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
378	320	AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N90). /
379		− AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
380	321	AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
381	322	AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
382	323	AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
@@ -395,10 +336,8 @@ enum aarch64_opnd · 12 unmodified lines
395	336	AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
396	337	AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
397	338	AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
398		− AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
399	339	AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
400	340	AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
401		− AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
402	341	AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
403	342	AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
404	343	AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
@@ -418,15 +357,12 @@ enum aarch64_opnd · 13 unmodified lines
418	357	AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
419	358	AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
420	359	AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
421		− AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
422		− AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
423	360	AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
424	361	AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
425	362	AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
426	363	AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
427	364	AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
428	365	AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
429		− AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
430	366	AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
431	367	};
432	368
@@ -463,13 +399,11 @@ enum aarch64_opnd_qualifier · 30 unmodified lines
463	399	AARCH64_OPND_QLF_S_S,
464	400	AARCH64_OPND_QLF_S_D,
465	401	AARCH64_OPND_QLF_S_Q,
466		− /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
467		− or 2 x 2 byte are selected by the instruction. Other than that they have
468		− no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
469		− for syntactical reasons and is an exception from normal AArch64
470		− disassembly scheme. */
	402	+ /* This type qualifier has a special meaning in that it means that 4 x 1 byte
	403	+ are selected by the instruction. Other than that it has no difference
	404	+ with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
	405	+ reasons and is an exception from normal AArch64 disassembly scheme. */
471	406	AARCH64_OPND_QLF_S_4B,
472		− AARCH64_OPND_QLF_S_2H,
473	407
474	408	/* Qualifying an operand which is a SIMD vector register or a SIMD vector
475	409	register list; indicating register shape.
@@ -492,10 +426,6 @@ enum aarch64_opnd_qualifier · 16 unmodified lines
492	426	AARCH64_OPND_QLF_P_Z,
493	427	AARCH64_OPND_QLF_P_M,
494	428
495		− /* Used in scaled signed immediate that are scaled by a Tag granule
496		− like in stg, st2g, etc. */
497		− AARCH64_OPND_QLF_imm_tag,
498		−
499	429	/* Constraint on value. */
500	430	AARCH64_OPND_QLF_CR, /* CRn, CRm. */
501	431	AARCH64_OPND_QLF_imm_0_7,
@@ -519,7 +449,6 @@ enum aarch64_opnd_qualifier · 17 unmodified lines
519	449
520	450	enum aarch64_insn_class
521	451	{
522		− aarch64_misc,
523	452	addsub_carry,
524	453	addsub_ext,
525	454	addsub_imm,
@@ -601,19 +530,11 @@ enum aarch64_insn_class · 75 unmodified lines
601	530	sve_size_bhs,
602	531	sve_size_bhsd,
603	532	sve_size_hsd,
604		− sve_size_hsd2,
605	533	sve_size_sd,
606		− sve_size_bh,
607		− sve_size_sd2,
608		− sve_size_13,
609		− sve_shift_tsz_hsd,
610		− sve_shift_tsz_bhsd,
611		− sve_size_tsz_bhs,
612	534	testbranch,
613	535	cryptosm3,
614	536	cryptosm4,
615	537	dotproduct,
616		− bfloat16,
617	538	};
618	539
619	540	/* Opcode enumerators. */
@@ -720,17 +641,6 @@ enum aarch64_op · 100 unmodified lines
720	641	OP_TOTAL_NUM, /* Pseudo. */
721	642	};
722	643
723		−/* Error types. */
724		−enum err_type
725		−{
726		− ERR_OK,
727		− ERR_UND,
728		− ERR_UNP,
729		− ERR_NYI,
730		− ERR_VFI,
731		− ERR_NR_ENTRIES
732		−};
733		−
734	644	/* Maximum number of operands an instruction can have. */
735	645	#define AARCH64_MAX_OPND_NUM 6
736	646	/* Maximum number of qualifier sequences an instruction can have. */
@@ -752,13 +662,6 @@ empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) · 15 unmodified lines
752	662	return TRUE;
753	663	}
754	664
755		−/* Forward declare error reporting type. */
756		−typedef struct aarch64_operand_error aarch64_operand_error;
757		−/* Forward declare instruction sequence type. */
758		−typedef struct aarch64_instr_sequence aarch64_instr_sequence;
759		−/* Forward declare instruction definition. */
760		−typedef struct aarch64_inst aarch64_inst;
761		−
762	665	/* This structure holds information for a particular opcode. */
763	666
764	667	struct aarch64_opcode
@@ -797,19 +700,14 @@ struct aarch64_opcode · 32 unmodified lines
797	700	aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
798	701
799	702	/* Flags providing information about this instruction */
800		− uint64_t flags;
801		−
802		− /* Extra constraints on the instruction that the verifier checks. */
803		− uint32_t constraints;
	703	+ uint32_t flags;
804	704
805	705	/* If nonzero, this operand and operand 0 are both registers and
806	706	are required to have the same register number. */
807	707	unsigned char tied_operand;
808	708
809	709	/* If non-NULL, a function to verify that a given instruction is valid. */
810		− enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
811		− bfd_vma, bfd_boolean, aarch64_operand_error *,
812		− struct aarch64_instr_sequence *);
	710	+ bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
813	711	};
814	712
815	713	typedef struct aarch64_opcode aarch64_opcode;
@@ -873,18 +771,7 @@ extern aarch64_opcode aarch64_opcode_table[]; · 57 unmodified lines
873	771	#define F_SYS_READ (1ULL << 29)
874	772	/* This system instruction is used to write system registers. */
875	773	#define F_SYS_WRITE (1ULL << 30)
876		−/* This instruction has an extra constraint on it that imposes a requirement on
877		− subsequent instructions. */
878		−#define F_SCAN (1ULL << 31)
879		−/* Next bit is 32. */
880		−
881		−/* Instruction constraints. */
882		−/* This instruction has a predication constraint on the instruction at PC+4. */
883		−#define C_SCAN_MOVPRFX (1U << 0)
884		−/* This instruction's operation width is determined by the operand with the
885		− largest element size. */
886		−#define C_MAX_ELEM (1U << 1)
887		−/* Next bit is 2. */
	774	+/* Next bit is 31. */
888	775
889	776	static inline bfd_boolean
890	777	alias_opcode_p (const aarch64_opcode *opcode)
@@ -949,22 +836,18 @@ extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; · 58 unmodified lines
949	836	extern const struct aarch64_name_value_pair aarch64_prfops [32];
950	837	extern const struct aarch64_name_value_pair aarch64_hint_options [];
951	838
952		−#define AARCH64_MAX_SYSREG_NAME_LEN 32
953		−
954	839	typedef struct
955	840	{
956	841	const char * name;
957	842	aarch64_insn value;
958	843	uint32_t flags;
959		−
960		− /* A set of features, all of which are required for this system register to be
961		− available. */
962		− aarch64_feature_set features;
963	844	} aarch64_sys_reg;
964	845
965	846	extern const aarch64_sys_reg aarch64_sys_regs [];
966	847	extern const aarch64_sys_reg aarch64_pstatefields [];
967		−extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
	848	+extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
	849	+extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
	850	+ const aarch64_sys_reg *);
968	851	extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
969	852	const aarch64_sys_reg *);
970	853
@@ -978,14 +861,12 @@ typedef struct · 7 unmodified lines
978	861	extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
979	862	extern bfd_boolean
980	863	aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
981		− const char *reg_name, aarch64_insn,
982		− uint32_t, aarch64_feature_set);
	864	+ const aarch64_sys_ins_reg *);
983	865
984	866	extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
985	867	extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
986	868	extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
987	869	extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
988		−extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
989	870
990	871	/* Shift/extending operator kinds.
991	872	N.B. order is important; keep aarch64_operand_modifiers synced. */
@@ -1151,13 +1032,7 @@ struct aarch64_inst · 159 unmodified lines
1151	1032	aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1152	1033	};
1153	1034
1154		−/* Defining the HINT #imm values for the aarch64_hint_options. */
1155		−#define HINT_OPD_CSYNC 0x11
1156		−#define HINT_OPD_C 0x22
1157		−#define HINT_OPD_J 0x24
1158		−#define HINT_OPD_JC 0x26
1159		−#define HINT_OPD_NULL 0x00
1160		−
	1035	+typedef struct aarch64_inst aarch64_inst;
1161	1036
1162	1037	/* Diagnosis related declaration and interface. */
1163	1038
@@ -1235,27 +1110,14 @@ struct aarch64_operand_error · 71 unmodified lines
1235	1110	bfd_boolean non_fatal;
1236	1111	};
1237	1112
1238		−/* AArch64 sequence structure used to track instructions with F_SCAN
1239		− dependencies for both assembler and disassembler. */
1240		−struct aarch64_instr_sequence
1241		−{
1242		− /* The instruction that caused this sequence to be opened. */
1243		− aarch64_inst *instr;
1244		− /* The number of instructions the above instruction allows to be kept in the
1245		− sequence before an automatic close is done. */
1246		− int num_insns;
1247		− /* The instructions currently added to the sequence. */
1248		− aarch64_inst **current_insns;
1249		− /* The number of instructions already in the sequence. */
1250		− int next_insn;
1251		−};
	1113	+typedef struct aarch64_operand_error aarch64_operand_error;
1252	1114
1253	1115	/* Encoding entrypoint. */
1254	1116
1255	1117	extern int
1256	1118	aarch64_opcode_encode (const aarch64_opcode , const aarch64_inst ,
1257	1119	aarch64_insn , aarch64_opnd_qualifier_t ,
1258		− aarch64_operand_error , aarch64_instr_sequence );
	1120	+ aarch64_operand_error *);
1259	1121
1260	1122	extern const aarch64_opcode *
1261	1123	aarch64_replace_opcode (struct aarch64_inst *,
@@ -1271,8 +1133,7 @@ aarch64_get_opcode (enum aarch64_op); · 9 unmodified lines
1271	1133	extern void
1272	1134	aarch64_print_operand (char , size_t, bfd_vma, const aarch64_opcode ,
1273	1135	const aarch64_opnd_info , int, int , bfd_vma *,
1274		− char **,
1275		− aarch64_feature_set features);
	1136	+ char **);
1276	1137
1277	1138	/* Miscellaneous interface. */
1278	1139
@@ -1283,9 +1144,6 @@ extern aarch64_opnd_qualifier_t · 4 unmodified lines
1283	1144	aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1284	1145	const aarch64_opnd_qualifier_t, int);
1285	1146
1286		−extern bfd_boolean
1287		−aarch64_is_destructive_by_operands (const aarch64_opcode *);
1288		−
1289	1147	extern int
1290	1148	aarch64_num_of_operands (const aarch64_opcode *);
1291	1149
@@ -1295,12 +1153,9 @@ aarch64_stack_pointer_p (const aarch64_opnd_info *); · 3 unmodified lines
1295	1153	extern int
1296	1154	aarch64_zero_register_p (const aarch64_opnd_info *);
1297	1155
1298		−extern enum err_type
	1156	+extern int
1299	1157	aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1300		− aarch64_operand_error *);
1301		−
1302		−extern void
1303		−init_insn_sequence (const struct aarch64_inst , aarch64_instr_sequence );
	1158	+ aarch64_operand_error *errors);
1304	1159
1305	1160	/* Given an operand qualifier, return the expected data element size
1306	1161	of a qualified operand. */

binutils/include/opcode/alpha.h+1−1

@@ -1,5 +1,5 @@
1	1	/* alpha.h -- Header file for Alpha opcode table
2		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
3	3	Contributed by Richard Henderson <rth@tamu.edu>,
4	4	patterned after the PPC opcode table written by Ian Lance Taylor.
5	5

binutils/include/opcode/arc-attrs.h+1−1

@@ -1,4 +1,4 @@
1		−/* Copyright (C) 1994-2020 Free Software Foundation, Inc.
	1	+/* Copyright (C) 1994-2018 Free Software Foundation, Inc.
2	2
3	3	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
4	4

binutils/include/opcode/arc-func.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Replace functions for the ARC relocs.
2		− Copyright (C) 2015-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2015-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
5	5	the GNU Binutils.

binutils/include/opcode/arc.h+1−6

@@ -1,5 +1,5 @@
1	1	/* Opcode table for the ARC.
2		− Copyright (C) 1994-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1994-2018 Free Software Foundation, Inc.
3	3
4	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5	5
@@ -64,7 +64,6 @@ typedef enum · 58 unmodified lines
64	64	JUMP,
65	65	KERNEL,
66	66	LEAVE,
67		− LLOCK,
68	67	LOAD,
69	68	LOGICAL,
70	69	LOOP,
@@ -77,11 +76,9 @@ typedef enum · 6 unmodified lines
77	76	PMU,
78	77	POP,
79	78	PUSH,
80		− SCOND,
81	79	SJLI,
82	80	STORE,
83	81	SUB,
84		− SWITCH,
85	82	ULTRAIP,
86	83	XY
87	84	} insn_class_t;
@@ -100,7 +97,6 @@ typedef enum · 12 unmodified lines
100	97	DP = (1U << 6),
101	98	DPA = (1U << 7),
102	99	DPX = (1U << 8),
103		− FASTMATH = (1U << 23),
104	100	LL64 = (1U << 9),
105	101	MPY1E = (1U << 10),
106	102	MPY6E = (1U << 11),
@@ -204,7 +200,6 @@ extern int arc_opcode_len (const struct arc_opcode *opcode); · 97 unmodified lines
204	200	#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700 \
205	201	\| ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS)
206	202	#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCv2EM)
207		−#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 \| ARC_OPCODE_ARC700)
208	203	#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM \| ARC_OPCODE_ARCv2HS)
209	204	#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 \| ARC_OPCODE_ARCV2)
210	205

binutils/include/opcode/arm.h+252−328

@@ -1,5 +1,5 @@
1	1	/* ARM assembler/disassembler support.
2		− Copyright (C) 2004-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2004-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB and GAS.
5	5
@@ -19,183 +19,154 @@ · 13 unmodified lines
19	19	MA 02110-1301, USA. */
20	20
21	21	/* The following bitmasks control CPU extensions: */
22		−#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
23		−#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
24		−#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
25		−#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
26		−#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
27		−#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
28		−#define ARM_EXT_V4T 0x00000040 /* Thumb. */
29		−#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
30		−#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
31		−#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
32		−#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
33		−#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
34		−#define ARM_EXT_V6 0x00001000 /* ARM V6. */
35		−#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
36		−#define ARM_EXT_V8 0x00004000 /* ARMv8 w/o atomics. */
37		−#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
38		−#define ARM_EXT_DIV 0x00010000 /* Integer division. */
	22	+#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
	23	+#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
	24	+#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
	25	+#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
	26	+#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
	27	+#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
	28	+#define ARM_EXT_V4T 0x00000040 /* Thumb. */
	29	+#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
	30	+#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
	31	+#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
	32	+#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
	33	+#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
	34	+#define ARM_EXT_V6 0x00001000 /* ARM V6. */
	35	+#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
	36	+#define ARM_EXT_V8 0x00004000 /* ARMv8 w/o atomics. */
	37	+#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
	38	+#define ARM_EXT_DIV 0x00010000 /* Integer division. */
39	39	/* The 'M' in Arm V7M stands for Microcontroller.
40	40	On earlier architecture variants it stands for Multiply. */
41		−#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
42		−#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
43		−#define ARM_EXT_V7 0x00080000 /* Arm V7. */
44		−#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
45		−#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
46		−#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
47		−#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
48		−#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
49		−#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
50		−#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
51		− not in v7-M. */
52		−#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
53		−#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
54		−#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
55		−#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
56		− state. */
57		−#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
58		−
59		−#define ARM_EXT2_PAN 0x00000001 /* PAN extension. */
60		−#define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */
61		−#define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */
62		−#define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */
63		−#define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */
64		−#define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */
65		−#define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */
66		−#define ARM_EXT2_RAS 0x00000080 /* RAS extension. */
67		−#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
68		−#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
69		−#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */
70		−#define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML
71		− instructions. */
72		−#define ARM_EXT2_V8_5A 0x00001000 /* ARM V8.5A. */
73		−#define ARM_EXT2_SB 0x00002000 /* Speculation Barrier instruction. */
74		−#define ARM_EXT2_PREDRES 0x00004000 /* Prediction Restriction insns. */
75		−#define ARM_EXT2_V8_1M_MAIN 0x00008000 /* ARMv8.1-M Mainline. */
76		−#define ARM_EXT2_V8_6A 0x00010000 /* ARM V8.6A. */
77		−#define ARM_EXT2_BF16 0x00020000 /* ARMv8 bfloat16. */
78		−#define ARM_EXT2_I8MM 0x00040000 /* ARMv8.6A i8mm. */
79		−#define ARM_EXT2_CRC 0x00080000 /* ARMv8 CRC32 */
80		−#define ARM_EXT2_MVE 0x00100000 /* MVE Integer extension. */
81		−#define ARM_EXT2_MVE_FP 0x00200000 /* MVE Floating Point extension. */
82		−#define ARM_EXT2_CDE 0x00400000 /* Custom Datapath Extension. */
83		−#define ARM_EXT2_CDE0 0x00800000 /* Using CDE coproc 0. */
84		−#define ARM_EXT2_CDE1 0x01000000 /* Using CDE coproc 1. */
85		−#define ARM_EXT2_CDE2 0x02000000 /* Using CDE coproc 2. */
86		−#define ARM_EXT2_CDE3 0x04000000 /* Using CDE coproc 3. */
87		−#define ARM_EXT2_CDE4 0x08000000 /* Using CDE coproc 4. */
88		−#define ARM_EXT2_CDE5 0x10000000 /* Using CDE coproc 5. */
89		−#define ARM_EXT2_CDE6 0x20000000 /* Using CDE coproc 6. */
90		−#define ARM_EXT2_CDE7 0x40000000 /* Using CDE coproc 7. */
91		−#define ARM_EXT2_V8R 0x80000000 /* Arm V8R. */
	41	+#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
	42	+#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
	43	+#define ARM_EXT_V7 0x00080000 /* Arm V7. */
	44	+#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
	45	+#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
	46	+#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
	47	+#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
	48	+#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
	49	+#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
	50	+#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
	51	+ not in v7-M. */
	52	+#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
	53	+#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
	54	+#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
	55	+#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
	56	+ state. */
	57	+#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
	58	+
	59	+#define ARM_EXT2_PAN 0x00000001 /* PAN extension. */
	60	+#define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */
	61	+#define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */
	62	+#define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */
	63	+#define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */
	64	+#define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */
	65	+#define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */
	66	+#define ARM_EXT2_RAS 0x00000080 /* RAS extension. */
	67	+#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
	68	+#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
	69	+#define ARM_EXT2_V8_4A 0x00000400 /* ARM V8.4A. */
	70	+#define ARM_EXT2_FP16_FML 0x00000800 /* ARM V8.2A FP16-FML instructions. */
92	71
93	72	/* Co-processor space extensions. */
94		−#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
95		−#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
96		−#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology
97		− coprocessor. */
98		−#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology
99		− coprocessor version 2. */
100		−
101		−#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
102		−#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
103		−#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
104		−#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
105		−#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
106		−#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
107		−#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
108		−#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
109		−#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
110		−#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
111		−#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
112		−#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
113		−#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add. */
114		−#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add. */
115		−#define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */
116		−#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */
117		−#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
118		−/* Unused 0x00004000 */
119		−#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
120		−#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
121		−#define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */
	73	+#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
	74	+#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
	75	+#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
	76	+#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
	77	+
	78	+#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
	79	+#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
	80	+#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
	81	+#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
	82	+#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
	83	+#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
	84	+#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
	85	+#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
	86	+#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
	87	+#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
	88	+#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
	89	+#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
	90	+#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
	91	+#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
	92	+#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
	93	+#define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */
	94	+#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */
	95	+#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
	96	+#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
	97	+#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
	98	+#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
	99	+#define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */
122	100
123	101	/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
124	102	defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
125	103	ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
126	104	three more to cover cores prior to ARM6. Finally, there are cores which
127	105	implement further extensions in the co-processor space. */
128		−#define ARM_AEXT_V1 ARM_EXT_V1
129		−#define ARM_AEXT_V2 (ARM_AEXT_V1 \| ARM_EXT_V2)
130		−#define ARM_AEXT_V2S (ARM_AEXT_V2 \| ARM_EXT_V2S)
131		−#define ARM_AEXT_V3 (ARM_AEXT_V2S \| ARM_EXT_V3)
132		−#define ARM_AEXT_V3M (ARM_AEXT_V3 \| ARM_EXT_V3M)
133		−#define ARM_AEXT_V4xM (ARM_AEXT_V3 \| ARM_EXT_V4)
134		−#define ARM_AEXT_V4 (ARM_AEXT_V3M \| ARM_EXT_V4)
135		−#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM \| ARM_EXT_V4T \| ARM_EXT_OS)
136		−#define ARM_AEXT_V4T (ARM_AEXT_V4 \| ARM_EXT_V4T \| ARM_EXT_OS)
137		−#define ARM_AEXT_V5xM (ARM_AEXT_V4xM \| ARM_EXT_V5)
138		−#define ARM_AEXT_V5 (ARM_AEXT_V4 \| ARM_EXT_V5)
139		−#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM \| ARM_EXT_V4T \| ARM_EXT_V5T \
140		− \| ARM_EXT_OS)
141		−#define ARM_AEXT_V5T (ARM_AEXT_V5 \| ARM_EXT_V4T \| ARM_EXT_V5T \
142		− \| ARM_EXT_OS)
143		−#define ARM_AEXT_V5TExP (ARM_AEXT_V5T \| ARM_EXT_V5ExP)
144		−#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP \| ARM_EXT_V5E)
145		−#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE \| ARM_EXT_V5J)
146		−#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ \| ARM_EXT_V6)
147		−#define ARM_AEXT_V6K (ARM_AEXT_V6 \| ARM_EXT_V6K)
148		−#define ARM_AEXT_V6Z (ARM_AEXT_V6K \| ARM_EXT_SEC)
149		−#define ARM_AEXT_V6KZ (ARM_AEXT_V6K \| ARM_EXT_SEC)
150		−#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \| ARM_EXT_V6T2 \| ARM_EXT_V6_NOTM \
151		− \| ARM_EXT_THUMB_MSR \
152		− \| ARM_EXT_V6_DSP )
153		−#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K)
154		−#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 \| ARM_EXT_SEC)
155		−#define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K \| ARM_EXT_SEC)
156		−#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 \| ARM_EXT_V7 \| ARM_EXT_BARRIER)
157		−#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM \| ARM_EXT_V7A)
158		−#define ARM_AEXT_V7VE (ARM_AEXT_V7A \| ARM_EXT_DIV \| ARM_EXT_ADIV \
159		− \| ARM_EXT_VIRT \| ARM_EXT_SEC \
160		− \| ARM_EXT_MP)
161		−#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM \| ARM_EXT_V7R \| ARM_EXT_DIV)
162		−#define ARM_AEXT_NOTM (ARM_AEXT_V4 \| ARM_EXT_V5ExP \| ARM_EXT_V5J \
163		− \| ARM_EXT_V6_DSP \
164		− \| ARM_EXT_V6_NOTM)
165		−#define ARM_AEXT_V6M ((ARM_AEXT_V6K \| ARM_EXT_V6M \| ARM_EXT_BARRIER \
166		− \| ARM_EXT_THUMB_MSR) \
167		− & ~(ARM_AEXT_NOTM \| ARM_EXT_OS))
168		−#define ARM_AEXT_V6SM (ARM_AEXT_V6M \| ARM_EXT_OS)
169		−#define ARM_AEXT_V7M ((ARM_AEXT_V7_ARM \| ARM_EXT_V6M \| ARM_EXT_V7M \
170		− \| ARM_EXT_DIV) \
171		− & ~ARM_AEXT_NOTM)
172		−#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
173		−#define ARM_AEXT_V7EM (ARM_AEXT_V7M \| ARM_EXT_V5ExP \| ARM_EXT_V6_DSP)
174		−#define ARM_AEXT_V8A (ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC \
175		− \| ARM_EXT_DIV \| ARM_EXT_ADIV \
176		− \| ARM_EXT_VIRT \| ARM_EXT_V8)
	106	+#define ARM_AEXT_V1 ARM_EXT_V1
	107	+#define ARM_AEXT_V2 (ARM_AEXT_V1 \| ARM_EXT_V2)
	108	+#define ARM_AEXT_V2S (ARM_AEXT_V2 \| ARM_EXT_V2S)
	109	+#define ARM_AEXT_V3 (ARM_AEXT_V2S \| ARM_EXT_V3)
	110	+#define ARM_AEXT_V3M (ARM_AEXT_V3 \| ARM_EXT_V3M)
	111	+#define ARM_AEXT_V4xM (ARM_AEXT_V3 \| ARM_EXT_V4)
	112	+#define ARM_AEXT_V4 (ARM_AEXT_V3M \| ARM_EXT_V4)
	113	+#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM \| ARM_EXT_V4T \| ARM_EXT_OS)
	114	+#define ARM_AEXT_V4T (ARM_AEXT_V4 \| ARM_EXT_V4T \| ARM_EXT_OS)
	115	+#define ARM_AEXT_V5xM (ARM_AEXT_V4xM \| ARM_EXT_V5)
	116	+#define ARM_AEXT_V5 (ARM_AEXT_V4 \| ARM_EXT_V5)
	117	+#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM \| ARM_EXT_V4T \| ARM_EXT_V5T \
	118	+ \| ARM_EXT_OS)
	119	+#define ARM_AEXT_V5T (ARM_AEXT_V5 \| ARM_EXT_V4T \| ARM_EXT_V5T \
	120	+ \| ARM_EXT_OS)
	121	+#define ARM_AEXT_V5TExP (ARM_AEXT_V5T \| ARM_EXT_V5ExP)
	122	+#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP \| ARM_EXT_V5E)
	123	+#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE \| ARM_EXT_V5J)
	124	+#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ \| ARM_EXT_V6)
	125	+#define ARM_AEXT_V6K (ARM_AEXT_V6 \| ARM_EXT_V6K)
	126	+#define ARM_AEXT_V6Z (ARM_AEXT_V6K \| ARM_EXT_SEC)
	127	+#define ARM_AEXT_V6KZ (ARM_AEXT_V6K \| ARM_EXT_SEC)
	128	+#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
	129	+ \| ARM_EXT_V6T2 \| ARM_EXT_V6_NOTM \| ARM_EXT_THUMB_MSR \
	130	+ \| ARM_EXT_V6_DSP )
	131	+#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K)
	132	+#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 \| ARM_EXT_SEC)
	133	+#define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K \| ARM_EXT_SEC)
	134	+#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 \| ARM_EXT_V7 \| ARM_EXT_BARRIER)
	135	+#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM \| ARM_EXT_V7A)
	136	+#define ARM_AEXT_V7VE (ARM_AEXT_V7A \| ARM_EXT_DIV \| ARM_EXT_ADIV \
	137	+ \| ARM_EXT_VIRT \| ARM_EXT_SEC \| ARM_EXT_MP)
	138	+#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM \| ARM_EXT_V7R \| ARM_EXT_DIV)
	139	+#define ARM_AEXT_NOTM \
	140	+ (ARM_AEXT_V4 \| ARM_EXT_V5ExP \| ARM_EXT_V5J \| ARM_EXT_V6_NOTM \
	141	+ \| ARM_EXT_V6_DSP )
	142	+#define ARM_AEXT_V6M_ONLY \
	143	+ ((ARM_EXT_BARRIER \| ARM_EXT_V6M \| ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
	144	+#define ARM_AEXT_V6M \
	145	+ ((ARM_AEXT_V6K \| ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM \| ARM_EXT_OS))
	146	+#define ARM_AEXT_V6SM (ARM_AEXT_V6M \| ARM_EXT_OS)
	147	+#define ARM_AEXT_V7M \
	148	+ ((ARM_AEXT_V7_ARM \| ARM_EXT_V6M \| ARM_EXT_V7M \| ARM_EXT_DIV) \
	149	+ & ~(ARM_AEXT_NOTM))
	150	+#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
	151	+#define ARM_AEXT_V7EM \
	152	+ (ARM_AEXT_V7M \| ARM_EXT_V5ExP \| ARM_EXT_V6_DSP)
	153	+#define ARM_AEXT_V8A \
	154	+ (ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC \| ARM_EXT_DIV \| ARM_EXT_ADIV \
	155	+ \| ARM_EXT_VIRT \| ARM_EXT_V8)
177	156	#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M \| ARM_EXT2_ATOMICS)
178		−#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR \| ARM_EXT2_V8A)
179		−#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A \| ARM_EXT2_PAN)
180		−#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A \| ARM_EXT2_V8_2A \| ARM_EXT2_RAS)
181		−#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A \| ARM_EXT2_V8_3A)
182		−#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A \| ARM_EXT2_FP16_FML \
183		− \| ARM_EXT2_V8_4A)
184		−#define ARM_AEXT2_V8_5A (ARM_AEXT2_V8_4A \| ARM_EXT2_V8_5A \| ARM_EXT2_SB \
185		− \| ARM_EXT2_PREDRES)
186		−#define ARM_AEXT2_V8_6A (ARM_AEXT2_V8_5A \| ARM_EXT2_V8_6A \| ARM_EXT2_BF16)
187		−#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM \| ARM_EXT_DIV)
188		−#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
189		−#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
190		−#define ARM_AEXT2_V8M_BASE (ARM_EXT2_V8M \| ARM_EXT2_ATOMICS \
191		− \| ARM_EXT2_V6T2_V8M)
192		−#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M_BASE \| ARM_EXT2_V8M_MAIN)
193		−#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
194		−#define ARM_AEXT_V8R ARM_AEXT_V8A
195		−#define ARM_AEXT2_V8R (ARM_EXT2_V8R \| ARM_AEXT2_V8AR)
196		−#define ARM_AEXT_V8_1M_MAIN ARM_AEXT_V8M_MAIN
197		−#define ARM_AEXT2_V8_1M_MAIN (ARM_AEXT2_V8M_MAIN \| ARM_EXT2_V8_1M_MAIN \
198		− \| ARM_EXT2_FP16_INST)
	157	+#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR \| ARM_EXT2_V8A)
	158	+#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A \| ARM_EXT2_PAN)
	159	+#define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A \| ARM_EXT2_V8_2A \| ARM_EXT2_RAS)
	160	+#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A \| ARM_EXT2_V8_3A)
	161	+#define ARM_AEXT2_V8_4A (ARM_AEXT2_V8_3A \| ARM_EXT2_FP16_FML \| ARM_EXT2_V8_4A)
	162	+#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM \| ARM_EXT_DIV)
	163	+#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
	164	+#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
	165	+#define ARM_AEXT2_V8M (ARM_EXT2_V8M \| ARM_EXT2_ATOMICS \| ARM_EXT2_V6T2_V8M)
	166	+#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M \| ARM_EXT2_V8M_MAIN)
	167	+#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
	168	+#define ARM_AEXT_V8R ARM_AEXT_V8A
	169	+#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
199	170
200	171	/* Processors with specific extensions in the co-processor space. */
201	172	#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
@@ -205,185 +176,136 @@ · 3 unmodified lines
205	176	ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT \
206	177	\| ARM_CEXT_IWMMXT2)
207	178
208		−#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD \| FPU_ENDIAN_PURE)
209		−#define FPU_VFP_V1 (FPU_VFP_V1xD \| FPU_VFP_EXT_V1)
210		−#define FPU_VFP_V2 (FPU_VFP_V1 \| FPU_VFP_EXT_V2)
211		−#define FPU_VFP_V3D16 (FPU_VFP_V2 \| FPU_VFP_EXT_V3xD \
212		− \| FPU_VFP_EXT_V3)
213		−#define FPU_VFP_V3 (FPU_VFP_V3D16 \| FPU_VFP_EXT_D32)
214		−#define FPU_VFP_V3xD (FPU_VFP_V1xD \| FPU_VFP_EXT_V2 \
215		− \| FPU_VFP_EXT_V3xD)
216		−#define FPU_VFP_V4D16 (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16 \
217		− \| FPU_VFP_EXT_FMA)
218		−#define FPU_VFP_V4 (FPU_VFP_V3 \| FPU_VFP_EXT_FP16 \
219		− \| FPU_VFP_EXT_FMA)
220		−#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD \| FPU_VFP_EXT_FP16 \
221		− \| FPU_VFP_EXT_FMA)
222		−#define FPU_VFP_V5D16 (FPU_VFP_V4D16 \| FPU_VFP_EXT_ARMV8xD \
223		− \| FPU_VFP_EXT_ARMV8)
	179	+#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD \| FPU_ENDIAN_PURE)
	180	+#define FPU_VFP_V1 (FPU_VFP_V1xD \| FPU_VFP_EXT_V1)
	181	+#define FPU_VFP_V2 (FPU_VFP_V1 \| FPU_VFP_EXT_V2)
	182	+#define FPU_VFP_V3D16 (FPU_VFP_V2 \| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_V3)
	183	+#define FPU_VFP_V3 (FPU_VFP_V3D16 \| FPU_VFP_EXT_D32)
	184	+#define FPU_VFP_V3xD (FPU_VFP_V1xD \| FPU_VFP_EXT_V2 \| FPU_VFP_EXT_V3xD)
	185	+#define FPU_VFP_V4D16 (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
	186	+#define FPU_VFP_V4 (FPU_VFP_V3 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
	187	+#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
	188	+#define FPU_VFP_V5D16 (FPU_VFP_V4D16 \| FPU_VFP_EXT_ARMV8xD \| FPU_VFP_EXT_ARMV8)
224	189	#define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 \| FPU_VFP_EXT_ARMV8xD)
225		−#define FPU_VFP_ARMV8 (FPU_VFP_V4 \| FPU_VFP_EXT_ARMV8 \
226		− \| FPU_VFP_EXT_ARMV8xD)
227		−#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA \
228		− \| FPU_NEON_EXT_ARMV8)
229		−#define FPU_NEON_ARMV8_1 (FPU_NEON_ARMV8 \| FPU_NEON_EXT_RDMA)
230		−#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
231		−#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD \| FPU_VFP_EXT_V1 \
232		− \| FPU_VFP_EXT_V2 \
233		− \| FPU_VFP_EXT_V3xD \
234		− \| FPU_VFP_EXT_FMA \
235		− \| FPU_NEON_EXT_FMA \
236		− \| FPU_VFP_EXT_V3 \
237		− \| FPU_NEON_EXT_V1 \
238		− \| FPU_VFP_EXT_D32)
239		−#define FPU_FPA (FPU_FPA_EXT_V1 \| FPU_FPA_EXT_V2)
	190	+#define FPU_VFP_ARMV8 (FPU_VFP_V4 \| FPU_VFP_EXT_ARMV8 \| FPU_VFP_EXT_ARMV8xD)
	191	+#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA \| FPU_NEON_EXT_ARMV8)
	192	+#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
	193	+#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD \| FPU_VFP_EXT_V1 \| FPU_VFP_EXT_V2 \
	194	+ \| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_FMA \| FPU_NEON_EXT_FMA \
	195	+ \| FPU_VFP_EXT_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_D32)
	196	+#define FPU_FPA (FPU_FPA_EXT_V1 \| FPU_FPA_EXT_V2)
240	197
241	198	/* Deprecated. */
242		−#define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
	199	+#define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
243	200
244		−#define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
245		−#define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA)
	201	+#define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
	202	+#define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA)
246	203
247		−#define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
248		−#define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1)
249		−#define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2)
	204	+#define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
	205	+#define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1)
	206	+#define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2)
250	207	#define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16)
251		−#define FPU_ARCH_VFP_V3D16_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3D16 \
252		− \| FPU_VFP_EXT_FP16)
253		−#define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3)
254		−#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \
255		− \| FPU_VFP_EXT_FP16)
	208	+#define FPU_ARCH_VFP_V3D16_FP16 \
	209	+ ARM_FEATURE_COPROC (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16)
	210	+#define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3)
	211	+#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_VFP_EXT_FP16)
256	212	#define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD)
257		−#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \
258		− \| FPU_VFP_EXT_FP16)
259		−#define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
260		−#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
261		− ARM_FEATURE_COPROC (FPU_VFP_V3 \
262		− \| FPU_NEON_EXT_V1)
263		−#define FPU_ARCH_NEON_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \
264		− \| FPU_NEON_EXT_V1 \
265		− \| FPU_VFP_EXT_FP16)
266		−#define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
267		−#define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
268		−#define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
269		−#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
270		−#define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
271		−#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
272		−#define FPU_ARCH_NEON_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4 \
273		− \| FPU_NEON_EXT_V1 \
274		− \| FPU_NEON_EXT_FMA)
275		−#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
276		−#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
277		− \| FPU_VFP_ARMV8)
278		−#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
279		− ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \
280		− \| FPU_NEON_ARMV8 \
281		− \| FPU_VFP_ARMV8)
282		−#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \
283		− ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \
284		− \| FPU_NEON_ARMV8 \
285		− \| FPU_VFP_ARMV8 \
286		− \| FPU_NEON_EXT_DOTPROD)
287		−#define FPU_ARCH_NEON_VFP_ARMV8_1 \
288		− ARM_FEATURE_COPROC (FPU_NEON_ARMV8_1 \
289		− \| FPU_VFP_ARMV8)
290		−#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
291		− ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \
292		− \| FPU_NEON_ARMV8_1 \
293		− \| FPU_VFP_ARMV8)
294		−
295		−#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \
296		− ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD \
297		− \| FPU_NEON_ARMV8_1 \
298		− \| FPU_VFP_ARMV8)
299		−
300		−#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16 \
301		− ARM_FEATURE (0, ARM_EXT2_FP16_INST, \
302		− FPU_NEON_ARMV8_1 \| FPU_VFP_ARMV8)
303		−
304		−#define FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML \
305		− ARM_FEATURE (0, ARM_EXT2_FP16_INST \| ARM_EXT2_FP16_FML, \
306		− FPU_NEON_ARMV8_1 \| FPU_VFP_ARMV8)
307		−
308		−#define FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML \
309		− ARM_FEATURE (0, ARM_EXT2_FP16_INST \| ARM_EXT2_FP16_FML, \
310		− FPU_NEON_ARMV8_1 \| FPU_VFP_ARMV8 \| FPU_NEON_EXT_DOTPROD)
	213	+#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \
	214	+ \| FPU_VFP_EXT_FP16)
	215	+#define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
	216	+#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
	217	+ ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_NEON_EXT_V1)
	218	+#define FPU_ARCH_NEON_FP16 \
	219	+ ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_FP16)
	220	+#define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
	221	+#define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
	222	+#define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
	223	+#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
	224	+#define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
	225	+#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
	226	+#define FPU_ARCH_NEON_VFP_V4 \
	227	+ ARM_FEATURE_COPROC (FPU_VFP_V4 \| FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA)
	228	+#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
	229	+#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
	230	+ \| FPU_VFP_ARMV8)
	231	+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
	232	+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8)
	233	+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD \
	234	+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8 \
	235	+ \| FPU_NEON_EXT_DOTPROD)
	236	+#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
	237	+#define FPU_ARCH_NEON_VFP_ARMV8_1 \
	238	+ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
	239	+ \| FPU_VFP_ARMV8 \
	240	+ \| FPU_NEON_EXT_RDMA)
	241	+#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
	242	+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8 \
	243	+ \| FPU_NEON_EXT_RDMA)
	244	+#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \
	245	+ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8)
311	246
312		−#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4 \
313		− ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \
314		− \| FPU_NEON_ARMV8_1 \
315		− \| FPU_VFP_ARMV8 \
316		− \| FPU_NEON_EXT_DOTPROD)
317	247
318	248	#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
319	249
320	250	#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
321	251
322		−#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
323		−#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
324		−#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
325		−#define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
326		−#define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
327		−#define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
328		−#define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
329		−#define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
330		−#define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
331		−#define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
332		−#define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
333		−#define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
334		−#define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
335		−#define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
336		−#define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
337		−#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
338		−#define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
339		−#define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
340		−#define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
341		−#define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
342		−#define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M)
343		−#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M)
344		−#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M)
345		−#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M)
346		−#define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
347		−#define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
348		−#define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M)
349		−#define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M)
350		−#define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M)
351		−#define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M)
352		−#define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M)
353		−#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M)
354		−#define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A)
355		−#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, \
356		− ARM_AEXT2_V8A \| ARM_EXT2_CRC)
357		−#define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A \
358		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA)
359		−#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A \
360		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA)
361		−#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A \
362		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA)
363		−#define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A \
364		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \
365		− \| FPU_NEON_EXT_DOTPROD)
366		−#define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_5A \
367		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \
368		− \| FPU_NEON_EXT_DOTPROD)
369		−#define ARM_ARCH_V8_6A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_6A \
370		− \| ARM_EXT2_CRC, FPU_NEON_EXT_RDMA \
371		− \| FPU_NEON_EXT_DOTPROD)
372		−#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, \
373		− ARM_AEXT2_V8M_BASE)
374		−#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
375		− ARM_AEXT2_V8M_MAIN)
376		−#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
377		− ARM_AEXT2_V8M_MAIN_DSP)
378		−#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
379		−#define ARM_ARCH_V8_1M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8_1M_MAIN, \
380		− ARM_AEXT2_V8_1M_MAIN)
	252	+#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
	253	+#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
	254	+#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
	255	+#define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
	256	+#define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
	257	+#define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
	258	+#define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
	259	+#define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
	260	+#define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
	261	+#define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
	262	+#define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
	263	+#define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
	264	+#define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
	265	+#define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
	266	+#define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
	267	+#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
	268	+#define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
	269	+#define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
	270	+#define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
	271	+#define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
	272	+#define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M)
	273	+#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M)
	274	+#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M)
	275	+#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M)
	276	+#define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
	277	+#define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
	278	+#define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M)
	279	+#define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M)
	280	+#define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M)
	281	+#define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M)
	282	+#define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M)
	283	+#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M)
	284	+#define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A)
	285	+#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \
	286	+ CRC_EXT_ARMV8)
	287	+#define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \
	288	+ CRC_EXT_ARMV8 \| FPU_NEON_EXT_RDMA)
	289	+#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \
	290	+ CRC_EXT_ARMV8 \| FPU_NEON_EXT_RDMA)
	291	+#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \
	292	+ CRC_EXT_ARMV8 \| FPU_NEON_EXT_RDMA)
	293	+#define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A, \
	294	+ CRC_EXT_ARMV8 \| FPU_NEON_EXT_RDMA \
	295	+ \| FPU_NEON_EXT_DOTPROD)
	296	+#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
	297	+#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
	298	+ ARM_AEXT2_V8M_MAIN)
	299	+#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
	300	+ ARM_AEXT2_V8M_MAIN_DSP)
	301	+#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
381	302
382	303	/* Some useful combinations: */
383	304	#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
384	305	#define FPU_NONE ARM_FEATURE_LOW (0, 0)
385		−#define ARM_ANY ARM_FEATURE (-1, -1 & ~ (ARM_EXT2_MVE \| ARM_EXT2_MVE_FP), 0) /* Any basic core. */
	306	+#define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */
386	307	#define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */
	308	+#define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */
387	309	#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA \| FPU_VFP_HARD \| FPU_MAVERICK)
388	310	/* Extensions containing some Thumb-2 instructions. If any is present, Thumb
389	311	ISA is Thumb-2. */
@@ -399,6 +321,8 @@ · 9 unmodified lines
399	321	/* v7-r+idiv. */
400	322	#define ARM_ARCH_V7R_IDIV \
401	323	ARM_FEATURE_CORE (ARM_AEXT_V7R \| ARM_EXT_ADIV, ARM_EXT2_V6T2_V8M)
	324	+/* Features that are present in v6M and v6S-M but not other v6 cores. */
	325	+#define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY)
402	326	/* v8-a+fp. */
403	327	#define ARM_ARCH_V8A_FP \
404	328	ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_VFP_ARMV8)

binutils/include/opcode/avr.h+1−1

@@ -1,6 +1,6 @@
1	1	/* Opcode table for the Atmel AVR micro controllers.
2	2
3		− Copyright (C) 2000-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2000-2018 Free Software Foundation, Inc.
4	4	Contributed by Denis Chertykov <denisc@overta.ru>
5	5
6	6	This program is free software; you can redistribute it and/or modify

binutils/include/opcode/bfin.h+1−1

@@ -1,5 +1,5 @@
1	1	/* bfin.h -- Header file for ADI Blackfin opcode table
2		− Copyright (C) 2005-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2005-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB, GAS, and the GNU binutils.
5	5

binutils/include/opcode/cgen.h+3−10

@@ -1,6 +1,6 @@
1	1	/* Header file for targets using CGEN: Cpu tools GENerator.
2	2
3		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
4	4
5	5	This file is part of GDB, the GNU debugger, and the GNU Binutils.
6	6
@@ -1392,9 +1392,7 @@ enum cgen_cpu_open_arg { · 1385 unmodified lines
1392	1392	Multiple machines can be specified by repeated use. */
1393	1393	CGEN_CPU_OPEN_BFDMACH,
1394	1394	/* Select endian, arg is CGEN_ENDIAN_. /
1395		− CGEN_CPU_OPEN_ENDIAN,
1396		− /* Select instruction endian, arg is CGEN_ENDIAN_. /
1397		− CGEN_CPU_OPEN_INSN_ENDIAN,
	1395	+ CGEN_CPU_OPEN_ENDIAN
1398	1396	};
1399	1397
1400	1398	/* Open a cpu descriptor table for use.
@@ -1463,13 +1461,8 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands · 62 unmodified lines
1463	1461	/* Cover fns to bfd_get/set. */
1464	1462
1465	1463	extern CGEN_INSN_INT cgen_get_insn_value
1466		− (CGEN_CPU_DESC, unsigned char *, int, int);
1467		−extern void cgen_put_insn_value
1468		− (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int);
1469		−
1470		−extern CGEN_INSN_INT cgen_get_base_insn_value
1471	1464	(CGEN_CPU_DESC, unsigned char *, int);
1472		−extern void cgen_put_base_insn_value
	1465	+extern void cgen_put_insn_value
1473	1466	(CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT);
1474	1467
1475	1468	/* Read in a cpu description file.

binutils/include/opcode/convex.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Information for instruction disassembly on the Convex.
2		− Copyright (C) 1989-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB.
5	5

binutils/include/opcode/cr16.h+1−1

@@ -1,5 +1,5 @@
1	1	/* cr16.h -- Header file for CR16 opcode and register tables.
2		− Copyright (C) 2007-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2007-2018 Free Software Foundation, Inc.
3	3	Contributed by M R Swami Reddy
4	4
5	5	This file is part of GAS, GDB and the GNU binutils.

binutils/include/opcode/cris.h+1−1

@@ -1,5 +1,5 @@
1	1	/* cris.h -- Header file for CRIS opcode and register tables.
2		− Copyright (C) 2000-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2000-2018 Free Software Foundation, Inc.
3	3	Contributed by Axis Communications AB, Lund, Sweden.
4	4	Originally written for GAS 1.38.1 by Mikael Asker.
5	5	Updated, BFDized and GNUified by Hans-Peter Nilsson.

binutils/include/opcode/crx.h+2−2

@@ -1,5 +1,5 @@
1	1	/* crx.h -- Header file for CRX opcode and register tables.
2		− Copyright (C) 2004-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2004-2018 Free Software Foundation, Inc.
3	3	Contributed by Tomer Levi, NSC, Israel.
4	4	Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
5	5	Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
@@ -260,7 +260,7 @@ typedef struct · 254 unmodified lines
260	260	/* Size (in words). */
261	261	unsigned int size;
262	262	/* Constant prefix (matched by the disassembler). */
263		− unsigned int match;
	263	+ unsigned long match;
264	264	/* Match size (in bits). */
265	265	int match_bits;
266	266	/* Attributes. */

binutils/include/opcode/csky.h+0−123

@@ -1,123 +0,0 @@
1		−/* C-SKY assembler/disassembler support.
2		− Copyright (C) 2004-2020 Free Software Foundation, Inc.
3		− Contributed by C-SKY Microsystems and Mentor Graphics.
4		−
5		− This file is part of GDB and GAS.
6		−
7		− GDB and GAS are free software; you can redistribute it and/or
8		− modify it under the terms of the GNU General Public License as
9		− published by the Free Software Foundation; either version 3, or (at
10		− your option) any later version.
11		−
12		− GDB and GAS are distributed in the hope that it will be useful, but
13		− WITHOUT ANY WARRANTY; without even the implied warranty of
14		− MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15		− General Public License for more details.
16		−
17		− You should have received a copy of the GNU General Public License
18		− along with GDB or GAS; see the file COPYING3. If not, write to the
19		− Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20		− MA 02110-1301, USA. */
21		−
22		−#include "dis-asm.h"
23		−
24		−/* The following bitmasks control instruction set architecture. */
25		−#define CSKYV1_ISA_E1 ((bfd_uint64_t)1 << 0)
26		−#define CSKYV2_ISA_E1 ((bfd_uint64_t)1 << 1)
27		−#define CSKYV2_ISA_1E2 ((bfd_uint64_t)1 << 2)
28		−#define CSKYV2_ISA_2E3 ((bfd_uint64_t)1 << 3)
29		−#define CSKYV2_ISA_3E7 ((bfd_uint64_t)1 << 4)
30		−#define CSKYV2_ISA_7E10 ((bfd_uint64_t)1 << 5)
31		−#define CSKYV2_ISA_3E3R1 ((bfd_uint64_t)1 << 6)
32		−#define CSKYV2_ISA_3E3R2 ((bfd_uint64_t)1 << 7)
33		−#define CSKYV2_ISA_10E60 ((bfd_uint64_t)1 << 8)
34		−#define CSKYV2_ISA_3E3R3 ((bfd_uint64_t)1 << 9)
35		−
36		−#define CSKY_ISA_TRUST ((bfd_uint64_t)1 << 11)
37		−#define CSKY_ISA_CACHE ((bfd_uint64_t)1 << 12)
38		−#define CSKY_ISA_NVIC ((bfd_uint64_t)1 << 13)
39		−#define CSKY_ISA_CP ((bfd_uint64_t)1 << 14)
40		−#define CSKY_ISA_MP ((bfd_uint64_t)1 << 15)
41		−#define CSKY_ISA_MP_1E2 ((bfd_uint64_t)1 << 16)
42		−#define CSKY_ISA_JAVA ((bfd_uint64_t)1 << 17)
43		−#define CSKY_ISA_MAC ((bfd_uint64_t)1 << 18)
44		−#define CSKY_ISA_MAC_DSP ((bfd_uint64_t)1 << 19)
45		−
46		−/* Base ISA for csky v1 and v2. */
47		−#define CSKY_ISA_DSP ((bfd_uint64_t)1 << 20)
48		−#define CSKY_ISA_DSP_1E2 ((bfd_uint64_t)1 << 21)
49		−#define CSKY_ISA_DSP_ENHANCE ((bfd_uint64_t)1 << 22)
50		−#define CSKY_ISA_DSPE60 ((bfd_uint64_t)1 << 23)
51		−
52		−/* Base float instruction (803f & 810f). */
53		−#define CSKY_ISA_FLOAT_E1 ((bfd_uint64_t)1 << 25)
54		−/* M_FLOAT support (810f). */
55		−#define CSKY_ISA_FLOAT_1E2 ((bfd_uint64_t)1 << 26)
56		−/* 803 support (803f). */
57		−#define CSKY_ISA_FLOAT_1E3 ((bfd_uint64_t)1 << 27)
58		−/* 807 support (803f & 807f). */
59		−#define CSKY_ISA_FLOAT_3E4 ((bfd_uint64_t)1 << 28)
60		−/* 860 support. */
61		−#define CSKY_ISA_FLOAT_7E60 ((bfd_uint64_t)1 << 36)
62		−/* Vector DSP support. */
63		−#define CSKY_ISA_VDSP ((bfd_uint64_t)1 << 29)
64		−#define CSKY_ISA_VDSP_2 ((bfd_uint64_t)1 << 30)
65		−
66		−/* The following bitmasks control cpu architecture for CSKY. */
67		−#define CSKY_ABI_V1 (1 << 28)
68		−#define CSKY_ABI_V2 (2 << 28)
69		−#define CSKY_ARCH_MASK 0x0000001F
70		−#define CSKY_ABI_MASK 0xF0000000
71		−
72		−#define CSKY_ARCH_510 0x1
73		−#define CSKY_ARCH_610 0x2
74		−#define CSKY_ARCH_801 0xa
75		−#define CSKY_ARCH_802 0x10
76		−#define CSKY_ARCH_803 0x9
77		−/* 804 use the same arch flag as 803 yet. */
78		−#define CSKY_ARCH_804 0x9
79		−#define CSKY_ARCH_805 0x11
80		−#define CSKY_ARCH_807 0x6
81		−#define CSKY_ARCH_810 0x8
82		−#define CSKY_ARCH_860 0xb
83		−/* 800 is a special arch supporting all instructions for ABIV2. */
84		−#define CSKY_ARCH_800 0x1f
85		−
86		−#define CSKY_ARCH_MAC (1 << 15)
87		−#define CSKY_ARCH_DSP (1 << 14)
88		−#define CSKY_ARCH_FLOAT (1 << 13)
89		−#define CSKY_ARCH_SIMD (1 << 12)
90		−#define CSKY_ARCH_CP (1 << 11)
91		−#define CSKY_ARCH_MP (1 << 10)
92		−#define CSKY_ARCH_CACHE (1 << 9)
93		−#define CSKY_ARCH_JAVA (1 << 8)
94		−#define CSKY_ARCH_APS (1 << 7)
95		−
96		−#define IS_CSKY_V1(a) \
97		− (((a) & CSKY_ABI_MASK) == CSKY_ABI_V1)
98		−#define IS_CSKY_V2(a) \
99		− (((a) & CSKY_ABI_MASK) == CSKY_ABI_V2)
100		−#define IS_CSKY_ARCH_V1(a) \
101		− (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_510 \
102		− \|\| ((a) & CSKY_ARCH_MASK) == CSKY_ARCH_610)
103		−#define IS_CSKY_ARCH_V2(a) \
104		− (!(IS_CSKY_ARCH_V1 (a)))
105		−
106		−#define IS_CSKY_ARCH_510(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_510)
107		−#define IS_CSKY_ARCH_610(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_610)
108		−#define IS_CSKY_ARCH_801(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_801)
109		−#define IS_CSKY_ARCH_802(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_802)
110		−#define IS_CSKY_ARCH_803(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_803)
111		−#define IS_CSKY_ARCH_807(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_807)
112		−#define IS_CSKY_ARCH_810(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_810)
113		−
114		−#define CPU_ARCH_MASK \
115		− (CSKY_ARCH_JAVA \| CSKY_ARCH_FLOAT \| CSKY_ARCH_DSP \| CSKY_ARCH_MASK)
116		−
117		−#ifdef __cplusplus
118		−extern "C" {
119		−#endif
120		−extern int print_insn_csky (bfd_vma memaddr, struct disassemble_info *info);
121		−#ifdef __cplusplus
122		−}
123		−#endif

binutils/include/opcode/d10v.h+1−1

@@ -1,5 +1,5 @@
1	1	/* d10v.h -- Header file for D10V opcode table
2		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
3	3	Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/d30v.h+2−2

@@ -1,5 +1,5 @@
1	1	/* d30v.h -- Header file for D30V opcode table
2		− Copyright (C) 1997-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1997-2018 Free Software Foundation, Inc.
3	3	Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
@@ -33,7 +33,7 @@ struct pd_reg · 27 unmodified lines
33	33	{
34	34	char name; / name to recognize */
35	35	char pname; / name to print for this register */
36		− unsigned int value;
	36	+ int value;
37	37	};
38	38
39	39	extern const struct pd_reg pre_defined_registers[];

binutils/include/opcode/dlx.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Table of opcodes for the DLX microprocess.
2		− Copyright (C) 2002-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2002-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB and GAS.
5	5

binutils/include/opcode/ft32.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Definitions for decoding the ft32 opcode table.
2		− Copyright (C) 2013-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2013-2018 Free Software Foundation, Inc.
3	3	Contributed by FTDI (support@ftdichip.com)
4	4
5	5	This program is free software; you can redistribute it and/or modify

binutils/include/opcode/h8300.h+48−48

@@ -1,5 +1,5 @@
1	1	/* Opcode table for the H8/300
2		− Copyright (C) 1991-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1991-2018 Free Software Foundation, Inc.
3	3	Written by Steve Chamberlain <sac@cygnus.com>.
4	4
5	5	This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
@@ -980,8 +980,8 @@ struct h8_opcode · 974 unmodified lines
980	980	{CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 \| IGNORE, ABS16LIST, OP1, OP2, OP3, B30 \| IGNORE, E}}}, \
981	981	{CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 \| IGNORE, ABS32LIST, OP1, OP2, OP3, B30 \| IGNORE, E}}}
982	982
983		−#define EXPAND_UNOP_EXTENDED_B(CODE, MODEL, NAME, CONST, PREFIX, OP1, OP2, OP3) \
984		− {CODE, MODEL, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \
	983	+#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
	984	+ {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \
985	985	{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 \| RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
986	986	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 \| RDPOSTINC, B31 \| IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
987	987	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 \| RDPOSTDEC, B31 \| IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
@@ -1000,8 +1000,8 @@ struct h8_opcode · 12 unmodified lines
1000	1000	{CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 \| IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
1001	1001	{CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 \| IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
1002	1002
1003		−#define EXPAND_UNOP_EXTENDED_W(CODE, MODEL, NAME, CONST, PREFIX, OP1, OP2, OP3) \
1004		− {CODE, MODEL, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \
	1003	+#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \
	1004	+ {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \
1005	1005	{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 \| RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
1006	1006	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 \| RDPOSTINC, B31 \| IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
1007	1007	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 \| RDPOSTDEC, B31 \| IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \
@@ -1019,8 +1019,8 @@ struct h8_opcode · 11 unmodified lines
1019	1019	{CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 \| IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \
1020	1020	{CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 \| IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}}
1021	1021
1022		−#define EXPAND_UNOP_EXTENDED_L(CODE, MODEL, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
1023		− {CODE, MODEL, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT \| RD32, E}}}, \
	1022	+#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \
	1023	+ {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT \| RD32, E}}}, \
1024	1024	{CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 \| RDIND, B31 \| IGNORE, OP1, OP2, OP3, BIT \| IGNORE, E}}}, \
1025	1025	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 \| RDPOSTINC, B31 \| IGNORE, OP1, OP2, OP3, BIT \| IGNORE, E}}}, \
1026	1026	{CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 \| RDPOSTDEC, B31 \| IGNORE, OP1, OP2, OP3, BIT \| IGNORE, E}}}, \
@@ -1393,10 +1393,10 @@ struct h8_opcode h8_opcodes[] = · 366 unmodified lines
1393	1393
1394	1394	EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd),
1395	1395	EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf),
1396		− EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), AV_H8SX, "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
	1396	+ EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0),
1397	1397	EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5),
1398	1398	EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7),
1399		− EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), AV_H8SX, "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
	1399	+ EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0),
1400	1400
1401	1401	UNOP (O (O_INC, SB), "inc", 0x0, 0xA),
1402	1402
@@ -1698,29 +1698,29 @@ struct h8_opcode h8_opcodes[] = · 295 unmodified lines
1698	1698	{O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 \| B30, E}}},
1699	1699
1700	1700	EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8),
1701		− EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), AV_H8S, "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
	1701	+ EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc),
1702	1702	EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9),
1703		− EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), AV_H8S, "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
	1703	+ EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd),
1704	1704	EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb),
1705		− EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), AV_H8S, "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
	1705	+ EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30),
1706	1706	EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8),
1707		− EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), AV_H8S, "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
	1707	+ EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc),
1708	1708	EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9),
1709		− EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), AV_H8S, "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
	1709	+ EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd),
1710	1710	EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb),
1711		− EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), AV_H8S, "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
	1711	+ EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30),
1712	1712	EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0),
1713		− EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), AV_H8S, "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
	1713	+ EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4),
1714	1714	EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1),
1715		− EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), AV_H8S, "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
	1715	+ EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5),
1716	1716	EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3),
1717		− EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), AV_H8S, "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
	1717	+ EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30),
1718	1718	EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0),
1719		− EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), AV_H8S, "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
	1719	+ EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4),
1720	1720	EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1),
1721		− EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), AV_H8S, "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
	1721	+ EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5),
1722	1722	EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3),
1723		− EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), AV_H8S, "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
	1723	+ EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30),
1724	1724
1725	1725
1726	1726	{O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}},
@@ -1730,70 +1730,70 @@ struct h8_opcode h8_opcodes[] = · 3 unmodified lines
1730	1730	{O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 \| B30, RD32 \| B30, E}}},
1731	1731
1732	1732	EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8),
1733		− EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), AV_H8S, "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
	1733	+ EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc),
1734	1734	EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9),
1735		− EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), AV_H8S, "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
	1735	+ EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd),
1736	1736	EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb),
1737		− EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), AV_H8S, "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
	1737	+ EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30),
1738	1738	EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8),
1739		− EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), AV_H8S, "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
	1739	+ EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc),
1740	1740	EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9),
1741		− EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), AV_H8S, "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
	1741	+ EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd),
1742	1742	EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb),
1743		− EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), AV_H8S, "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
	1743	+ EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30),
1744	1744
1745	1745	EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0),
1746	1746
1747	1747	{O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}},
1748	1748
1749		− EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), AV_H8S, "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
1750		− EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), AV_H8SX, "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
	1749	+ EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4),
	1750	+ EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa),
1751	1751	{O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}},
1752	1752
1753	1753	EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1),
1754	1754
1755	1755	{O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}},
1756	1756
1757		− EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), AV_H8S, "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
1758		− EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), AV_H8SX, "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
1759		− EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), AV_H8SX, "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
	1757	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5),
	1758	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2),
	1759	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6),
1760	1760	{O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}},
1761	1761
1762	1762	EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3),
1763	1763
1764	1764	{O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 \| RD32, E}}},
1765	1765
1766		− EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), AV_H8S, "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30),
1767		− EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), AV_H8SX, "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31),
1768		− EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), AV_H8SX, "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31),
1769		− EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), AV_H8SX, "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
	1766	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30),
	1767	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31),
	1768	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31),
	1769	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31),
1770	1770	{O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x0, 0x3, B30 \| RD32, E}}},
1771	1771
1772	1772	EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0),
1773	1773
1774	1774	{O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}},
1775	1775
1776		− EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), AV_H8S, "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
1777		− EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), AV_H8SX, "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
	1776	+ EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4),
	1777	+ EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa),
1778	1778	{O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}},
1779	1779
1780	1780	EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1),
1781	1781
1782	1782	{O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}},
1783	1783
1784		− EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), AV_H8S, "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
1785		− EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), AV_H8SX, "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
1786		− EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), AV_H8SX, "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
	1784	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5),
	1785	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2),
	1786	+ EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6),
1787	1787	{O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}},
1788	1788
1789	1789	EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3),
1790	1790
1791	1791	{O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 \| RD32, E}}},
1792	1792
1793		− EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), AV_H8S, "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30),
1794		− EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), AV_H8SX, "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31),
1795		− EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), AV_H8SX, "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31),
1796		− EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), AV_H8SX, "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
	1793	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30),
	1794	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31),
	1795	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31),
	1796	+ EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31),
1797	1797	{O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 \| IMM5, DATA, 0x1, 0x1, 0x3, B30 \| RD32, E}}},
1798	1798
1799	1799	{O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}},
@@ -1864,7 +1864,7 @@ struct h8_opcode h8_opcodes[] = · 64 unmodified lines
1864	1864	{O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 \| RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}},
1865	1865
1866	1866	{O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}},
1867		− {O (O_TAS, SB), AV_H8S, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 \| RSIND, 0xc, E}}},
	1867	+ {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 \| RSIND, 0xc, E}}},
1868	1868
1869	1869	{O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}},
1870	1870	EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0),
@@ -1882,8 +1882,8 @@ struct h8_opcode h8_opcodes[] = · 11 unmodified lines
1882	1882	{O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 \| RSPOSTINC, B30 \| RDPOSTINC, E}}},
1883	1883	{O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}},
1884	1884	{O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}},
1885		− {O (O_LDM, SL), AV_H8S, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 \| RD32, E}}},
1886		− {O (O_STM, SL), AV_H8S, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 \| RS32, E}}},
	1885	+ {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 \| RD32, E}}},
	1886	+ {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 \| RS32, E}}},
1887	1887	{0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}}
1888	1888	};
1889	1889	#else

binutils/include/opcode/hppa.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Table of opcodes for the PA-RISC.
2		− Copyright (C) 1990-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1990-2018 Free Software Foundation, Inc.
3	3
4	4	Contributed by the Center for Software Science at the
5	5	University of Utah (pa-gdb-bugs@cs.utah.edu).

binutils/include/opcode/i386.h+1−2

@@ -1,5 +1,5 @@
1	1	/* opcode/i386.h -- Intel 80386 opcode macros
2		− Copyright (C) 1989-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5	5
@@ -46,7 +46,6 @@ · 40 unmodified lines
46	46
47	47	#define MOV_AX_DISP32 0xa0
48	48	#define POP_SEG_SHORT 0x07
49		−#define POP_SEG386_SHORT 0xfa1
50	49	#define JUMP_PC_RELATIVE 0xeb
51	50	#define INT_OPCODE 0xcd
52	51	#define INT3_OPCODE 0xcc

binutils/include/opcode/ia64.h+1−1

@@ -1,5 +1,5 @@
1	1	/* ia64.h -- Header file for ia64 opcode table
2		− Copyright (C) 1998-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1998-2018 Free Software Foundation, Inc.
3	3	Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4	4
5	5	This file is part of BFD, the Binary File Descriptor library.

binutils/include/opcode/m68hc11.h+1−1

@@ -1,5 +1,5 @@
1	1	/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
2		− Copyright (C) 1999-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1999-2018 Free Software Foundation, Inc.
3	3	Written by Stephane Carrez (stcarrez@nerim.fr)
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/m68k.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Opcode table header for m680[01234]0/m6888[12]/m68851.
2		− Copyright (C) 1989-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB, GAS, and the GNU binutils.
5	5

binutils/include/opcode/metag.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Imagination Technologies Meta opcode table.
2		− Copyright (C) 2013-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2013-2018 Free Software Foundation, Inc.
3	3	Contributed by Imagination Technologies Ltd.
4	4
5	5	This file is part of GDB and GAS.

binutils/include/opcode/mips.h+10−24

@@ -1,5 +1,5 @@
1	1	/* mips.h. Mips opcode list for GDB, the GNU debugger.
2		− Copyright (C) 1993-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1993-2018 Free Software Foundation, Inc.
3	3	Contributed by Ralph Campbell and OSF
4	4	Commented and modified by Ian Lance Taylor, Cygnus Support
5	5
@@ -56,8 +56,8 @@ extern "C" { · 50 unmodified lines
56	56	code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
57	57	only use ten bits). An optional two-operand form of break/sdbbp
58	58	allows the lower ten bits to be set too, and MIPS32 and later
59		− architectures allow 20 bits to be set with a single operand for
60		− the sdbbp instruction (using CODE20).
	59	+ architectures allow 20 bits to be set with a signal operand
	60	+ (using CODE20).
61	61
62	62	The syscall instruction uses CODE20.
63	63
@@ -928,7 +928,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) · 864 unmodified lines
928	928	"+S" Length-minus-one field of cins/exts. Requires msb position
929	929	of the field to be <= 63.
930	930
931		− Loongson-ext ASE:
	931	+ Loongson-3A:
932	932	"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
933	933	"+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
934	934	"+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
@@ -1256,6 +1256,8 @@ static const unsigned int mips_isa_table[] = { · 321 unmodified lines
1256	1256	#define INSN_LOONGSON_2E 0x40000000
1257	1257	/* ST Microelectronics Loongson 2F. */
1258	1258	#define INSN_LOONGSON_2F 0x80000000
	1259	+/* Loongson 3A. */
	1260	+#define INSN_LOONGSON_3A 0x00000400
1259	1261	/* RMI Xlr instruction */
1260	1262	#define INSN_XLR 0x00000020
1261	1263	/* Imagination interAptiv MR2. */
@@ -1300,17 +1302,6 @@ static const unsigned int mips_isa_table[] = { · 38 unmodified lines
1300	1302	#define ASE_CRC64 0x00080000
1301	1303	/* Global INValidate Extension. */
1302	1304	#define ASE_GINV 0x00100000
1303		−/* Loongson MultiMedia extensions Instructions (MMI). */
1304		−#define ASE_LOONGSON_MMI 0x00200000
1305		−/* Loongson Content Address Memory (CAM). */
1306		−#define ASE_LOONGSON_CAM 0x00400000
1307		−/* Loongson EXTensions (EXT) instructions. */
1308		−#define ASE_LOONGSON_EXT 0x00800000
1309		−/* Loongson EXTensions R2 (EXT2) instructions. */
1310		−#define ASE_LOONGSON_EXT2 0x01000000
1311		−/* The Enhanced VA Scheme (EVA) extension has instructions which are
1312		− only valid for the R6 ISA. */
1313		−#define ASE_EVA_R6 0x02000000
1314	1305
1315	1306	/* MIPS ISA defines, use instead of hardcoding ISA level. */
1316	1307
@@ -1375,9 +1366,7 @@ static const unsigned int mips_isa_table[] = { · 58 unmodified lines
1375	1366	#define CPU_SB1 12310201 /* octal 'SB', 01. */
1376	1367	#define CPU_LOONGSON_2E 3001
1377	1368	#define CPU_LOONGSON_2F 3002
1378		−#define CPU_GS464 3003
1379		−#define CPU_GS464E 3004
1380		−#define CPU_GS264E 3005
	1369	+#define CPU_LOONGSON_3A 3003
1381	1370	#define CPU_OCTEON 6501
1382	1371	#define CPU_OCTEONP 6601
1383	1372	#define CPU_OCTEON2 6502
@@ -1436,6 +1425,9 @@ cpu_is_member (int cpu, unsigned int mask) · 52 unmodified lines
1436	1425	case CPU_LOONGSON_2F:
1437	1426	return (mask & INSN_LOONGSON_2F) != 0;
1438	1427
	1428	+ case CPU_LOONGSON_3A:
	1429	+ return (mask & INSN_LOONGSON_3A) != 0;
	1430	+
1439	1431	case CPU_OCTEON:
1440	1432	return (mask & INSN_OCTEON) != 0;
1441	1433
@@ -1631,10 +1623,7 @@ enum · 189 unmodified lines
1631	1623	M_LI_SS,
1632	1624	M_LL_AB,
1633	1625	M_LLD_AB,
1634		− M_LLDP_AB,
1635	1626	M_LLE_AB,
1636		− M_LLWP_AB,
1637		− M_LLWPE_AB,
1638	1627	M_LQ_AB,
1639	1628	M_LW_AB,
1640	1629	M_LWE_AB,
@@ -1685,10 +1674,7 @@ enum · 44 unmodified lines
1685	1674	M_SAAD_AB,
1686	1675	M_SC_AB,
1687	1676	M_SCD_AB,
1688		− M_SCDP_AB,
1689	1677	M_SCE_AB,
1690		− M_SCWP_AB,
1691		− M_SCWPE_AB,
1692	1678	M_SD_AB,
1693	1679	M_SDC1_AB,
1694	1680	M_SDC2_AB,

binutils/include/opcode/mmix.h+9−9

@@ -1,5 +1,5 @@
1	1	/* mmix.h -- Header file for MMIX opcode table
2		− Copyright (C) 2001-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2001-2018 Free Software Foundation, Inc.
3	3	Written by Hans-Peter Nilsson (hp@bitrange.com)
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
@@ -173,14 +173,14 @@ extern const struct mmix_spec_reg mmix_spec_regs[]; · 167 unmodified lines
173	173	#define COND_INV_BIT 0x8
174	174	#define PRED_INV_BIT 0x10
175	175
176		−#define PUSHGO_INSN_BYTE 0xbeu
177		−#define GO_INSN_BYTE 0x9eu
178		−#define SETL_INSN_BYTE 0xe3u
179		−#define INCML_INSN_BYTE 0xe6u
180		−#define INCMH_INSN_BYTE 0xe5u
181		−#define INCH_INSN_BYTE 0xe4u
182		−#define SWYM_INSN_BYTE 0xfdu
183		−#define JMP_INSN_BYTE 0xf0u
	176	+#define PUSHGO_INSN_BYTE 0xbe
	177	+#define GO_INSN_BYTE 0x9e
	178	+#define SETL_INSN_BYTE 0xe3
	179	+#define INCML_INSN_BYTE 0xe6
	180	+#define INCMH_INSN_BYTE 0xe5
	181	+#define INCH_INSN_BYTE 0xe4
	182	+#define SWYM_INSN_BYTE 0xfd
	183	+#define JMP_INSN_BYTE 0xf0
184	184
185	185	/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable)
186	186	global registers. */

binutils/include/opcode/mn10200.h+1−1

@@ -1,5 +1,5 @@
1	1	/* mn10200.h -- Header file for Matsushita 10200 opcode table
2		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
3	3	Written by Jeff Law, Cygnus Support
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/mn10300.h+1−1

@@ -1,5 +1,5 @@
1	1	/* mn10300.h -- Header file for Matsushita 10300 opcode table
2		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
3	3	Written by Jeff Law, Cygnus Support
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/moxie.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Definitions for decoding the moxie opcode table.
2		− Copyright (C) 2009-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2009-2018 Free Software Foundation, Inc.
3	3	Contributed by Anthony Green (green@moxielogic.com).
4	4
5	5	This program is free software; you can redistribute it and/or modify

binutils/include/opcode/msp430-decode.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Opcode decoder for the TI MSP430
2		− Copyright (C) 2012-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2012-2018 Free Software Foundation, Inc.
3	3	Written by DJ Delorie <dj@redhat.com>
4	4
5	5	This file is part of GDB, the GNU Debugger.

binutils/include/opcode/msp430.h+1−16

@@ -1,6 +1,6 @@
1	1	/* Opcode table for the TI MSP430 microcontrollers
2	2
3		− Copyright (C) 2002-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2002-2018 Free Software Foundation, Inc.
4	4	Contributed by Dmitry Diky <diwil@mail.ru>
5	5
6	6	This program is free software; you can redistribute it and/or modify
@@ -21,18 +21,6 @@ · 14 unmodified lines
21	21	#ifndef __MSP430_H_
22	22	#define __MSP430_H_
23	23
24		−enum msp430_expp_e
25		−{
26		− MSP_EXPP_ALL = 0, /* Use full the value of the expression - default. */
27		− MSP_EXPP_LO, /* Extract least significant word from expression. */
28		− MSP_EXPP_HI, /* Extract 2nd word from expression. */
29		− MSP_EXPP_LLO, /* Extract least significant word from an
30		− immediate value. */
31		− MSP_EXPP_LHI, /* Extract 2nd word from an immediate value. */
32		− MSP_EXPP_HLO, /* Extract 3rd word from an immediate value. */
33		− MSP_EXPP_HHI, /* Extract 4th word from an immediate value. */
34		−};
35		−
36	24	struct msp430_operand_s
37	25	{
38	26	int ol; /* Operand length words. */
@@ -40,9 +28,6 @@ struct msp430_operand_s · 1 unmodified line
40	28	int reg; /* Register. */
41	29	int mode; /* Operand mode. */
42	30	int vshift; /* Number of bytes to shift operand down. */
43		− enum msp430_expp_e expp; /* For when the operand is a constant
44		− expression, the part of the expression to
45		− extract. */
46	31	#define OP_REG 0
47	32	#define OP_EXP 1
48	33	#ifndef DASM_SECTION

binutils/include/opcode/nds32.h+27−186

@@ -1,5 +1,5 @@
1	1	/* nds32.h -- Header file for nds32 opcode table
2		− Copyright (C) 2012-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2012-2018 Free Software Foundation, Inc.
3	3	Contributed by Andes Technology Corporation.
4	4
5	5	This program is free software; you can redistribute it and/or modify
@@ -21,20 +21,19 @@ · 15 unmodified lines
21	21	#define OPCODE_NDS32_H
22	22
23	23	/* Registers. */
24		−#define REG_R0 (0)
25		−#define REG_R5 (5)
26		−#define REG_R8 (8)
27		−#define REG_R10 (10)
28		−#define REG_R12 (12)
29		−#define REG_R15 (15)
30		−#define REG_R16 (16)
31		−#define REG_R20 (20)
32		−#define REG_TA (15)
33		−#define REG_TP (25)
34		−#define REG_FP (28)
35		−#define REG_GP (29)
36		−#define REG_LP (30)
37		−#define REG_SP (31)
	24	+#define REG_R5 5
	25	+#define REG_R8 8
	26	+#define REG_R10 10
	27	+#define REG_R12 12
	28	+#define REG_R15 15
	29	+#define REG_R16 16
	30	+#define REG_R20 20
	31	+#define REG_TA 15
	32	+#define REG_TP 27
	33	+#define REG_FP 28
	34	+#define REG_GP 29
	35	+#define REG_LP 30
	36	+#define REG_SP 31
38	37
39	38	/* Macros for extracting fields or making an instruction. */
40	39	static const int nds32_r45map[] ATTRIBUTE_UNUSED =
@@ -51,12 +50,11 @@ static const int nds32_r54map[] ATTRIBUTE_UNUSED = · 10 unmodified lines
51	50	-1, -1, -1, -1, -1, -1, -1, -1
52	51	};
53	52
54		−#define N32_BIT(n) (1u << (n))
	53	+#define N32_BIT(n) (1 << (n))
55	54	#define __MASK(n) (N32_BIT (n) - 1)
56	55	#define __MF(v, off, bs) (((v) & __MASK (bs)) << (off))
57	56	#define __GF(v, off, bs) (((v) >> off) & __MASK (bs))
58		−#define __SEXT(v, bs) \
59		− ((((v) & __MASK ((bs))) ^ N32_BIT ((bs) - 1)) - N32_BIT ((bs) - 1))
	57	+#define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
60	58
61	59	/* Make nds32 instructions. */
62	60
@@ -148,10 +146,9 @@ static const int nds32_r54map[] ATTRIBUTE_UNUSED = · 85 unmodified lines
148	146	#define N32_RD5(insn) (((insn) >> 5) & 0x1f)
149	147	#define N32_SH5(insn) (((insn) >> 5) & 0x1f)
150	148	#define N32_SUB5(insn) (((insn) >> 0) & 0x1f)
151		−#define N32_SUB6(insn) (((insn) >> 0) & 0x3f)
152	149	#define N32_SWID(insn) (((insn) >> 5) & 0x3ff)
153	150	#define N32_IMMU(insn, bs) ((insn) & __MASK (bs))
154		−#define N32_IMMS(insn, bs) ((signed) __SEXT ((insn), (bs)))
	151	+#define N32_IMMS(insn, bs) ((signed) __SEXT (((insn) & __MASK (bs)), bs))
155	152	#define N32_IMM5U(insn) N32_IMMU (insn, 5)
156	153	#define N32_IMM12S(insn) N32_IMMS (insn, 12)
157	154	#define N32_IMM14S(insn) N32_IMMS (insn, 14)
@@ -278,7 +275,7 @@ enum n32_opcodes · 120 unmodified lines
278	275	N32_BR1_BNE = 1,
279	276
280	277	/* bit[16:19] */
281		− N32_BR2_SOP0 = 0,
	278	+ N32_BR2_IFCALL = 0,
282	279	N32_BR2_BEQZ = 2,
283	280	N32_BR2_BNEZ = 3,
284	281	N32_BR2_BGEZ = 4,
@@ -368,8 +365,7 @@ enum n32_opcodes · 83 unmodified lines
368	365	N32_ALU2_FFZMISM,
369	366	N32_ALU2_KADD = 0x18,
370	367	N32_ALU2_KSUB,
371		− N32_ALU2_KSLRAW,
372		− N32_ALU2_KSLRAWu,
	368	+ N32_ALU2_KSLRA,
373	369	N32_ALU2_MFUSR = 0x20,
374	370	N32_ALU2_MTUSR,
375	371	N32_ALU2_0x22,
@@ -385,173 +381,20 @@ enum n32_opcodes · 9 unmodified lines
385	381	N32_ALU2_MSUB64,
386	382	N32_ALU2_DIVS,
387	383	N32_ALU2_DIV,
388		− N32_ALU2_ADD64 = 0x30,
	384	+ N32_ALU2_0x30 = 0x30,
389	385	N32_ALU2_MULT32,
390		− N32_ALU2_SMAL,
	386	+ N32_ALU2_0x32,
391	387	N32_ALU2_MADD32,
392		− N32_ALU2_SUB64,
	388	+ N32_ALU2_0x34,
393	389	N32_ALU2_MSUB32,
394		− N32_ALU2_0x36,
395		− N32_ALU2_0x37,
396		− N32_ALU2_RADD64 = 0x38,
397		− N32_ALU2_URADD64,
398		− N32_ALU2_KADD64,
399		− N32_ALU2_UKADD64,
400		− N32_ALU2_RSUB64,
401		− N32_ALU2_URSUB64,
402		− N32_ALU2_KSUB64,
403		− N32_ALU2_UKSUB64,
404		−
405		− /* bit[0:5], where bit[6:9] = 0001 */
406		− N32_ALU2_SMAR64 = 0x0,
407		− N32_ALU2_UMAR64,
408		− N32_ALU2_SMSR64,
409		− N32_ALU2_UMSR64,
410		− N32_ALU2_KMAR64,
411		− N32_ALU2_UKMAR64,
412		− N32_ALU2_KMSR64,
413		− N32_ALU2_UKMSR64,
414		− N32_ALU2_SMALDA = 0x8,
415		− N32_ALU2_SMSLDA,
416		− N32_ALU2_SMALDS,
417		− N32_ALU2_SMALBB,
	390	+
	391	+ /* bit[0:5], where bit[6:9] != 0 */
418	392	N32_ALU2_FFBI = 0xe,
419	393	N32_ALU2_FLMISM = 0xf,
420		− N32_ALU2_SMALXDA = 0x10,
421		− N32_ALU2_SMSLXDA,
422		− N32_ALU2_SMALXDS,
423		− N32_ALU2_SMALBT,
424		− N32_ALU2_SMALDRS = 0x1a,
425		− N32_ALU2_SMALTT,
426		− N32_ALU2_RDOV = 0x20,
427		− N32_ALU2_CLROV,
428	394	N32_ALU2_MULSR64 = 0x28,
429	395	N32_ALU2_MULR64 = 0x29,
430		− N32_ALU2_SMDS = 0x30,
431		− N32_ALU2_SMXDS,
432		− N32_ALU2_SMDRS,
433		− N32_ALU2_MADDR32,
434		− N32_ALU2_KMADRS,
435		− N32_ALU2_MSUBR32,
436		− N32_ALU2_KMADS,
437		− N32_ALU2_KMAXDS,
438		−
439		− /* bit[0:5], where bit[6:9] = 0010 */
440		− N32_ALU2_KADD16 = 0x0,
441		− N32_ALU2_KSUB16,
442		− N32_ALU2_KCRAS16,
443		− N32_ALU2_KCRSA16,
444		− N32_ALU2_KADD8,
445		− N32_ALU2_KSUB8,
446		− N32_ALU2_WEXT,
447		− N32_ALU2_WEXTI,
448		− N32_ALU2_UKADD16 = 0x8,
449		− N32_ALU2_UKSUB16,
450		− N32_ALU2_UKCRAS16,
451		− N32_ALU2_UKCRSA16,
452		− N32_ALU2_UKADD8,
453		− N32_ALU2_UKSUB8,
454		− N32_ALU2_ONEOP = 0xf,
455		− N32_ALU2_SMBB = 0x10,
456		− N32_ALU2_SMBT,
457		− N32_ALU2_SMTT,
458		− N32_ALU2_KMABB = 0x15,
459		− N32_ALU2_KMABT,
460		− N32_ALU2_KMATT,
461		− N32_ALU2_KMDA = 0x18,
462		− N32_ALU2_KMXDA,
463		− N32_ALU2_KMADA,
464		− N32_ALU2_KMAXDA,
465		− N32_ALU2_KMSDA,
466		− N32_ALU2_KMSXDA,
467		− N32_ALU2_RADD16 = 0x20,
468		− N32_ALU2_RSUB16,
469		− N32_ALU2_RCRAS16,
470		− N32_ALU2_RCRSA16,
471		− N32_ALU2_RADD8,
472		− N32_ALU2_RSUB8,
473		− N32_ALU2_RADDW,
474		− N32_ALU2_RSUBW,
475		− N32_ALU2_URADD16 = 0x28,
476		− N32_ALU2_URSUB16,
477		− N32_ALU2_URCRAS16,
478		− N32_ALU2_URCRSA16,
479		− N32_ALU2_URADD8,
480		− N32_ALU2_URSUB8,
481		− N32_ALU2_URADDW,
482		− N32_ALU2_URSUBW,
483		− N32_ALU2_ADD16 = 0x30,
484		− N32_ALU2_SUB16,
485		− N32_ALU2_CRAS16,
486		− N32_ALU2_CRSA16,
487		− N32_ALU2_ADD8,
488		− N32_ALU2_SUB8,
489		− N32_ALU2_BITREV,
490		− N32_ALU2_BITREVI,
491		− N32_ALU2_SMMUL = 0x38,
492		− N32_ALU2_SMMULu,
493		− N32_ALU2_KMMAC,
494		− N32_ALU2_KMMACu,
495		− N32_ALU2_KMMSB,
496		− N32_ALU2_KMMSBu,
497		− N32_ALU2_KWMMUL,
498		− N32_ALU2_KWMMULu,
499		−
500		− /* bit[0:5], where bit[6:9] = 0011 */
501		− N32_ALU2_SMMWB = 0x0,
502		− N32_ALU2_SMMWBu,
503		− N32_ALU2_SMMWT,
504		− N32_ALU2_SMMWTu,
505		− N32_ALU2_KMMAWB,
506		− N32_ALU2_KMMAWBu,
507		− N32_ALU2_KMMAWT,
508		− N32_ALU2_KMMAWTu,
509		− N32_ALU2_PKTT16 = 0x8,
510		− N32_ALU2_PKTB16,
511		− N32_ALU2_PKBT16,
512		− N32_ALU2_PKBB16,
513		− N32_ALU2_0x10 = 0x10,
514		− N32_ALU2_SCLIP16,
515		− N32_ALU2_0x12,
516		− N32_ALU2_SMAX16,
517		− N32_ALU2_SMAX8 = 0x17,
518		− N32_ALU2_0x18 = 0x18,
519		− N32_ALU2_UCLIP16,
520		− N32_ALU2_0x1a,
521		− N32_ALU2_UMAX16,
522		− N32_ALU2_UMAX8 = 0x1f,
523		− N32_ALU2_SRA16 = 0x20,
524		− N32_ALU2_SRA16u,
525		− N32_ALU2_SRL16,
526		− N32_ALU2_SRL16u,
527		− N32_ALU2_SLL16,
528		− N32_ALU2_KSLRA16,
529		− N32_ALU2_KSLRA16u,
530		− N32_ALU2_SRAu,
531		− N32_ALU2_SRAI16 = 0x28,
532		− N32_ALU2_SRAI16u,
533		− N32_ALU2_SRLI16,
534		− N32_ALU2_SRLI16u,
535		− N32_ALU2_SLLI16,
536		− N32_ALU2_KSLLI16,
537		− N32_ALU2_KSLLI,
538		− N32_ALU2_SRAIu,
539		− N32_ALU2_CMPEQ16 = 0x30,
540		− N32_ALU2_SCMPLT16,
541		− N32_ALU2_SCMPLE16,
542		− N32_ALU2_SMIN16,
543		− N32_ALU2_CMPEQ8,
544		− N32_ALU2_SCMPLT8,
545		− N32_ALU2_SCMPLE8,
546		− N32_ALU2_SMIN8,
547		− N32_ALU2_0x38,
548		− N32_ALU2_UCMPLT16 = 0x39,
549		− N32_ALU2_UCMPLE16,
550		− N32_ALU2_UMIN16,
551		− N32_ALU2_0x3c,
552		− N32_ALU2_UCMPLT8,
553		− N32_ALU2_UCMPLE8,
554		− N32_ALU2_UMIN8,
	396	+ N32_ALU2_MADDR32 = 0x33,
	397	+ N32_ALU2_MSUBR32 = 0x35,
555	398
556	399	/* bit[0:5] */
557	400	N32_MEM_LB = 0,
@@ -616,8 +459,7 @@ enum n32_opcodes · 58 unmodified lines
616	459	N32_MISC_MSYNC,
617	460	N32_MISC_ISYNC,
618	461	N32_MISC_TLBOP,
619		− N32_MISC_SPECL,
620		− N32_MISC_BPICK = 0x10,
	462	+ N32_MISC_0xf,
621	463
622	464	/* bit[0:4] */
623	465	N32_SIMD_PBSAD = 0,
@@ -862,7 +704,6 @@ enum n16_opcodes · 238 unmodified lines
862	704	#define INSN_ANDI 0x54000000
863	705	#define INSN_LDI 0x06000000
864	706	#define INSN_SDI 0x16000000
865		−#define INSN_LW 0x38000002
866	707	#define INSN_LWI 0x04000000
867	708	#define INSN_LWSI 0x24000000
868	709	#define INSN_LWIP 0x0c000000

binutils/include/opcode/nfp.h+1−1

@@ -1,5 +1,5 @@
1	1	/* nfp.h. NFP opcode list.
2		− Copyright (C) 2017-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2017-2018 Free Software Foundation, Inc.
3	3	Contributed by Francois H. Theron <francois.theron@netronome.com>
4	4
5	5	This file is part of the GNU opcodes library.

binutils/include/opcode/nios2.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Nios II opcode list for GAS, the GNU assembler.
2		− Copyright (C) 2012-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2012-2018 Free Software Foundation, Inc.
3	3	Contributed by Nigel Gray (ngray@altera.com).
4	4	Contributed by Mentor Graphics, Inc.
5	5

binutils/include/opcode/nios2r1.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Nios II R1 opcode list for GAS, the GNU assembler.
2		− Copyright (C) 2013-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2013-2018 Free Software Foundation, Inc.
3	3	Contributed by Mentor Graphics, Inc.
4	4
5	5	This file is part of the GNU opcodes library.

binutils/include/opcode/nios2r2.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Nios II R2 opcode list for GAS, the GNU assembler.
2		− Copyright (C) 2013-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2013-2018 Free Software Foundation, Inc.
3	3	Contributed by Mentor Graphics, Inc.
4	4
5	5	This file is part of the GNU opcodes library.

binutils/include/opcode/np1.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Print GOULD NPL instructions for GDB, the GNU debugger.
2		− Copyright (C) 1986-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1986-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB.
5	5

binutils/include/opcode/ns32k.h+1−1

@@ -1,5 +1,5 @@
1	1	/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
2		− Copyright (C) 1987-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1987-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GAS, the GNU Assembler.
5	5

binutils/include/opcode/pdp11.h+1−1

@@ -1,5 +1,5 @@
1	1	/* PDP-11 opcde list.
2		− Copyright (C) 2001-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2001-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB and GAS.
5	5

binutils/include/opcode/pj.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Definitions for decoding the picoJava opcode table.
2		− Copyright (C) 1999-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1999-2018 Free Software Foundation, Inc.
3	3	Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
4	4
5	5	This program is free software; you can redistribute it and/or modify

binutils/include/opcode/pn.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
2		− Copyright (C) 1986-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1986-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB.
5	5

binutils/include/opcode/ppc.h+42−67

@@ -1,5 +1,5 @@
1	1	/* ppc.h -- Header file for PowerPC opcode table
2		− Copyright (C) 1994-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1994-2018 Free Software Foundation, Inc.
3	3	Written by Ian Lance Taylor, Cygnus Support
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
@@ -30,6 +30,14 @@ extern "C" { · 24 unmodified lines
30	30
31	31	typedef uint64_t ppc_cpu_t;
32	32
	33	+#if BFD_HOST_64BIT_LONG
	34	+# define PPC_INT_FMT "l"
	35	+#elif defined (__MSVCRT__)
	36	+# define PPC_INT_FMT "I64"
	37	+#else
	38	+# define PPC_INT_FMT "ll"
	39	+#endif
	40	+
33	41	/* The opcode table is an array of struct powerpc_opcode. */
34	42
35	43	struct powerpc_opcode
@@ -68,8 +76,6 @@ struct powerpc_opcode · 32 unmodified lines
68	76	instructions. */
69	77	extern const struct powerpc_opcode powerpc_opcodes[];
70	78	extern const unsigned int powerpc_num_opcodes;
71		−extern const struct powerpc_opcode prefix_opcodes[];
72		−extern const unsigned int prefix_num_opcodes;
73	79	extern const struct powerpc_opcode vle_opcodes[];
74	80	extern const unsigned int vle_num_opcodes;
75	81	extern const struct powerpc_opcode spe2_opcodes[];
@@ -198,7 +204,7 @@ extern const unsigned int spe2_num_opcodes; · 122 unmodified lines
198	204	/* Opcode is only supported by Power8 architecture. */
199	205	#define PPC_OPCODE_POWER8 0x1000000000ull
200	206
201		−/* Opcode is supported by ppc750cl/Gekko/Broadway. */
	207	+/* Opcode is supported by ppc750cl. */
202	208	#define PPC_OPCODE_750 0x2000000000ull
203	209
204	210	/* Opcode is supported by ppc7450. */
@@ -228,9 +234,6 @@ extern const unsigned int spe2_num_opcodes; · 23 unmodified lines
228	234	/* Opcode is supported by EFS2. */
229	235	#define PPC_OPCODE_EFS2 0x200000000000ull
230	236
231		−/* Opcode is only supported by power10 architecture. */
232		−#define PPC_OPCODE_POWER10 0x400000000000ull
233		−
234	237	/* A macro to extract the major opcode from an instruction. */
235	238	#define PPC_OP(i) (((i) >> 26) & 0x3f)
236	239
@@ -248,19 +251,6 @@ extern const unsigned int spe2_num_opcodes; · 11 unmodified lines
248	251
249	252	/* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
250	253	#define SPE2_XOP_TO_SEG(i) ((i) >> 7)
251		−
252		−/* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
253		−#define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
254		−
255		−/* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
256		−#define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
257		−
258		−/* A macro to determine whether insn I is an 8-byte prefix instruction. */
259		−#define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
260		−
261		−/* A macro used to hash 8-byte PREFIX instructions. */
262		−#define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
263		−
264	254
265	255	/* The operands table is an array of struct powerpc_operand. */
266	256
@@ -290,10 +280,11 @@ struct powerpc_operand · 23 unmodified lines
290	280
291	281	If this field is not NULL, then simply call it with the
292	282	instruction and the operand value. It will return the new value
293		− of the instruction. If the operand value is illegal, *ERRMSG
294		− will be set to a warning string (the operand will be inserted in
295		− any case). If the operand value is legal, *ERRMSG will be
296		− unchanged (most operands can accept any value). */
	283	+ of the instruction. If the ERRMSG argument is not NULL, then if
	284	+ the operand value is illegal, *ERRMSG will be set to a warning
	285	+ string (the operand will be inserted in any case). If the
	286	+ operand value is legal, *ERRMSG will be unchanged (most operands
	287	+ can accept any value). */
297	288	uint64_t (*insert)
298	289	(uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
299	290
@@ -311,18 +302,11 @@ struct powerpc_operand · 11 unmodified lines
311	302	is the result).
312	303
313	304	If this field is not NULL, then simply call it with the
314		− instruction value. It will return the value of the operand.
315		− *INVALID will be set to one by the extraction function if this
316		− operand type can not be extracted from this operand (i.e., the
317		− instruction does not match). If the operand is valid, *INVALID
318		− will not be changed. *INVALID will always be non-negative when
319		− used to extract a field from an instruction.
320		−
321		− The extraction function is also called by both the assembler and
322		− disassembler if an operand is optional, in which case the
323		− function should return the default value of the operand.
324		− *INVALID is negative in this case, and is the negative count of
325		− omitted optional operands up to and including this operand. */
	305	+ instruction value. It will return the value of the operand. If
	306	+ the INVALID argument is not NULL, *INVALID will be set to
	307	+ non-zero if this operand type can not actually be extracted from
	308	+ this operand (i.e., the instruction does not match). If the
	309	+ operand is valid, INVALID will not be changed. /
326	310	int64_t (extract) (uint64_t instruction, ppc_cpu_t dialect, int invalid);
327	311
328	312	/* One bit syntax flags. */
@@ -362,9 +346,6 @@ extern const unsigned int num_powerpc_operands; · 33 unmodified lines
362	346	prints these with a leading 'vs'. */
363	347	#define PPC_OPERAND_VSR (0x10)
364	348
365		−/* This operand names a VSX accumulator. */
366		−#define PPC_OPERAND_ACC (0x20)
367		−
368	349	/* This operand may use the symbolic names for the CR fields (even
369	350	without -mregnames), which are
370	351	lt 0 gt 1 eq 2 so 3 un 3
@@ -372,60 +353,57 @@ extern const unsigned int num_powerpc_operands; · 1 unmodified line
372	353	cr4 4 cr5 5 cr6 6 cr7 7
373	354	These may be combined arithmetically, as in cr2*4+gt. These are
374	355	only supported on the PowerPC, not the POWER. */
375		−#define PPC_OPERAND_CR_BIT (0x40)
	356	+#define PPC_OPERAND_CR_BIT (0x20)
376	357
377	358	/* This is a CR FIELD that does not use symbolic names (unless
378		− -mregnames is in effect). If both PPC_OPERAND_CR_BIT and
379		− PPC_OPERAND_CR_REG are set then treat the field as per
380		− PPC_OPERAND_CR_BIT for assembly, but as if neither of these
381		− bits are set for disassembly. */
382		−#define PPC_OPERAND_CR_REG (0x80)
	359	+ -mregnames is in effect). */
	360	+#define PPC_OPERAND_CR_REG (0x40)
383	361
384	362	/* This operand names a special purpose register. */
385		−#define PPC_OPERAND_SPR (0x100)
	363	+#define PPC_OPERAND_SPR (0x80)
386	364
387	365	/* This operand names a paired-single graphics quantization register. */
388		−#define PPC_OPERAND_GQR (0x200)
	366	+#define PPC_OPERAND_GQR (0x100)
389	367
390	368	/* This operand is a relative branch displacement. The disassembler
391	369	prints these symbolically if possible. */
392		−#define PPC_OPERAND_RELATIVE (0x400)
	370	+#define PPC_OPERAND_RELATIVE (0x200)
393	371
394	372	/* This operand is an absolute branch address. The disassembler
395	373	prints these symbolically if possible. */
396		−#define PPC_OPERAND_ABSOLUTE (0x800)
	374	+#define PPC_OPERAND_ABSOLUTE (0x400)
397	375
398	376	/* This operand takes signed values. */
399		−#define PPC_OPERAND_SIGNED (0x1000)
	377	+#define PPC_OPERAND_SIGNED (0x800)
400	378
401	379	/* This operand takes signed values, but also accepts a full positive
402	380	range of values when running in 32 bit mode. That is, if bits is
403	381	16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
404	382	this flag is ignored. */
405		−#define PPC_OPERAND_SIGNOPT (0x2000)
	383	+#define PPC_OPERAND_SIGNOPT (0x1000)
406	384
407	385	/* The next operand should be wrapped in parentheses rather than
408	386	separated from this one by a comma. This is used for the load and
409	387	store instructions which want their operands to look like
410	388	reg,displacement(reg)
411	389	*/
412		−#define PPC_OPERAND_PARENS (0x4000)
	390	+#define PPC_OPERAND_PARENS (0x2000)
413	391
414	392	/* This operand is for the DS field in a DS form instruction. */
415		−#define PPC_OPERAND_DS (0x8000)
	393	+#define PPC_OPERAND_DS (0x4000)
416	394
417	395	/* This operand is for the DQ field in a DQ form instruction. */
418		−#define PPC_OPERAND_DQ (0x10000)
	396	+#define PPC_OPERAND_DQ (0x8000)
419	397
420	398	/* This operand should be regarded as a negative number for the
421	399	purposes of overflow checking (i.e., the normal most negative
422	400	number is disallowed and one more than the normal most positive
423	401	number is allowed). This flag will only be set for a signed
424	402	operand. */
425		−#define PPC_OPERAND_NEGATIVE (0x20000)
	403	+#define PPC_OPERAND_NEGATIVE (0x10000)
426	404
427	405	/* Valid range of operand is 0..n rather than 0..n-1. */
428		−#define PPC_OPERAND_PLUS1 (0x40000)
	406	+#define PPC_OPERAND_PLUS1 (0x20000)
429	407
430	408	/* This operand is optional, and is zero if omitted. This is used for
431	409	example, in the optional BF field in the comparison instructions. The
@@ -443,6 +421,11 @@ extern const unsigned int num_powerpc_operands; · 11 unmodified lines
443	421	out regardless of the PPC_OPERAND_OPTIONAL field. */
444	422	#define PPC_OPERAND_NEXT (0x100000)
445	423
	424	+/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
	425	+ is omitted, then the value it should use for the operand is stored
	426	+ in the SHIFT field of the immediatly following operand field. */
	427	+#define PPC_OPERAND_OPTIONAL_VALUE (0x200000)
	428	+
446	429	/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
447	430	only optional when generating 32-bit code. */
448	431	#define PPC_OPERAND_OPTIONAL32 (0x400000)
@@ -481,19 +464,14 @@ extern const int powerpc_num_macros; · 32 unmodified lines
481	464	extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t , const char );
482	465
483	466	static inline int64_t
484		−ppc_optional_operand_value (const struct powerpc_operand *operand,
485		− uint64_t insn,
486		− ppc_cpu_t dialect,
487		− int num_optional)
	467	+ppc_optional_operand_value (const struct powerpc_operand *operand)
488	468	{
489		− if (operand->extract)
490		− return (*operand->extract) (insn, dialect, &num_optional);
	469	+ if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
	470	+ return (operand+1)->shift;
491	471	return 0;
492	472	}
493	473
494	474	/* PowerPC VLE insns. */
495		−#define E_OPCODE_MASK 0xfc00f800
496		−
497	475	/* Form I16L, uses 16A relocs. */
498	476	#define E_OR2I_INSN 0x7000C000
499	477	#define E_AND2I_DOT_INSN 0x7000C800
@@ -510,9 +488,6 @@ ppc_optional_operand_value (const struct powerpc_operand *operand, · 10 unmodified lines
510	488	#define E_CMPH16I_INSN 0x7000B000
511	489	#define E_CMPHL16I_INSN 0x7000B800
512	490
513		−#define E_LI_INSN 0x70000000
514		−#define E_LI_MASK 0xfc008000
515		−
516	491	#ifdef __cplusplus
517	492	}
518	493	#endif

binutils/include/opcode/pru.h+1−1

@@ -1,5 +1,5 @@
1	1	/* TI PRU opcode list for GAS, the GNU assembler.
2		− Copyright (C) 2014-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2014-2018 Free Software Foundation, Inc.
3	3	Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
4	4
5	5	This file is part of the GNU opcodes library.

binutils/include/opcode/pyr.h+1−1

@@ -1,6 +1,6 @@
1	1	/* pyramid.opcode.h -- gdb initial attempt.
2	2
3		− Copyright (C) 2001-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2001-2018 Free Software Foundation, Inc.
4	4
5	5	This program is free software; you can redistribute it and/or modify
6	6	it under the terms of the GNU General Public License as published by

binutils/include/opcode/riscv-opc.h+293−305

@@ -1,26 +1,6 @@
1		−/* riscv-opc.h. RISC-V instruction opcode and CSR macros.
2		− Copyright (C) 2011-2020 Free Software Foundation, Inc.
3		− Contributed by Andrew Waterman
4		−
5		− This file is part of GDB, GAS, and the GNU binutils.
6		−
7		− GDB, GAS, and the GNU binutils are free software; you can redistribute
8		− them and/or modify them under the terms of the GNU General Public
9		− License as published by the Free Software Foundation; either version
10		− 3, or (at your option) any later version.
11		−
12		− GDB, GAS, and the GNU binutils are distributed in the hope that they
13		− will be useful, but WITHOUT ANY WARRANTY; without even the implied
14		− warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15		− the GNU General Public License for more details.
16		−
17		− You should have received a copy of the GNU General Public License
18		− along with this program; see the file COPYING3. If not,
19		− see <http://www.gnu.org/licenses/>. */
20		−
	1	+/* Automatically generated by parse-opcodes. */
21	2	#ifndef RISCV_ENCODING_H
22	3	#define RISCV_ENCODING_H
23		−/* Instruction opcode macros. */
24	4	#define MATCH_SLLI_RV32 0x1013
25	5	#define MASK_SLLI_RV32 0xfe00707f
26	6	#define MATCH_SRLI_RV32 0x5013
@@ -161,8 +141,6 @@ · 134 unmodified lines
161	141	#define MASK_FENCE 0x707f
162	142	#define MATCH_FENCE_I 0x100f
163	143	#define MASK_FENCE_I 0x707f
164		−#define MATCH_FENCE_TSO 0x8330000f
165		−#define MASK_FENCE_TSO 0xfff0707f
166	144	#define MATCH_MUL 0x2000033
167	145	#define MASK_MUL 0xfe00707f
168	146	#define MATCH_MULH 0x2001033
@@ -595,7 +573,6 @@ · 426 unmodified lines
595	573	#define MASK_CUSTOM3_RD_RS1 0x707f
596	574	#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
597	575	#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
598		−/* Privileged CSR addresses (v1.11). */
599	576	#define CSR_USTATUS 0x0
600	577	#define CSR_UIE 0x4
601	578	#define CSR_UTVEC 0x5
@@ -604,6 +581,9 @@ · 2 unmodified lines
604	581	#define CSR_UCAUSE 0x42
605	582	#define CSR_UTVAL 0x43
606	583	#define CSR_UIP 0x44
	584	+#define CSR_FFLAGS 0x1
	585	+#define CSR_FRM 0x2
	586	+#define CSR_FCSR 0x3
607	587	#define CSR_CYCLE 0xc00
608	588	#define CSR_TIME 0xc01
609	589	#define CSR_INSTRET 0xc02
@@ -778,7 +758,6 @@ · 168 unmodified lines
778	758	#define CSR_MHPMCOUNTER29H 0xb9d
779	759	#define CSR_MHPMCOUNTER30H 0xb9e
780	760	#define CSR_MHPMCOUNTER31H 0xb9f
781		−#define CSR_MCOUNTINHIBIT 0x320
782	761	#define CSR_MHPMEVENT3 0x323
783	762	#define CSR_MHPMEVENT4 0x324
784	763	#define CSR_MHPMEVENT5 0x325
@@ -808,6 +787,14 @@ · 23 unmodified lines
808	787	#define CSR_MHPMEVENT29 0x33d
809	788	#define CSR_MHPMEVENT30 0x33e
810	789	#define CSR_MHPMEVENT31 0x33f
	790	+#define CSR_TSELECT 0x7a0
	791	+#define CSR_TDATA1 0x7a1
	792	+#define CSR_TDATA2 0x7a2
	793	+#define CSR_TDATA3 0x7a3
	794	+#define CSR_DCSR 0x7b0
	795	+#define CSR_DPC 0x7b1
	796	+#define CSR_DSCRATCH 0x7b2
	797	+/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
811	798	#define CSR_HSTATUS 0x200
812	799	#define CSR_HEDELEG 0x202
813	800	#define CSR_HIDELEG 0x203
@@ -818,31 +805,29 @@ · 4 unmodified lines
818	805	#define CSR_HCAUSE 0x242
819	806	#define CSR_HBADADDR 0x243
820	807	#define CSR_HIP 0x244
	808	+/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
821	809	#define CSR_MBASE 0x380
822	810	#define CSR_MBOUND 0x381
823	811	#define CSR_MIBASE 0x382
824	812	#define CSR_MIBOUND 0x383
825	813	#define CSR_MDBASE 0x384
826	814	#define CSR_MDBOUND 0x385
	815	+#define CSR_MUCOUNTEREN 0x320
827	816	#define CSR_MSCOUNTEREN 0x321
828	817	#define CSR_MHCOUNTEREN 0x322
829		−/* Unprivileged CSR addresses. */
830		−#define CSR_FFLAGS 0x1
831		−#define CSR_FRM 0x2
832		−#define CSR_FCSR 0x3
833		−#define CSR_DCSR 0x7b0
834		−#define CSR_DPC 0x7b1
835		−#define CSR_DSCRATCH0 0x7b2
836		−#define CSR_DSCRATCH1 0x7b3
837		−#define CSR_TSELECT 0x7a0
838		−#define CSR_TDATA1 0x7a1
839		−#define CSR_TDATA2 0x7a2
840		−#define CSR_TDATA3 0x7a3
841		−#define CSR_TINFO 0x7a4
842		−#define CSR_TCONTROL 0x7a5
843		−#define CSR_MCONTEXT 0x7a8
844		−#define CSR_SCONTEXT 0x7aa
845		−#endif /* RISCV_ENCODING_H. */
	818	+#define CAUSE_MISALIGNED_FETCH 0x0
	819	+#define CAUSE_FAULT_FETCH 0x1
	820	+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
	821	+#define CAUSE_BREAKPOINT 0x3
	822	+#define CAUSE_MISALIGNED_LOAD 0x4
	823	+#define CAUSE_FAULT_LOAD 0x5
	824	+#define CAUSE_MISALIGNED_STORE 0x6
	825	+#define CAUSE_FAULT_STORE 0x7
	826	+#define CAUSE_USER_ECALL 0x8
	827	+#define CAUSE_SUPERVISOR_ECALL 0x9
	828	+#define CAUSE_HYPERVISOR_ECALL 0xa
	829	+#define CAUSE_MACHINE_ECALL 0xb
	830	+#endif
846	831	#ifdef DECLARE_INSN
847	832	DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
848	833	DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
@@ -1127,268 +1112,271 @@ DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) · 278 unmodified lines
1127	1112	DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
1128	1113	DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
1129	1114	DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
1130		−#endif /* DECLARE_INSN. */
	1115	+#endif
1131	1116	#ifdef DECLARE_CSR
1132		−/* Privileged. */
1133		−DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1134		−DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1135		−DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1136		−DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1137		−DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1138		−DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1139		−DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1140		−DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1141		−DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1142		−DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1143		−DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1144		−DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1145		−DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1146		−DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1147		−DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1148		−DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1149		−DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1150		−DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1151		−DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1152		−DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1153		−DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1154		−DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1155		−DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1156		−DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1157		−DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1158		−DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1159		−DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1160		−DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1161		−DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1162		−DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1163		−DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1164		−DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1165		−DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1166		−DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1167		−DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1168		−DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1169		−DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1170		−DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1171		−DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1172		−DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1173		−DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1174		−DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1175		−DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1176		−DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1177		−DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1178		−DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1179		−DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1180		−DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1181		−DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1182		−DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1183		−DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1184		−DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1185		−DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1186		−DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1187		−DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1188		−DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1189		−DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1190		−DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1191		−DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1192		−DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1193		−DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1194		−DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1195		−DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1196		−DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1197		−DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1198		−DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1199		−DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1200		−DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1201		−DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1202		−DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1203		−DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1204		−DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1205		−DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1206		−DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1207		−DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1208		−DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1209		−DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1210		−DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1211		−DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1212		−DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1213		−DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1214		−DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1215		−DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1216		−DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1217		−DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1218		−DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1219		−DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1220		−DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1221		−DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1222		−DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1223		−DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1224		−DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1225		−DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1226		−DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1227		−DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1228		−DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1229		−DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1230		−DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1231		−DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1232		−DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1233		−DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1234		−DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1235		−DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1236		−DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1237		−DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1238		−DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1239		−DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1240		−DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1241		−DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1242		−DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1243		−DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1244		−DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1245		−DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1246		−DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1247		−DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1248		−DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1249		−DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1250		−DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1251		−DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1252		−DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_DRAFT)
1253		−DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1254		−DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1255		−DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1256		−DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1257		−DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1258		−DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1259		−DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1260		−DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1261		−DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1262		−DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1263		−DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1264		−DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1265		−DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1266		−DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1267		−DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1268		−DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1269		−DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1270		−DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1271		−DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1272		−DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1273		−DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1274		−DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1275		−DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1276		−DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1277		−DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1278		−DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1279		−DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1280		−DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1281		−DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1282		−DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1283		−DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1284		−DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1285		−DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1286		−DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1287		−DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1288		−DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1289		−DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1290		−DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1291		−DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1292		−DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1293		−DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1294		−DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1295		−DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1296		−DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1297		−DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1298		−DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1299		−DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1300		−DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1301		−DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1302		−DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1303		−DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1304		−DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1305		−DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1306		−DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1307		−DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1308		−DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1309		−DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1310		−DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1311		−DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1312		−DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1313		−DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1314		−DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1315		−DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P11, PRIV_SPEC_CLASS_DRAFT)
1316		−DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1317		−DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1318		−DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1319		−DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1320		−DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1321		−DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1322		−DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1323		−DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1324		−DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1325		−DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1326		−DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1327		−DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1328		−DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1329		−DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1330		−DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1331		−DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1332		−DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1333		−DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1334		−DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1335		−DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1336		−DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1337		−DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1338		−DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1339		−DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1340		−DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1341		−DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1342		−DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1343		−DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1344		−DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
1345		−/* Dropped. */
1346		−DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1347		−DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1348		−DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1349		−DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1350		−DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1351		−DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1352		−DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1353		−DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1354		−DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1355		−DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1356		−DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1357		−DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1358		−DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1359		−DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1360		−DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1361		−DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1362		−DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1363		−DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1364		−/* Unprivileged. */
1365		−DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1366		−DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1367		−DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1368		−DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1369		−DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1370		−DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1371		−DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1372		−DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1373		−DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1374		−DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1375		−DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1376		−DECLARE_CSR(tinfo, CSR_TINFO, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1377		−DECLARE_CSR(tcontrol, CSR_TCONTROL, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1378		−DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1379		−DECLARE_CSR(scontext, CSR_SCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1380		−#endif /* DECLARE_CSR. */
	1117	+DECLARE_CSR(ustatus, CSR_USTATUS)
	1118	+DECLARE_CSR(uie, CSR_UIE)
	1119	+DECLARE_CSR(utvec, CSR_UTVEC)
	1120	+DECLARE_CSR(uscratch, CSR_USCRATCH)
	1121	+DECLARE_CSR(uepc, CSR_UEPC)
	1122	+DECLARE_CSR(ucause, CSR_UCAUSE)
	1123	+DECLARE_CSR(utval, CSR_UTVAL)
	1124	+DECLARE_CSR(uip, CSR_UIP)
	1125	+DECLARE_CSR(fflags, CSR_FFLAGS)
	1126	+DECLARE_CSR(frm, CSR_FRM)
	1127	+DECLARE_CSR(fcsr, CSR_FCSR)
	1128	+DECLARE_CSR(cycle, CSR_CYCLE)
	1129	+DECLARE_CSR(time, CSR_TIME)
	1130	+DECLARE_CSR(instret, CSR_INSTRET)
	1131	+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
	1132	+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
	1133	+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
	1134	+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
	1135	+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
	1136	+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
	1137	+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
	1138	+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
	1139	+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
	1140	+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
	1141	+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
	1142	+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
	1143	+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
	1144	+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
	1145	+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
	1146	+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
	1147	+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
	1148	+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
	1149	+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
	1150	+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
	1151	+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
	1152	+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
	1153	+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
	1154	+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
	1155	+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
	1156	+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
	1157	+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
	1158	+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
	1159	+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
	1160	+DECLARE_CSR(cycleh, CSR_CYCLEH)
	1161	+DECLARE_CSR(timeh, CSR_TIMEH)
	1162	+DECLARE_CSR(instreth, CSR_INSTRETH)
	1163	+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
	1164	+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
	1165	+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
	1166	+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
	1167	+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
	1168	+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
	1169	+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
	1170	+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
	1171	+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
	1172	+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
	1173	+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
	1174	+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
	1175	+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
	1176	+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
	1177	+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
	1178	+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
	1179	+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
	1180	+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
	1181	+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
	1182	+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
	1183	+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
	1184	+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
	1185	+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
	1186	+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
	1187	+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
	1188	+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
	1189	+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
	1190	+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
	1191	+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
	1192	+DECLARE_CSR(sstatus, CSR_SSTATUS)
	1193	+DECLARE_CSR(sedeleg, CSR_SEDELEG)
	1194	+DECLARE_CSR(sideleg, CSR_SIDELEG)
	1195	+DECLARE_CSR(sie, CSR_SIE)
	1196	+DECLARE_CSR(stvec, CSR_STVEC)
	1197	+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
	1198	+DECLARE_CSR(sscratch, CSR_SSCRATCH)
	1199	+DECLARE_CSR(sepc, CSR_SEPC)
	1200	+DECLARE_CSR(scause, CSR_SCAUSE)
	1201	+DECLARE_CSR(stval, CSR_STVAL)
	1202	+DECLARE_CSR(sip, CSR_SIP)
	1203	+DECLARE_CSR(satp, CSR_SATP)
	1204	+DECLARE_CSR(mvendorid, CSR_MVENDORID)
	1205	+DECLARE_CSR(marchid, CSR_MARCHID)
	1206	+DECLARE_CSR(mimpid, CSR_MIMPID)
	1207	+DECLARE_CSR(mhartid, CSR_MHARTID)
	1208	+DECLARE_CSR(mstatus, CSR_MSTATUS)
	1209	+DECLARE_CSR(misa, CSR_MISA)
	1210	+DECLARE_CSR(medeleg, CSR_MEDELEG)
	1211	+DECLARE_CSR(mideleg, CSR_MIDELEG)
	1212	+DECLARE_CSR(mie, CSR_MIE)
	1213	+DECLARE_CSR(mtvec, CSR_MTVEC)
	1214	+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
	1215	+DECLARE_CSR(mscratch, CSR_MSCRATCH)
	1216	+DECLARE_CSR(mepc, CSR_MEPC)
	1217	+DECLARE_CSR(mcause, CSR_MCAUSE)
	1218	+DECLARE_CSR(mtval, CSR_MTVAL)
	1219	+DECLARE_CSR(mip, CSR_MIP)
	1220	+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
	1221	+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
	1222	+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
	1223	+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
	1224	+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
	1225	+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
	1226	+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
	1227	+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
	1228	+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
	1229	+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
	1230	+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
	1231	+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
	1232	+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
	1233	+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
	1234	+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
	1235	+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
	1236	+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
	1237	+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
	1238	+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
	1239	+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
	1240	+DECLARE_CSR(mcycle, CSR_MCYCLE)
	1241	+DECLARE_CSR(minstret, CSR_MINSTRET)
	1242	+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
	1243	+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
	1244	+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
	1245	+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
	1246	+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
	1247	+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
	1248	+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
	1249	+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
	1250	+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
	1251	+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
	1252	+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
	1253	+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
	1254	+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
	1255	+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
	1256	+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
	1257	+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
	1258	+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
	1259	+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
	1260	+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
	1261	+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
	1262	+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
	1263	+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
	1264	+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
	1265	+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
	1266	+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
	1267	+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
	1268	+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
	1269	+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
	1270	+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
	1271	+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
	1272	+DECLARE_CSR(minstreth, CSR_MINSTRETH)
	1273	+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
	1274	+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
	1275	+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
	1276	+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
	1277	+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
	1278	+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
	1279	+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
	1280	+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
	1281	+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
	1282	+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
	1283	+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
	1284	+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
	1285	+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
	1286	+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
	1287	+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
	1288	+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
	1289	+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
	1290	+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
	1291	+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
	1292	+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
	1293	+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
	1294	+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
	1295	+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
	1296	+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
	1297	+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
	1298	+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
	1299	+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
	1300	+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
	1301	+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
	1302	+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
	1303	+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
	1304	+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
	1305	+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
	1306	+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
	1307	+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
	1308	+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
	1309	+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
	1310	+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
	1311	+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
	1312	+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
	1313	+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
	1314	+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
	1315	+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
	1316	+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
	1317	+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
	1318	+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
	1319	+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
	1320	+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
	1321	+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
	1322	+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
	1323	+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
	1324	+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
	1325	+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
	1326	+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
	1327	+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
	1328	+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
	1329	+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
	1330	+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
	1331	+DECLARE_CSR(tselect, CSR_TSELECT)
	1332	+DECLARE_CSR(tdata1, CSR_TDATA1)
	1333	+DECLARE_CSR(tdata2, CSR_TDATA2)
	1334	+DECLARE_CSR(tdata3, CSR_TDATA3)
	1335	+DECLARE_CSR(dcsr, CSR_DCSR)
	1336	+DECLARE_CSR(dpc, CSR_DPC)
	1337	+DECLARE_CSR(dscratch, CSR_DSCRATCH)
	1338	+/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
	1339	+DECLARE_CSR(hstatus, CSR_HSTATUS)
	1340	+DECLARE_CSR(hedeleg, CSR_HEDELEG)
	1341	+DECLARE_CSR(hideleg, CSR_HIDELEG)
	1342	+DECLARE_CSR(hie, CSR_HIE)
	1343	+DECLARE_CSR(htvec, CSR_HTVEC)
	1344	+DECLARE_CSR(hscratch, CSR_HSCRATCH)
	1345	+DECLARE_CSR(hepc, CSR_HEPC)
	1346	+DECLARE_CSR(hcause, CSR_HCAUSE)
	1347	+DECLARE_CSR(hbadaddr, CSR_HBADADDR)
	1348	+DECLARE_CSR(hip, CSR_HIP)
	1349	+DECLARE_CSR(mbase, CSR_MBASE)
	1350	+DECLARE_CSR(mbound, CSR_MBOUND)
	1351	+DECLARE_CSR(mibase, CSR_MIBASE)
	1352	+DECLARE_CSR(mibound, CSR_MIBOUND)
	1353	+DECLARE_CSR(mdbase, CSR_MDBASE)
	1354	+DECLARE_CSR(mdbound, CSR_MDBOUND)
	1355	+DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
	1356	+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
	1357	+DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
	1358	+#endif
1381	1359	#ifdef DECLARE_CSR_ALIAS
1382		−DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1383		−DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1384		−DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1385		−DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1386		−DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
1387		−DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1388		−DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1389		−DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1390		−DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1391		−DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1392		−DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1393		−DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
1394		−#endif /* DECLARE_CSR_ALIAS. */
	1360	+/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
	1361	+DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
	1362	+/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
	1363	+DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
	1364	+/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
	1365	+DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
	1366	+/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
	1367	+DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
	1368	+#endif
	1369	+#ifdef DECLARE_CAUSE
	1370	+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
	1371	+DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
	1372	+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
	1373	+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
	1374	+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
	1375	+DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
	1376	+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
	1377	+DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
	1378	+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
	1379	+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
	1380	+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
	1381	+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
	1382	+#endif

binutils/include/opcode/riscv.h+7−137

@@ -1,5 +1,5 @@
1	1	/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
2		− Copyright (C) 2011-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2011-2018 Free Software Foundation, Inc.
3	3	Contributed by Andrew Waterman
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
@@ -204,7 +204,7 @@ static const char * const riscv_pred_succ[16] = · 198 unmodified lines
204	204	#define OP_SH_RS2 20
205	205	#define OP_MASK_RS1 0x1f
206	206	#define OP_SH_RS1 15
207		−#define OP_MASK_RS3 0x1fU
	207	+#define OP_MASK_RS3 0x1f
208	208	#define OP_SH_RS3 27
209	209	#define OP_MASK_RD 0x1f
210	210	#define OP_SH_RD 7
@@ -223,14 +223,14 @@ static const char * const riscv_pred_succ[16] = · 12 unmodified lines
223	223	#define OP_MASK_RL 0x1
224	224	#define OP_SH_RL 25
225	225
226		−#define OP_MASK_CUSTOM_IMM 0x7fU
	226	+#define OP_MASK_CUSTOM_IMM 0x7f
227	227	#define OP_SH_CUSTOM_IMM 25
228		−#define OP_MASK_CSR 0xfffU
	228	+#define OP_MASK_CSR 0xfff
229	229	#define OP_SH_CSR 20
230	230
231	231	#define OP_MASK_FUNCT3 0x7
232	232	#define OP_SH_FUNCT3 12
233		−#define OP_MASK_FUNCT7 0x7fU
	233	+#define OP_MASK_FUNCT7 0x7f
234	234	#define OP_SH_FUNCT7 25
235	235	#define OP_MASK_FUNCT2 0x3
236	236	#define OP_SH_FUNCT2 25
@@ -247,14 +247,10 @@ static const char * const riscv_pred_succ[16] = · 10 unmodified lines
247	247	#define OP_MASK_CRS2S 0x7
248	248	#define OP_SH_CRS2S 2
249	249
250		−#define OP_MASK_CFUNCT6 0x3f
251		−#define OP_SH_CFUNCT6 10
252	250	#define OP_MASK_CFUNCT4 0xf
253	251	#define OP_SH_CFUNCT4 12
254	252	#define OP_MASK_CFUNCT3 0x7
255	253	#define OP_SH_CFUNCT3 13
256		−#define OP_MASK_CFUNCT2 0x3
257		−#define OP_SH_CFUNCT2 5
258	254
259	255	/* ABI names for selected x-registers. */
260	256
@@ -270,12 +266,6 @@ static const char * const riscv_pred_succ[16] = · 9 unmodified lines
270	266	#define NGPR 32
271	267	#define NFPR 32
272	268
273		−/* These fake label defines are use by both the assembler, and
274		− libopcodes. The assembler uses this when it needs to generate a fake
275		− label, and libopcodes uses it to hide the fake labels in its output. */
276		−#define RISCV_FAKE_LABEL_NAME ".L0 "
277		−#define RISCV_FAKE_LABEL_CHAR ' '
278		−
279	269	/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
280	270	VALUE << SHIFT. VALUE is evaluated exactly once. */
281	271	#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
@@ -291,37 +281,14 @@ static const char * const riscv_pred_succ[16] = · 9 unmodified lines
291	281	#define EXTRACT_OPERAND(FIELD, INSN) \
292	282	EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
293	283
294		−/* The maximal number of subset can be required. */
295		−#define MAX_SUBSET_NUM 4
296		−
297		−/* All RISC-V instructions belong to at least one of these classes. */
298		−
299		−enum riscv_insn_class
300		− {
301		− INSN_CLASS_NONE,
302		−
303		− INSN_CLASS_I,
304		− INSN_CLASS_C,
305		− INSN_CLASS_A,
306		− INSN_CLASS_M,
307		− INSN_CLASS_F,
308		− INSN_CLASS_D,
309		− INSN_CLASS_D_AND_C,
310		− INSN_CLASS_F_AND_C,
311		− INSN_CLASS_Q,
312		− };
313		−
314	284	/* This structure holds information for a particular instruction. */
315	285
316	286	struct riscv_opcode
317	287	{
318	288	/* The name of the instruction. */
319	289	const char *name;
320		− /* The requirement of xlen for the instruction, 0 if no requirement. */
321		− unsigned xlen_requirement;
322		− /* Class to which this instruction belongs. Used to decide whether or
323		− not this instruction is legal in the current -march context. */
324		− enum riscv_insn_class insn_class;
	290	+ /* The ISA subset name (I, M, A, F, D, Xextension). */
	291	+ const char *subset;
325	292	/* A string describing the arguments for this instruction. */
326	293	const char *args;
327	294	/* The basic opcode for the instruction. When assembling, this
@@ -343,101 +310,8 @@ struct riscv_opcode · 15 unmodified lines
343	310	unsigned long pinfo;
344	311	};
345	312
346		−/* The current supported ISA spec versions. */
347		−
348		−enum riscv_isa_spec_class
349		−{
350		− ISA_SPEC_CLASS_NONE,
351		−
352		− ISA_SPEC_CLASS_2P2,
353		− ISA_SPEC_CLASS_20190608,
354		− ISA_SPEC_CLASS_20191213
355		−};
356		−
357		−/* This structure holds version information for specific ISA. */
358		−
359		−struct riscv_ext_version
360		−{
361		− const char *name;
362		− enum riscv_isa_spec_class isa_spec_class;
363		− unsigned int major_version;
364		− unsigned int minor_version;
365		−};
366		−
367		−/* All RISC-V CSR belong to one of these classes. */
368		−
369		−enum riscv_csr_class
370		−{
371		− CSR_CLASS_NONE,
372		−
373		− CSR_CLASS_I,
374		− CSR_CLASS_I_32, /* rv32 only */
375		− CSR_CLASS_F, /* f-ext only */
376		− CSR_CLASS_DEBUG /* debug CSR */
377		−};
378		−
379		−/* The current supported privilege spec versions. */
380		−
381		−enum riscv_priv_spec_class
382		−{
383		− PRIV_SPEC_CLASS_NONE,
384		−
385		− PRIV_SPEC_CLASS_1P9P1,
386		− PRIV_SPEC_CLASS_1P10,
387		− PRIV_SPEC_CLASS_1P11,
388		− PRIV_SPEC_CLASS_DRAFT
389		−};
390		−
391		−/* This structure holds all restricted conditions for a CSR. */
392		−
393		−struct riscv_csr_extra
394		−{
395		− /* Class to which this CSR belongs. Used to decide whether or
396		− not this CSR is legal in the current -march context. */
397		− enum riscv_csr_class csr_class;
398		−
399		− /* CSR may have differnet numbers in the previous priv spec. */
400		− unsigned address;
401		−
402		− /* Record the CSR is defined/valid in which versions. */
403		− enum riscv_priv_spec_class define_version;
404		−
405		− /* Record the CSR is aborted/invalid from which versions. If it isn't
406		− aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
407		− enum riscv_priv_spec_class abort_version;
408		−
409		− /* The CSR may have more than one setting. */
410		− struct riscv_csr_extra *next;
411		−};
412		−
413	313	/* Instruction is a simple alias (e.g. "mv" for "addi"). */
414	314	#define INSN_ALIAS 0x00000001
415		−
416		−/* These are for setting insn_info fields.
417		−
418		− Nonbranch is the default. Noninsn is used only if there is no match.
419		− There are no condjsr or dref2 instructions. So that leaves condbranch,
420		− branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
421		−#define INSN_TYPE 0x0000000e
422		−
423		−/* Instruction is an unconditional branch. */
424		−#define INSN_BRANCH 0x00000002
425		−/* Instruction is a conditional branch. */
426		−#define INSN_CONDBRANCH 0x00000004
427		−/* Instruction is a jump to subroutine. */
428		−#define INSN_JSR 0x00000006
429		−/* Instruction is a data reference. */
430		−#define INSN_DREF 0x00000008
431		−
432		−/* We have 5 data reference sizes, which we can encode in 3 bits. */
433		−#define INSN_DATA_SIZE 0x00000070
434		−#define INSN_DATA_SIZE_SHIFT 4
435		−#define INSN_1_BYTE 0x00000010
436		−#define INSN_2_BYTE 0x00000020
437		−#define INSN_4_BYTE 0x00000030
438		−#define INSN_8_BYTE 0x00000040
439		−#define INSN_16_BYTE 0x00000050
440		−
441	315	/* Instruction is actually a macro. It should be ignored by the
442	316	disassembler, and requires special treatment by the assembler. */
443	317	#define INSN_MACRO 0xffffffff
@@ -487,9 +361,5 @@ extern const char * const riscv_fpr_names_abi[NFPR]; · 43 unmodified lines
487	361
488	362	extern const struct riscv_opcode riscv_opcodes[];
489	363	extern const struct riscv_opcode riscv_insn_types[];
490		−extern const struct riscv_ext_version riscv_ext_version_table[];
491		−
492		−extern int
493		−riscv_get_isa_spec_class (const char , enum riscv_isa_spec_class );
494	364
495	365	#endif /* _RISCV_H_ */

binutils/include/opcode/rl78.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Opcode decoder for the Renesas RL78
2		− Copyright (C) 2011-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2011-2018 Free Software Foundation, Inc.
3	3	Written by DJ Delorie <dj@redhat.com>
4	4
5	5	This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.

binutils/include/opcode/rx.h+1−33

@@ -1,5 +1,5 @@
1	1	/* Opcode decoder for the Renesas RX
2		− Copyright (C) 2008-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2008-2018 Free Software Foundation, Inc.
3	3	Written by DJ Delorie <dj@redhat.com>
4	4
5	5	This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
@@ -38,7 +38,6 @@ typedef enum · 32 unmodified lines
38	38	RX_SWord,
39	39	RX_3Byte,
40	40	RX_Long,
41		− RX_Double,
42	41	RX_Bad_Size,
43	42	RX_MAX_SIZE
44	43	} RX_Size;
@@ -55,11 +54,6 @@ typedef enum · 10 unmodified lines
55	54	RX_Operand_Condition, /* eq, gtu, etc */
56	55	RX_Operand_Flag, /* [UIOSZC] */
57	56	RX_Operand_TwoReg, /* [Rn + scaleR2] /
58		− RX_Operand_DoubleReg, /* DRn */
59		− RX_Operand_DoubleRegH,/* DRHn */
60		− RX_Operand_DoubleRegL,/* DRLn */
61		− RX_Operand_DoubleCReg,/* DCRxx */
62		− RX_Operand_DoubleCond,/* UN/EQ/LE/LT */
63	57	} RX_Operand_Type;
64	58
65	59	typedef enum
@@ -186,32 +180,6 @@ typedef enum · 120 unmodified lines
186	180	RXO_racl,
187	181	RXO_rdacl,
188	182	RXO_rdacw,
189		−
190		− RXO_bfmov,
191		− RXO_bfmovz,
192		− RXO_rstr,
193		− RXO_save,
194		− RXO_dmov,
195		− RXO_dpopm,
196		− RXO_dpushm,
197		− RXO_mvfdc,
198		− RXO_mvfdr,
199		− RXO_mvtdc,
200		− RXO_dabs,
201		− RXO_dadd,
202		− RXO_dcmp,
203		− RXO_ddiv,
204		− RXO_dmul,
205		− RXO_dneg,
206		− RXO_dround,
207		− RXO_dsqrt,
208		− RXO_dsub,
209		− RXO_dtoi,
210		− RXO_dtof,
211		− RXO_dtou,
212		− RXO_ftod,
213		− RXO_itod,
214		− RXO_utod
215	183	} RX_Opcode_ID;
216	184
217	185	/* Condition bitpatterns, as registers. */

binutils/include/opcode/s12z.h+0−75

@@ -1,75 +0,0 @@
1		−#ifndef S12Z_H
2		−#define S12Z_H
3		−
4		−/* This byte is used to prefix instructions in "page 2" of the opcode
5		− space. */
6		−#define PAGE2_PREBYTE (0x1b)
7		−
8		−struct reg
9		−{
10		− char name; / The canonical name of the register. */
11		− int bytes; /* its size, in bytes. */
12		−};
13		−
14		−
15		−/* How many registers do we have. Actually there are only 13,
16		− because CCL and CCH are the low and high bytes of CCW. But
17		− for assemnbly / disassembly purposes they are considered
18		− distinct registers. */
19		−#define S12Z_N_REGISTERS 15
20		−
21		−extern const struct reg registers[S12Z_N_REGISTERS];
22		−
23		−/* Solaris defines REG_Y in sys/regset.h; undef it here to avoid
24		− breaking compilation when this target is enabled. */
25		−#undef REG_Y
26		−
27		−enum
28		− {
29		− REG_D2 = 0,
30		− REG_D3,
31		− REG_D4,
32		− REG_D5,
33		− REG_D0,
34		− REG_D1,
35		− REG_D6,
36		− REG_D7,
37		− REG_X,
38		− REG_Y,
39		− REG_S,
40		− REG_P,
41		− REG_CCH,
42		− REG_CCL,
43		− REG_CCW
44		− };
45		−
46		−/* Any of the registers d0, d1, ... d7. */
47		−#define REG_BIT_Dn \
48		−((0x1U << REG_D2) \| \
49		− (0x1U << REG_D3) \| \
50		− (0x1U << REG_D4) \| \
51		− (0x1U << REG_D5) \| \
52		− (0x1U << REG_D6) \| \
53		− (0x1U << REG_D7) \| \
54		− (0x1U << REG_D0) \| \
55		− (0x1U << REG_D1))
56		−
57		−/* Any of the registers x, y or z. */
58		−#define REG_BIT_XYS \
59		−((0x1U << REG_X) \| \
60		− (0x1U << REG_Y) \| \
61		− (0x1U << REG_S))
62		−
63		−/* Any of the registers x, y, z or p. */
64		−#define REG_BIT_XYSP \
65		−((0x1U << REG_X) \| \
66		− (0x1U << REG_Y) \| \
67		− (0x1U << REG_S) \| \
68		− (0x1U << REG_P))
69		−
70		−/* The x register or the y register. */
71		−#define REG_BIT_XY \
72		−((0x1U << REG_X) \| \
73		− (0x1U << REG_Y))
74		−
75		−#endif

binutils/include/opcode/s390.h+1−2

@@ -1,5 +1,5 @@
1	1	/* s390.h -- Header file for S390 opcode table
2		− Copyright (C) 2000-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2000-2018 Free Software Foundation, Inc.
3	3	Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
4	4
5	5	This file is part of BFD, the Binary File Descriptor library.
@@ -43,7 +43,6 @@ enum s390_opcode_cpu_val · 37 unmodified lines
43	43	S390_OPCODE_ZEC12,
44	44	S390_OPCODE_Z13,
45	45	S390_OPCODE_ARCH12,
46		− S390_OPCODE_ARCH13,
47	46	S390_OPCODE_MAXCPU
48	47	};
49	48

binutils/include/opcode/score-datadep.h+1−1

@@ -1,5 +1,5 @@
1	1	/* score-datadep.h -- Score Instructions data dependency table
2		− Copyright (C) 2006-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2006-2018 Free Software Foundation, Inc.
3	3	Contributed by:
4	4	Brain.lin (brain.lin@sunplusct.com)
5	5	Mei Ligang (ligang@sunnorth.com.cn)

binutils/include/opcode/score-inst.h+1−1

@@ -1,5 +1,5 @@
1	1	/* score-inst.h -- Score Instructions Table
2		− Copyright (C) 2006-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2006-2018 Free Software Foundation, Inc.
3	3	Contributed by:
4	4	Brain.lin (brain.lin@sunplusct.com)
5	5	Mei Ligang (ligang@sunnorth.com.cn)

binutils/include/opcode/sparc.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Definitions for opcode table for the sparc.
2		− Copyright (C) 1989-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
5	5	the GNU Binutils.

binutils/include/opcode/spu-insns.h+1−1

@@ -1,6 +1,6 @@
1	1	/* SPU ELF support for BFD.
2	2
3		− Copyright (C) 2006-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2006-2018 Free Software Foundation, Inc.
4	4
5	5	This file is part of BFD, the Binary File Descriptor library.
6	6

binutils/include/opcode/spu.h+18−21

@@ -1,6 +1,6 @@
1	1	/* SPU ELF support for BFD.
2	2
3		− Copyright (C) 2006-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2006-2018 Free Software Foundation, Inc.
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
6	6
@@ -87,42 +87,39 @@ struct spu_opcode · 80 unmodified lines
87	87	int arg[5];
88	88	};
89	89
90		−#define UNSIGNED_EXTRACT(insn, size, pos) \
91		− (((insn) >> (pos)) & ((1u << (size)) - 1))
92		−#define SIGNED_EXTRACT(insn, size, pos) \
93		− (((int) UNSIGNED_EXTRACT(insn, size, pos) \
94		− ^ (1 << ((size) - 1))) - (1 << ((size) - 1)))
	90	+#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
	91	+#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
95	92
96	93	#define DECODE_INSN_RT(insn) (insn & 0x7f)
97	94	#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
98	95	#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
99	96	#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
100	97
101		−#define DECODE_INSN_I10(insn) SIGNED_EXTRACT (insn, 10, 14)
102		−#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT (insn, 10, 14)
	98	+#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
	99	+#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
103	100
104	101	/* For branching, immediate loads, hbr and lqa/stqa. */
105		−#define DECODE_INSN_I16(insn) SIGNED_EXTRACT (insn, 16, 7)
106		−#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT (insn, 16, 7)
	102	+#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
	103	+#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
107	104
108	105	/* for stop */
109		−#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT (insn, 14, 0)
	106	+#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
110	107
111	108	/* For ila */
112		−#define DECODE_INSN_I18(insn) SIGNED_EXTRACT (insn, 18, 7)
113		−#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT (insn, 18, 7)
	109	+#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
	110	+#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
114	111
115	112	/* For rotate and shift and generate control mask */
116		−#define DECODE_INSN_I7(insn) SIGNED_EXTRACT (insn, 7, 14)
117		−#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT (insn, 7, 14)
	113	+#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
	114	+#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
118	115
119	116	/* For float <-> int conversion */
120		−#define DECODE_INSN_I8(insn) SIGNED_EXTRACT (insn, 8, 14)
121		−#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT (insn, 8, 14)
	117	+#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
	118	+#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
122	119
123	120	/* For hbr */
124		−#define DECODE_INSN_I9a(insn) \
125		− ((SIGNED_EXTRACT (insn, 2, 23) * 128) \| (int) UNSIGNED_EXTRACT (insn, 7, 0))
126		−#define DECODE_INSN_I9b(insn) \
127		− ((SIGNED_EXTRACT (insn, 2, 14) * 128) \| (int) UNSIGNED_EXTRACT (insn, 7, 0))
	121	+#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) \| UNSIGNED_EXTRACT(insn,7,0))
	122	+#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) \| UNSIGNED_EXTRACT(insn,7,0))
	123	+#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) \| UNSIGNED_EXTRACT(insn,7,0))
	124	+#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) \| UNSIGNED_EXTRACT(insn,7,0))
128	125

binutils/include/opcode/tic30.h+1−1

@@ -1,5 +1,5 @@
1	1	/* tic30.h -- Header file for TI TMS320C30 opcode table
2		− Copyright (C) 1998-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1998-2018 Free Software Foundation, Inc.
3	3	Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/tic4x.h+6−8

@@ -1,6 +1,6 @@
1	1	/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
2	2
3		− Copyright (C) 2002-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2002-2018 Free Software Foundation, Inc.
4	4
5	5	Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
6	6
@@ -23,13 +23,11 @@ · 16 unmodified lines
23	23	#define IS_CPU_TIC4X(v) ((v) == 0 \|\| (v) == 40 \|\| (v) == 44)
24	24
25	25	/* Define some bitfield extraction/insertion macros. */
26		−#define EXTRU(inst, m, l) \
27		− (((inst) >> (l)) & ((2u << ((m) - (l))) - 1))
28		−#define EXTRS(inst, m, l) \
29		− ((int) ((EXTRU (inst, m, l) ^ (1u << ((m) - (l)))) - (1u << ((m) - (l)))))
30		−#define INSERTU(inst, val, m, l) \
31		− ((inst) \|= ((val) & ((2u << ((m) - (l))) - 1)) << (l))
32		−#define INSERTS INSERTU
	26	+#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
	27	+#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l))
	28	+#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l))
	29	+#define INSERTU(inst, val, m, l) (inst \|= ((val) << (l)))
	30	+#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l)
33	31
34	32	/* Define register numbers. */
35	33	typedef enum

binutils/include/opcode/tic54x.h+1−1

@@ -1,5 +1,5 @@
1	1	/* tic54x.h -- Header file for TI TMS320C54X opcode table
2		− Copyright (C) 1999-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1999-2018 Free Software Foundation, Inc.
3	3	Written by Timothy Wall (twall@cygnus.com)
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.

binutils/include/opcode/tic6x-control-registers.h+1−1

@@ -1,5 +1,5 @@
1	1	/* TI C6X control register information.
2		− Copyright (C) 2010-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2010-2018 Free Software Foundation, Inc.
3	3
4	4	This program is free software; you can redistribute it and/or modify
5	5	it under the terms of the GNU General Public License as published by

binutils/include/opcode/tic6x-insn-formats.h+1−1

@@ -1,5 +1,5 @@
1	1	/* TI C6X instruction format information.
2		− Copyright (C) 2010-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2010-2018 Free Software Foundation, Inc.
3	3
4	4	This program is free software; you can redistribute it and/or modify
5	5	it under the terms of the GNU General Public License as published by

binutils/include/opcode/tic6x-opcode-table.h+1−1

@@ -1,5 +1,5 @@
1	1	/* TI C6X opcode table.
2		− Copyright (C) 2010-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2010-2018 Free Software Foundation, Inc.
3	3
4	4	This program is free software; you can redistribute it and/or modify
5	5	it under the terms of the GNU General Public License as published by

binutils/include/opcode/tic6x.h+1−1

@@ -1,5 +1,5 @@
1	1	/* TI C6X opcode information.
2		− Copyright (C) 2010-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2010-2018 Free Software Foundation, Inc.
3	3
4	4	This program is free software; you can redistribute it and/or modify
5	5	it under the terms of the GNU General Public License as published by

binutils/include/opcode/tic80.h+283−0

@@ -0,0 +1,283 @@
	1	+/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
	3	+ Written by Fred Fish (fnf@cygnus.com), Cygnus Support
	4	+
	5	+ This file is part of GDB, GAS, and the GNU binutils.
	6	+
	7	+ GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	+ them and/or modify them under the terms of the GNU General Public
	9	+ License as published by the Free Software Foundation; either version 3,
	10	+ or (at your option) any later version.
	11	+
	12	+ GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	+ will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	+ the GNU General Public License for more details.
	16	+
	17	+ You should have received a copy of the GNU General Public License
	18	+ along with this file; see the file COPYING3. If not, write to the Free
	19	+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	20	+ MA 02110-1301, USA. */
	21	+
	22	+#ifndef TIC80_H
	23	+#define TIC80_H
	24	+
	25	+/* The opcode table is an array of struct tic80_opcode. */
	26	+
	27	+struct tic80_opcode
	28	+{
	29	+ /* The opcode name. */
	30	+
	31	+ const char *name;
	32	+
	33	+ /* The opcode itself. Those bits which will be filled in with operands
	34	+ are zeroes. */
	35	+
	36	+ unsigned long opcode;
	37	+
	38	+ /* The opcode mask. This is used by the disassembler. This is a mask
	39	+ containing ones indicating those bits which must match the opcode
	40	+ field, and zeroes indicating those bits which need not match (and are
	41	+ presumably filled in by operands). */
	42	+
	43	+ unsigned long mask;
	44	+
	45	+ /* Special purpose flags for this opcode. */
	46	+
	47	+ unsigned char flags;
	48	+
	49	+ /* An array of operand codes. Each code is an index into the operand
	50	+ table. They appear in the order which the operands must appear in
	51	+ assembly code, and are terminated by a zero. FIXME: Adjust size to
	52	+ match actual requirements when TIc80 support is complete */
	53	+
	54	+ unsigned char operands[8];
	55	+};
	56	+
	57	+/* The table itself is sorted by major opcode number, and is otherwise in
	58	+ the order in which the disassembler should consider instructions.
	59	+ FIXME: This isn't currently true. */
	60	+
	61	+extern const struct tic80_opcode tic80_opcodes[];
	62	+extern const int tic80_num_opcodes;
	63	+
	64	+
	65	+/* The operands table is an array of struct tic80_operand. */
	66	+
	67	+struct tic80_operand
	68	+{
	69	+ /* The number of bits in the operand. */
	70	+
	71	+ int bits;
	72	+
	73	+ /* How far the operand is left shifted in the instruction. */
	74	+
	75	+ int shift;
	76	+
	77	+ /* Insertion function. This is used by the assembler. To insert an
	78	+ operand value into an instruction, check this field.
	79	+
	80	+ If it is NULL, execute
	81	+ i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	82	+ (i is the instruction which we are filling in, o is a pointer to
	83	+ this structure, and op is the opcode value; this assumes twos
	84	+ complement arithmetic).
	85	+
	86	+ If this field is not NULL, then simply call it with the
	87	+ instruction and the operand value. It will return the new value
	88	+ of the instruction. If the ERRMSG argument is not NULL, then if
	89	+ the operand value is illegal, *ERRMSG will be set to a warning
	90	+ string (the operand will be inserted in any case). If the
	91	+ operand value is legal, *ERRMSG will be unchanged (most operands
	92	+ can accept any value). */
	93	+
	94	+ unsigned long (*insert)
	95	+ (unsigned long instruction, long op, const char **errmsg);
	96	+
	97	+ /* Extraction function. This is used by the disassembler. To
	98	+ extract this operand type from an instruction, check this field.
	99	+
	100	+ If it is NULL, compute
	101	+ op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	102	+ if ((o->flags & TIC80_OPERAND_SIGNED) != 0
	103	+ && (op & (1 << (o->bits - 1))) != 0)
	104	+ op -= 1 << o->bits;
	105	+ (i is the instruction, o is a pointer to this structure, and op
	106	+ is the result; this assumes twos complement arithmetic).
	107	+
	108	+ If this field is not NULL, then simply call it with the
	109	+ instruction value. It will return the value of the operand. If
	110	+ the INVALID argument is not NULL, *INVALID will be set to
	111	+ non-zero if this operand type can not actually be extracted from
	112	+ this operand (i.e., the instruction does not match). If the
	113	+ operand is valid, INVALID will not be changed. /
	114	+
	115	+ long (extract) (unsigned long instruction, int invalid);
	116	+
	117	+ /* One bit syntax flags. */
	118	+
	119	+ unsigned long flags;
	120	+};
	121	+
	122	+/* Elements in the table are retrieved by indexing with values from
	123	+ the operands field of the tic80_opcodes table. */
	124	+
	125	+extern const struct tic80_operand tic80_operands[];
	126	+
	127	+
	128	+/* Values defined for the flags field of a struct tic80_operand.
	129	+
	130	+ Note that flags for all predefined symbols, such as the general purpose
	131	+ registers (ex: r10), control registers (ex: FPST), condition codes (ex:
	132	+ eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
	133	+ or'd into an int where the lower bits contain the actual numeric value
	134	+ that correponds to this predefined symbol. This way a single int can
	135	+ contain both the value of the symbol and it's type.
	136	+ */
	137	+
	138	+/* This operand must be an even register number. Floating point numbers
	139	+ for example are stored in even/odd register pairs. */
	140	+
	141	+#define TIC80_OPERAND_EVEN (1 << 0)
	142	+
	143	+/* This operand must be an odd register number and must be one greater than
	144	+ the register number of the previous operand. I.E. the second register in
	145	+ an even/odd register pair. */
	146	+
	147	+#define TIC80_OPERAND_ODD (1 << 1)
	148	+
	149	+/* This operand takes signed values. */
	150	+
	151	+#define TIC80_OPERAND_SIGNED (1 << 2)
	152	+
	153	+/* This operand may be either a predefined constant name or a numeric value.
	154	+ An example would be a condition code like "eq0.b" which has the numeric
	155	+ value 0x2. */
	156	+
	157	+#define TIC80_OPERAND_NUM (1 << 3)
	158	+
	159	+/* This operand should be wrapped in parentheses rather than separated
	160	+ from the previous one by a comma. This is used for various
	161	+ instructions, like the load and store instructions, which want
	162	+ their operands to look like "displacement(reg)" */
	163	+
	164	+#define TIC80_OPERAND_PARENS (1 << 4)
	165	+
	166	+/* This operand is a PC relative branch offset. The disassembler prints
	167	+ these symbolically if possible. Note that the offsets are taken as word
	168	+ offsets. */
	169	+
	170	+#define TIC80_OPERAND_PCREL (1 << 5)
	171	+
	172	+/* This flag is a hint to the disassembler for using hex as the prefered
	173	+ printing format, even for small positive or negative immediate values.
	174	+ Normally values in the range -999 to 999 are printed as signed decimal
	175	+ values and other values are printed in hex. */
	176	+
	177	+#define TIC80_OPERAND_BITFIELD (1 << 6)
	178	+
	179	+/* This operand may have a ":m" modifier specified by bit 17 in a short
	180	+ immediate form instruction. */
	181	+
	182	+#define TIC80_OPERAND_M_SI (1 << 7)
	183	+
	184	+/* This operand may have a ":m" modifier specified by bit 15 in a long
	185	+ immediate or register form instruction. */
	186	+
	187	+#define TIC80_OPERAND_M_LI (1 << 8)
	188	+
	189	+/* This operand may have a ":s" modifier specified in bit 11 in a long
	190	+ immediate or register form instruction. */
	191	+
	192	+#define TIC80_OPERAND_SCALED (1 << 9)
	193	+
	194	+/* This operand is a floating point value */
	195	+
	196	+#define TIC80_OPERAND_FLOAT (1 << 10)
	197	+
	198	+/* This operand is an byte offset from a base relocation. The lower
	199	+ two bits of the final relocated address are ignored when the value is
	200	+ written to the program counter. */
	201	+
	202	+#define TIC80_OPERAND_BASEREL (1 << 11)
	203	+
	204	+/* This operand is an "endmask" field for a shift instruction.
	205	+ It is treated special in that it can have values of 0-32,
	206	+ where 0 and 32 result in the same instruction. The assembler
	207	+ must be able to accept both endmask values. This disassembler
	208	+ has no way of knowing from the instruction which value was
	209	+ given at assembly time, so it just uses '0'. */
	210	+
	211	+#define TIC80_OPERAND_ENDMASK (1 << 12)
	212	+
	213	+/* This operand is one of the 32 general purpose registers.
	214	+ The disassembler prints these with a leading 'r'. */
	215	+
	216	+#define TIC80_OPERAND_GPR (1 << 27)
	217	+
	218	+/* This operand is a floating point accumulator register.
	219	+ The disassembler prints these with a leading 'a'. */
	220	+
	221	+#define TIC80_OPERAND_FPA ( 1 << 28)
	222	+
	223	+/* This operand is a control register number, either numeric or
	224	+ symbolic (like "EIF", "EPC", etc).
	225	+ The disassembler prints these symbolically. */
	226	+
	227	+#define TIC80_OPERAND_CR (1 << 29)
	228	+
	229	+/* This operand is a condition code, either numeric or
	230	+ symbolic (like "eq0.b", "ne0.w", etc).
	231	+ The disassembler prints these symbolically. */
	232	+
	233	+#define TIC80_OPERAND_CC (1 << 30)
	234	+
	235	+/* This operand is a bit number, either numeric or
	236	+ symbolic (like "eq.b", "or.f", etc).
	237	+ The disassembler prints these symbolically.
	238	+ Note that they appear in the instruction in 1's complement relative
	239	+ to the values given in the manual. */
	240	+
	241	+#define TIC80_OPERAND_BITNUM (1 << 31)
	242	+
	243	+/* This mask is used to strip operand bits from an int that contains
	244	+ both operand bits and a numeric value in the lsbs. */
	245	+
	246	+#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR \| TIC80_OPERAND_FPA \| TIC80_OPERAND_CR \| TIC80_OPERAND_CC \| TIC80_OPERAND_BITNUM)
	247	+
	248	+
	249	+/* Flag bits for the struct tic80_opcode flags field. */
	250	+
	251	+#define TIC80_VECTOR 01 /* Is a vector instruction */
	252	+#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */
	253	+
	254	+
	255	+/* The opcodes library contains a table that allows translation from predefined
	256	+ symbol names to numeric values, and vice versa. */
	257	+
	258	+/* Structure to hold information about predefined symbols. */
	259	+
	260	+struct predefined_symbol
	261	+{
	262	+ char name; / name to recognize */
	263	+ int value;
	264	+};
	265	+
	266	+#define PDS_NAME(pdsp) ((pdsp) -> name)
	267	+#define PDS_VALUE(pdsp) ((pdsp) -> value)
	268	+
	269	+/* Translation array. */
	270	+extern const struct predefined_symbol tic80_predefined_symbols[];
	271	+/* How many members in the array. */
	272	+extern const int tic80_num_predefined_symbols;
	273	+
	274	+/* Translate value to symbolic name. */
	275	+const char *tic80_value_to_symbol (int val, int class);
	276	+
	277	+/* Translate symbolic name to value. */
	278	+int tic80_symbol_to_value (char *name, int class);
	279	+
	280	+const struct predefined_symbol *tic80_next_predefined_symbol
	281	+ (const struct predefined_symbol *);
	282	+
	283	+#endif /* TIC80_H */

binutils/include/opcode/tilegx.h+1−1

@@ -1,6 +1,6 @@
1	1	/* TILE-Gx opcode information.
2	2	*
3		− * Copyright (C) 2011-2020 Free Software Foundation, Inc.
	3	+ * Copyright (C) 2011-2018 Free Software Foundation, Inc.
4	4	*
5	5	* This program is free software; you can redistribute it and/or modify
6	6	* it under the terms of the GNU General Public License as published by

binutils/include/opcode/tilepro.h+4−2

@@ -1,6 +1,6 @@
1	1	/* TILEPro opcode information.
2	2	*
3		− * Copyright (C) 2011-2020 Free Software Foundation, Inc.
	3	+ * Copyright (C) 2011-2018 Free Software Foundation, Inc.
4	4	*
5	5	* This program is free software; you can redistribute it and/or modify
6	6	* it under the terms of the GNU General Public License as published by
@@ -1412,7 +1412,6 @@ typedef enum · 1405 unmodified lines
1412	1412	TILEPRO_PIPELINE_Y0,
1413	1413	TILEPRO_PIPELINE_Y1,
1414	1414	TILEPRO_PIPELINE_Y2,
1415		− TILEPRO_NUM_PIPELINE_ENCODINGS
1416	1415	} tilepro_pipeline;
1417	1416
1418	1417	#define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1)
@@ -1433,6 +1432,9 @@ enum · 14 unmodified lines
1433	1432	/* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1434	1433	TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1435	1434
	1435	+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
	1436	+ TILEPRO_NUM_PIPELINE_ENCODINGS = 5,
	1437	+
1436	1438	/* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */
1437	1439	TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1438	1440

binutils/include/opcode/v850.h+2−2

@@ -1,5 +1,5 @@
1	1	/* v850.h -- Header file for NEC V850 opcode table
2		− Copyright (C) 1996-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
3	3	Written by J.T. Conklin, Cygnus Support
4	4
5	5	This file is part of GDB, GAS, and the GNU binutils.
@@ -133,7 +133,7 @@ struct v850_operand · 127 unmodified lines
133	133	operand value is legal, *ERRMSG will be unchanged (most operands
134	134	can accept any value). */
135	135	unsigned long (* insert)
136		− (unsigned long instruction, unsigned long op, const char ** errmsg);
	136	+ (unsigned long instruction, long op, const char ** errmsg);
137	137
138	138	/* Extraction function. This is used by the disassembler. To
139	139	extract this operand type from an instruction, check this field.

binutils/include/opcode/vax.h+1−1

@@ -1,5 +1,5 @@
1	1	/* Vax opcde list.
2		− Copyright (C) 1989-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 1989-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GDB and GAS.
5	5

binutils/include/opcode/visium.h+1−1

@@ -1,6 +1,6 @@
1	1	/* Opcode table header for Visium.
2	2
3		− Copyright (C) 2003-2020 Free Software Foundation, Inc.
	3	+ Copyright (C) 2003-2018 Free Software Foundation, Inc.
4	4
5	5	This file is part of GDB, GAS, and GNU binutils.
6	6

binutils/include/opcode/wasm.h+1−1

@@ -1,5 +1,5 @@
1	1	/* WebAssembly assembler/disassembler support.
2		− Copyright (C) 2017-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2017-2018 Free Software Foundation, Inc.
3	3
4	4	This file is part of GAS, the GNU assembler.
5	5

binutils/include/opcode/xgate.h+1−1

@@ -1,5 +1,5 @@
1	1	/* xgate.h -- Freescale XGATE opcode list
2		− Copyright (C) 2010-2020 Free Software Foundation, Inc.
	2	+ Copyright (C) 2010-2018 Free Software Foundation, Inc.
3	3	Written by Sean Keys (skeys@ipdatasys.com)
4	4
5	5	This file is part of the GNU opcodes library.

Revert "switch from binutils only to binutils-gdb, tag gdb-10.1-release"

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