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arm-asm: Add cdp

Also add p0...p15 (coprocessors), c0...c15 (coprocessor register aliases)

Danny Milosavljevic committed 5 years ago

Commit 036a7fe1 parent 593bed93 files · +118 −0Browse files

Unified · Split

3 files
  1. arm-asm.c +77 −0
  2. arm-tok.h +40 −0
  3. tests/arm-asm-testsuite.sh +1 −0
arm-asm.c+77−0
@@ -165,6 +165,26 @@ static void asm_emit_opcode(int token, uint32_t opcode) { · 164 unmodified lines
165 gen_le32((condition_code_of_token(token) << 28) | opcode);165 gen_le32((condition_code_of_token(token) << 28) | opcode);
166}166}
167 167
168static void asm_emit_coprocessor_opcode(uint32_t high_nibble, uint8_t cp_number, uint8_t cp_opcode, uint8_t cp_destination_register, uint8_t cp_n_operand_register, uint8_t cp_m_operand_register, uint8_t cp_opcode2, int inter_processor_transfer)
169{
170 uint32_t opcode = 0xe000000;
171 if (inter_processor_transfer)
172 opcode |= 1 << 4;
173 //assert(cp_opcode < 16);
174 opcode |= cp_opcode << 20;
175 //assert(cp_n_operand_register < 16);
176 opcode |= cp_n_operand_register << 16;
177 //assert(cp_destination_register < 16);
178 opcode |= cp_destination_register << 12;
179 //assert(cp_number < 16);
180 opcode |= cp_number << 8;
181 //assert(cp_information < 8);
182 opcode |= cp_opcode2 << 5;
183 //assert(cp_m_operand_register < 16);
184 opcode |= cp_m_operand_register;
185 gen_le32((high_nibble << 28) | opcode);
186}
187
168static void asm_nullary_opcode(int token)188static void asm_nullary_opcode(int token)
169{189{
170 switch (ARM_INSTRUCTION_GROUP(token)) {190 switch (ARM_INSTRUCTION_GROUP(token)) {
@@ -309,6 +329,60 @@ static void asm_binary_opcode(TCCState *s1, int token) · 138 unmodified lines
309 }329 }
310}330}
311 331
332static void asm_coprocessor_opcode(TCCState *s1, int token) {
333 uint8_t coprocessor;
334 Operand opcode1;
335 Operand opcode2;
336 uint8_t registers[3];
337 unsigned int i;
338
339 if (tok >= TOK_ASM_p0 && tok <= TOK_ASM_p15) {
340 coprocessor = tok - TOK_ASM_p0;
341 next();
342 } else {
343 expect("'p<number>'");
344 return;
345 }
346
347 if (tok == ',')
348 next();
349 else
350 expect("','");
351
352 parse_operand(s1, &opcode1);
353 if (opcode1.type != OP_IM8 || opcode1.e.v > 15) {
354 tcc_error("opcode1 of instruction '%s' must be an immediate value between 0 and 15", get_tok_str(token, NULL));
355 return;
356 }
357
358 for (i = 0; i < 3; ++i) {
359 if (tok == ',')
360 next();
361 else
362 expect("','");
363 if (tok >= TOK_ASM_c0 && tok <= TOK_ASM_c15) {
364 registers[i] = tok - TOK_ASM_c0;
365 next();
366 } else {
367 expect("'c<number>");
368 return;
369 }
370 }
371 if (tok == ',') {
372 next();
373 parse_operand(s1, &opcode2);
374 } else {
375 opcode2.type = OP_IM8;
376 opcode2.e.v = 0;
377 }
378 if (opcode2.type != OP_IM8 || opcode2.e.v > 15) {
379 tcc_error("opcode2 of instruction '%s' must be an immediate value between 0 and 15", get_tok_str(token, NULL));
380 return;
381 }
382
383 asm_emit_coprocessor_opcode(condition_code_of_token(token), coprocessor, opcode1.e.v, registers[0], registers[1], registers[2], opcode2.e.v, 0);
384}
385
312/* data processing and single data transfer instructions only */386/* data processing and single data transfer instructions only */
313#define ENCODE_RN(register_index) ((register_index) << 16)387#define ENCODE_RN(register_index) ((register_index) << 16)
314#define ENCODE_RD(register_index) ((register_index) << 12)388#define ENCODE_RD(register_index) ((register_index) << 12)
@@ -1468,6 +1542,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int token) · 1153 unmodified lines
1468 case TOK_ASM_umlaleq:1542 case TOK_ASM_umlaleq:
1469 case TOK_ASM_umlalseq:1543 case TOK_ASM_umlalseq:
1470 return asm_long_multiplication_opcode(s1, token);1544 return asm_long_multiplication_opcode(s1, token);
1545
1546 case TOK_ASM_cdpeq:
1547 return asm_coprocessor_opcode(s1, token);
1471 default:1548 default:
1472 expect("known instruction");1549 expect("known instruction");
1473 }1550 }
arm-tok.h+40−0
@@ -28,6 +28,44 @@ · 27 unmodified lines
28 DEF_ASM(lr) /* alias for r14 */28 DEF_ASM(lr) /* alias for r14 */
29 DEF_ASM(pc) /* alias for r15 */29 DEF_ASM(pc) /* alias for r15 */
30 30
31 /* coprocessors */
32
33 DEF_ASM(p0)
34 DEF_ASM(p1)
35 DEF_ASM(p2)
36 DEF_ASM(p3)
37 DEF_ASM(p4)
38 DEF_ASM(p5)
39 DEF_ASM(p6)
40 DEF_ASM(p7)
41 DEF_ASM(p8)
42 DEF_ASM(p9)
43 DEF_ASM(p10)
44 DEF_ASM(p11)
45 DEF_ASM(p12)
46 DEF_ASM(p13)
47 DEF_ASM(p14)
48 DEF_ASM(p15)
49
50 /* coprocessor registers */
51
52 DEF_ASM(c0)
53 DEF_ASM(c1)
54 DEF_ASM(c2)
55 DEF_ASM(c3)
56 DEF_ASM(c4)
57 DEF_ASM(c5)
58 DEF_ASM(c6)
59 DEF_ASM(c7)
60 DEF_ASM(c8)
61 DEF_ASM(c9)
62 DEF_ASM(c10)
63 DEF_ASM(c11)
64 DEF_ASM(c12)
65 DEF_ASM(c13)
66 DEF_ASM(c14)
67 DEF_ASM(c15)
68
31 /* data processing directives */69 /* data processing directives */
32 70
33 DEF_ASM(asl)71 DEF_ASM(asl)
@@ -170,3 +208,5 @@ · 136 unmodified lines
170 DEF_ASM_CONDED(rors)208 DEF_ASM_CONDED(rors)
171 DEF_ASM_CONDED(rrx)209 DEF_ASM_CONDED(rrx)
172 DEF_ASM_CONDED(rrxs)210 DEF_ASM_CONDED(rrxs)
211
212 DEF_ASM_CONDED(cdp)
tests/arm-asm-testsuite.sh+1−0
@@ -89,6 +89,7 @@ do · 88 unmodified lines
89 "r4, #0x0201" \89 "r4, #0x0201" \
90 "r4, #0xFFFFFF00" \90 "r4, #0xFFFFFF00" \
91 "r2, #-4" \91 "r2, #-4" \
92 "p10, #7, c2, c0, c1, #4" \
92 "#4" \93 "#4" \
93 "#-4" \94 "#-4" \
94 ""95 ""

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