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arm-asm: Add vmsr, vmrs

Danny Milosavljevic committed 5 years ago

Commit 25628cf1 parent 1c9d9993 files · +101 −5Browse files

Unified · Split

3 files
  1. arm-asm.c +81 −4
  2. arm-tok.h +12 −0
  3. tests/arm-asm-testsuite.sh +8 −1
arm-asm.c+81−4
@@ -77,6 +77,20 @@ static int asm_parse_vfp_regvar(int t, int double_precision) · 76 unmodified lines
7777 return -1;
7878 }
7979
80+static int asm_parse_vfp_status_regvar(int t)
81+{
82+ switch (t) {
83+ case TOK_ASM_fpsid:
84+ return 0;
85+ case TOK_ASM_fpscr:
86+ return 1;
87+ case TOK_ASM_fpexc:
88+ return 8;
89+ default:
90+ return -1;
91+ }
92+}
93+
8094 /* Parse a text containing operand and store the result in OP */
8195 static void parse_operand(TCCState *s1, Operand *op)
8296 {
@@ -1915,10 +1929,6 @@ static void asm_floating_point_data_processing_opcode(TCCState *s1, int token) { · 1832 unmodified lines
19151929 VMOV Rd, Dn[0]
19161930 VMOV Dn[1], Rd
19171931 VMOV Rd, Dn[1]
1918−
1919− VMSR <sysreg>, Rd
1920− VMRS Rd, <sysreg>
1921− VMRS APSR_nzcv, FPSCR
19221932 */
19231933
19241934 switch (ARM_INSTRUCTION_GROUP(token)) {
@@ -2110,6 +2120,68 @@ static void asm_floating_point_data_processing_opcode(TCCState *s1, int token) { · 185 unmodified lines
21102120
21112121 asm_emit_coprocessor_opcode(condition_code_of_token(token), coprocessor, opcode1, ops[0].reg, (ops[1].type == OP_IM8) ? ops[1].e.v : ops[1].reg, (ops[2].type == OP_IM8) ? ops[2].e.v : ops[2].reg, opcode2, 0);
21122122 }
2123+
2124+static void asm_floating_point_status_register_opcode(TCCState* s1, int token)
2125+{
2126+ uint8_t coprocessor = CP_SINGLE_PRECISION_FLOAT;
2127+ uint8_t opcode;
2128+ int vfp_sys_reg = -1;
2129+ Operand arm_operand;
2130+ switch (ARM_INSTRUCTION_GROUP(token)) {
2131+ case TOK_ASM_vmrseq:
2132+ opcode = 0xf;
2133+ if (tok == TOK_ASM_apsr_nzcv) {
2134+ arm_operand.type = OP_REG32;
2135+ arm_operand.reg = 15; // not PC
2136+ next(); // skip apsr_nzcv
2137+ } else {
2138+ parse_operand(s1, &arm_operand);
2139+ if (arm_operand.type == OP_REG32 && arm_operand.reg == 15) {
2140+ tcc_error("'%s' does not support 'pc' as operand", get_tok_str(token, NULL));
2141+ return;
2142+ }
2143+ }
2144+
2145+ if (tok != ',')
2146+ expect("','");
2147+ else
2148+ next(); // skip ','
2149+ vfp_sys_reg = asm_parse_vfp_status_regvar(tok);
2150+ next(); // skip vfp sys reg
2151+ if (arm_operand.type == OP_REG32 && arm_operand.reg == 15 && vfp_sys_reg != 1) {
2152+ tcc_error("'%s' only supports the variant 'vmrs apsr_nzcv, fpscr' here", get_tok_str(token, NULL));
2153+ return;
2154+ }
2155+ break;
2156+ case TOK_ASM_vmsreq:
2157+ opcode = 0xe;
2158+ vfp_sys_reg = asm_parse_vfp_status_regvar(tok);
2159+ next(); // skip vfp sys reg
2160+ if (tok != ',')
2161+ expect("','");
2162+ else
2163+ next(); // skip ','
2164+ parse_operand(s1, &arm_operand);
2165+ if (arm_operand.type == OP_REG32 && arm_operand.reg == 15) {
2166+ tcc_error("'%s' does not support 'pc' as operand", get_tok_str(token, NULL));
2167+ return;
2168+ }
2169+ break;
2170+ default:
2171+ expect("floating point status register instruction");
2172+ return;
2173+ }
2174+ if (vfp_sys_reg == -1) {
2175+ expect("VFP system register");
2176+ return;
2177+ }
2178+ if (arm_operand.type != OP_REG32) {
2179+ expect("ARM register");
2180+ return;
2181+ }
2182+ asm_emit_coprocessor_opcode(condition_code_of_token(token), coprocessor, opcode, arm_operand.reg, vfp_sys_reg, 0x10, 0, 0);
2183+}
2184+
21132185 #endif
21142186
21152187 static void asm_misc_single_data_transfer_opcode(TCCState *s1, int token)
@@ -2518,6 +2590,11 @@ ST_FUNC void asm_opcode(TCCState *s1, int token) · 402 unmodified lines
25182590 case TOK_ASM_vstmdbeq:
25192591 asm_floating_point_block_data_transfer_opcode(s1, token);
25202592 return;
2593+
2594+ case TOK_ASM_vmsreq:
2595+ case TOK_ASM_vmrseq:
2596+ asm_floating_point_status_register_opcode(s1, token);
2597+ return;
25212598 #endif
25222599
25232600 default:
arm-tok.h+12−0
@@ -120,6 +120,16 @@ · 119 unmodified lines
120120 DEF_ASM(d14)
121121 DEF_ASM(d15)
122122
123+ /* VFP status registers */
124+
125+ DEF_ASM(fpsid)
126+ DEF_ASM(fpscr)
127+ DEF_ASM(fpexc)
128+
129+ /* VFP magical ARM register */
130+
131+ DEF_ASM(apsr_nzcv)
132+
123133 /* data processing directives */
124134
125135 DEF_ASM(asl)
@@ -333,3 +343,5 @@ · 207 unmodified lines
333343 DEF_ASM_CONDED(vstm)
334344 DEF_ASM_CONDED(vstmia)
335345 DEF_ASM_CONDED(vstmdb)
346+ DEF_ASM_CONDED(vmsr)
347+ DEF_ASM_CONDED(vmrs)
tests/arm-asm-testsuite.sh+8−1
@@ -14,7 +14,7 @@ cat ../arm-tok.h | \ · 13 unmodified lines
1414 sed -e 's;^[ ]*DEF_ASM_CONDED_VFP_F32_F64[^(]*(\(.*\)).*$; DEF_ASM_CONDED(\1.f32)\
1515 DEF_ASM_CONDED(\1.f64);g' | \
1616 sed -e 's;^[ ]*DEF_ASM[^(]*(\(.*\)).*$;\1;g' | \
17− egrep -v '^((r|c|p|s|d)[0-9]+|fp|ip|sp|lr|pc|asl)$' | while read s
17+ egrep -v '^((r|c|p|s|d)[0-9]+|fp|ip|sp|lr|pc|asl|apsr_nzcv|fpsid|fpscr|fpexc)$' | while read s
1818 do
1919 as_opts=""
2020 if [ "${s#v}" != "${s}" ]
@@ -155,6 +155,13 @@ do · 134 unmodified lines
155155 "d1, r2, r3" \
156156 "s1, r2" \
157157 "r2, s1" \
158+ "r2, fpexc" \
159+ "r2, fpscr" \
160+ "r2, fpsid" \
161+ "apsr_nzcv, fpscr" \
162+ "fpexc, r2" \
163+ "fpscr, r2" \
164+ "fpsid, r2" \
158165 ""
159166 do
160167 #echo ".syntax unified" > a.s

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