Unified · Split
| @@ -49,9 +49,70 @@ ST_FUNC void gen_expr32(ExprValue *pe) · 48 unmodified lines | ||
| 49 | 49 | gen_le32(pe->v); |
| 50 | 50 | } |
| 51 | 51 | |
| 52 | −ST_FUNC void asm_opcode(TCCState *s1, int opcode) | |
| 52 | +static void asm_emit_opcode(uint32_t opcode) { | |
| 53 | + gen_le32(opcode); | |
| 54 | +} | |
| 55 | + | |
| 56 | +static void asm_nullary_opcode(TCCState *s1, int token) | |
| 53 | 57 | { |
| 54 | − tcc_error("RISCV64 asm not implemented."); | |
| 58 | + switch (token) { | |
| 59 | + // Sync instructions | |
| 60 | + | |
| 61 | + case TOK_ASM_fence: // I | |
| 62 | + asm_emit_opcode((0x3 << 2) | 3 | (0 << 12)); | |
| 63 | + return; | |
| 64 | + case TOK_ASM_fence_i: // I | |
| 65 | + asm_emit_opcode((0x3 << 2) | 3| (1 << 12)); | |
| 66 | + return; | |
| 67 | + | |
| 68 | + // System calls | |
| 69 | + | |
| 70 | + case TOK_ASM_scall: // I (pseudo) | |
| 71 | + asm_emit_opcode((0x1C << 2) | 3 | (0 << 12)); | |
| 72 | + return; | |
| 73 | + case TOK_ASM_sbreak: // I (pseudo) | |
| 74 | + asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20)); | |
| 75 | + return; | |
| 76 | + | |
| 77 | + // Privileged Instructions | |
| 78 | + | |
| 79 | + case TOK_ASM_ecall: | |
| 80 | + asm_emit_opcode((0x1C << 2) | 3 | (0 << 20)); | |
| 81 | + return; | |
| 82 | + case TOK_ASM_ebreak: | |
| 83 | + asm_emit_opcode((0x1C << 2) | 3 | (1 << 20)); | |
| 84 | + return; | |
| 85 | + | |
| 86 | + // Other | |
| 87 | + | |
| 88 | + case TOK_ASM_wfi: | |
| 89 | + asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20)); | |
| 90 | + return; | |
| 91 | + | |
| 92 | + default: | |
| 93 | + expect("nullary instruction"); | |
| 94 | + } | |
| 95 | +} | |
| 96 | + | |
| 97 | +ST_FUNC void asm_opcode(TCCState *s1, int token) | |
| 98 | +{ | |
| 99 | + switch (token) { | |
| 100 | + case TOK_ASM_fence: | |
| 101 | + case TOK_ASM_fence_i: | |
| 102 | + case TOK_ASM_scall: | |
| 103 | + case TOK_ASM_sbreak: | |
| 104 | + case TOK_ASM_ecall: | |
| 105 | + case TOK_ASM_ebreak: | |
| 106 | + case TOK_ASM_mrts: | |
| 107 | + case TOK_ASM_mrth: | |
| 108 | + case TOK_ASM_hrts: | |
| 109 | + case TOK_ASM_wfi: | |
| 110 | + asm_nullary_opcode(s1, token); | |
| 111 | + return; | |
| 112 | + | |
| 113 | + default: | |
| 114 | + expect("known instruction"); | |
| 115 | + } | |
| 55 | 116 | } |
| 56 | 117 | |
| 57 | 118 | ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier) |
| @@ -0,0 +1,104 @@ | ||
| 1 | +/* ------------------------------------------------------------------ */ | |
| 2 | +/* WARNING: relative order of tokens is important. */ | |
| 3 | + | |
| 4 | +// See https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf | |
| 5 | + | |
| 6 | +/* register */ | |
| 7 | + | |
| 8 | + DEF_ASM(x0) | |
| 9 | + DEF_ASM(x1) | |
| 10 | + DEF_ASM(x2) | |
| 11 | + DEF_ASM(x3) | |
| 12 | + DEF_ASM(x4) | |
| 13 | + DEF_ASM(x5) | |
| 14 | + DEF_ASM(x6) | |
| 15 | + DEF_ASM(x7) | |
| 16 | + DEF_ASM(x8) | |
| 17 | + DEF_ASM(x9) | |
| 18 | + DEF_ASM(x10) | |
| 19 | + DEF_ASM(x11) | |
| 20 | + DEF_ASM(x12) | |
| 21 | + DEF_ASM(x13) | |
| 22 | + DEF_ASM(x14) | |
| 23 | + DEF_ASM(x15) | |
| 24 | + DEF_ASM(x16) | |
| 25 | + DEF_ASM(x17) | |
| 26 | + DEF_ASM(x18) | |
| 27 | + DEF_ASM(x19) | |
| 28 | + DEF_ASM(x20) | |
| 29 | + DEF_ASM(x21) | |
| 30 | + DEF_ASM(x22) | |
| 31 | + DEF_ASM(x23) | |
| 32 | + DEF_ASM(x24) | |
| 33 | + DEF_ASM(x25) | |
| 34 | + DEF_ASM(x26) | |
| 35 | + DEF_ASM(x27) | |
| 36 | + DEF_ASM(x28) | |
| 37 | + DEF_ASM(x29) | |
| 38 | + DEF_ASM(x30) | |
| 39 | + DEF_ASM(x31) | |
| 40 | + | |
| 41 | +/* register macros */ | |
| 42 | + | |
| 43 | + DEF_ASM(zero) | |
| 44 | +/* | |
| 45 | + DEF_ASM(ra) | |
| 46 | + DEF_ASM(sp) | |
| 47 | + DEF_ASM(gp) | |
| 48 | + DEF_ASM(tp) | |
| 49 | + DEF_ASM(t0) | |
| 50 | + DEF_ASM(t1) | |
| 51 | + DEF_ASM(t2) | |
| 52 | + DEF_ASM(fp) | |
| 53 | + DEF_ASM(s1) | |
| 54 | + DEF_ASM(a0) | |
| 55 | + DEF_ASM(a1) | |
| 56 | + DEF_ASM(a2) | |
| 57 | + DEF_ASM(a3) | |
| 58 | + DEF_ASM(a4) | |
| 59 | + DEF_ASM(a5) | |
| 60 | + DEF_ASM(a6) | |
| 61 | + DEF_ASM(a7) | |
| 62 | + DEF_ASM(s2) | |
| 63 | + DEF_ASM(s3) | |
| 64 | + DEF_ASM(s4) | |
| 65 | + DEF_ASM(s5) | |
| 66 | + DEF_ASM(s6) | |
| 67 | + DEF_ASM(s7) | |
| 68 | + DEF_ASM(s8) | |
| 69 | + DEF_ASM(s9) | |
| 70 | + DEF_ASM(s10) | |
| 71 | + DEF_ASM(s11) | |
| 72 | + DEF_ASM(t3) | |
| 73 | + DEF_ASM(t4) | |
| 74 | + DEF_ASM(t5) | |
| 75 | + DEF_ASM(t6) | |
| 76 | + | |
| 77 | + DEF_ASM(s0) // = x8 | |
| 78 | +*/ | |
| 79 | + | |
| 80 | + DEF_ASM(pc) | |
| 81 | + | |
| 82 | +#define DEF_ASM_WITH_SUFFIX(x, y) \ | |
| 83 | + DEF(TOK_ASM_ ## x ## _ ## y, #x #y) | |
| 84 | + | |
| 85 | +/* Sync */ | |
| 86 | + | |
| 87 | + DEF_ASM(fence) | |
| 88 | + DEF_ASM_WITH_SUFFIX(fence, i) | |
| 89 | + | |
| 90 | +/* System call */ | |
| 91 | + | |
| 92 | + DEF_ASM(scall) | |
| 93 | + DEF_ASM(sbreak) | |
| 94 | + | |
| 95 | +/* Privileged Instructions */ | |
| 96 | + | |
| 97 | + DEF_ASM(ecall) | |
| 98 | + DEF_ASM(ebreak) | |
| 99 | + | |
| 100 | + DEF_ASM(mrts) | |
| 101 | + DEF_ASM(mrth) | |
| 102 | + DEF_ASM(hrts) | |
| 103 | + DEF_ASM(wfi) | |
| 104 | + | |
| @@ -391,3 +391,6 @@ · 390 unmodified lines | ||
| 391 | 391 | #if defined TCC_TARGET_ARM || defined TCC_TARGET_ARM64 |
| 392 | 392 | #include "arm-tok.h" |
| 393 | 393 | #endif |
| 394 | +#if defined TCC_TARGET_RISCV64 | |
| 395 | +#include "riscv64-tok.h" | |
| 396 | +#endif | |