History

riscv: Replace RR insn emitter with specific one

instead of using o() directly. Makes the code a little easier to read.

Michael Matz committed 7 years ago

Commit 48ba22c1 parent d5bb4071 file · +30 −24Browse files

Unified · Split

riscv64-gen.c+30−24
@@ -101,6 +101,12 @@ static void EIu(uint32_t opcode, uint32_t func3, · 100 unmodified lines
101 o(opcode | (func3 << 12) | (rd << 7) | (rs1 << 15) | (imm << 20));101 o(opcode | (func3 << 12) | (rd << 7) | (rs1 << 15) | (imm << 20));
102}102}
103 103
104static void ER(uint32_t opcode, uint32_t func3,
105 uint32_t rd, uint32_t rs1, uint32_t rs2, uint32_t func7)
106{
107 o(opcode | func3 << 12 | rd << 7 | rs1 << 15 | rs2 << 20 | func7 << 25);
108}
109
104static void EI(uint32_t opcode, uint32_t func3,110static void EI(uint32_t opcode, uint32_t func3,
105 uint32_t rd, uint32_t rs1, uint32_t imm)111 uint32_t rd, uint32_t rs1, uint32_t imm)
106{112{
@@ -175,7 +181,7 @@ static int load_symofs(int r, SValue *sv, int forstore) · 68 unmodified lines
175 if (((unsigned)fc + (1 << 11)) >> 12) {181 if (((unsigned)fc + (1 << 11)) >> 12) {
176 rr = is_ireg(r) ? ireg(r) : 5; // t0182 rr = is_ireg(r) ? ireg(r) : 5; // t0
177 o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)); //lui RR, upper(fc)183 o(0x37 | (rr << 7) | ((0x800 + fc) & 0xfffff000)); //lui RR, upper(fc)
178 o(0x33 | (rr << 7) | (rr << 15) | (8 << 20)); // add RR, RR, s0184 ER(0x33, 0, rr, rr, 8, 0); // add RR, RR, s0
179 sv->c.i = fc << 20 >> 20;185 sv->c.i = fc << 20 >> 20;
180 }186 }
181 } else187 } else
@@ -268,7 +274,7 @@ ST_FUNC void load(int r, SValue *sv) · 86 unmodified lines
268 } else if (v < VT_CONST) { /* reg-reg */274 } else if (v < VT_CONST) { /* reg-reg */
269 //assert(!fc); XXX support offseted regs275 //assert(!fc); XXX support offseted regs
270 if (is_freg(r) && is_freg(v))276 if (is_freg(r) && is_freg(v))
271 o(0x53 | (rr << 7) | (freg(v) << 15) | (freg(v) << 20) | ((bt == VT_DOUBLE ? 0x11 : 0x10) << 25)); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V277 ER(0x53, 0, rr, freg(v), freg(v), bt == VT_DOUBLE ? 0x11 : 0x10); //fsgnj.[sd] RR, V, V == fmv.[sd] RR, V
272 else if (is_ireg(r) && is_ireg(v))278 else if (is_ireg(r) && is_ireg(v))
273 EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V279 EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
274 else {280 else {
@@ -696,7 +702,7 @@ ST_FUNC void gfunc_epilog(void) · 421 unmodified lines
696 d = 16;702 d = 16;
697 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)703 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
698 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)704 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
699 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20)); //add sp, sp, t0705 ER(0x33, 0, 2, 2, 5, 0); // add sp, sp, t0
700 }706 }
701 EI(0x03, 3, 1, 2, d - 8 - num_va_regs * 8); // ld ra, v-8(sp)707 EI(0x03, 3, 1, 2, d - 8 - num_va_regs * 8); // ld ra, v-8(sp)
702 EI(0x03, 3, 8, 2, d - 16 - num_va_regs * 8); // ld s0, v-16(sp)708 EI(0x03, 3, 8, 2, d - 16 - num_va_regs * 8); // ld s0, v-16(sp)
@@ -707,7 +713,7 @@ ST_FUNC void gfunc_epilog(void) · 4 unmodified lines
707 EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d713 EI(0x13, 0, 8, 2, d - num_va_regs * 8); // addi s0, sp, d
708 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)714 o(0x37 | (5 << 7) | ((0x800 + (v-16)) & 0xfffff000)); //lui t0, upper(v)
709 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)715 EI(0x13, 0, 5, 5, (v-16) << 20 >> 20); // addi t0, t0, lo(v)
710 o(0x33 | (2 << 7) | (2 << 15) | (5 << 20) | (0x20 << 25)); //sub sp, sp, t0716 ER(0x33, 0, 2, 2, 5, 0x20); // sub sp, sp, t0
711 gjmp_addr(func_sub_sp_offset + 5*4);717 gjmp_addr(func_sub_sp_offset + 5*4);
712 }718 }
713 saved_ind = ind;719 saved_ind = ind;
@@ -849,7 +855,7 @@ static void gen_opil(int op, int ll) · 135 unmodified lines
849 if (fc)855 if (fc)
850 gen_opil('-', ll), a = ireg(vtop++->r);856 gen_opil('-', ll), a = ireg(vtop++->r);
851 if (op == TOK_NE)857 if (op == TOK_NE)
852 o(0x33 | (3 << 12) | (ireg(d) << 7) | (0 << 15) | (a << 20)); // sltu d, x0, a == snez d,a858 ER(0x33, 3, ireg(d), 0, a, 0); //sltu d, x0, a == snez d,a
853 else859 else
854 EI(0x13, 3, ireg(d), a, 1); // sltiu d, a, 1 == seqz d,a860 EI(0x13, 3, ireg(d), a, 1); // sltiu d, a, 1 == seqz d,a
855 --vtop;861 --vtop;
@@ -871,44 +877,44 @@ static void gen_opil(int op, int ll) · 15 unmodified lines
871 tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));877 tcc_error("implement me: %s(%s)", __FUNCTION__, get_tok_str(op, NULL));
872 878
873 case '+':879 case '+':
874 o(0x33 | (d << 7) | (a << 15) | (b << 20)); // add d, a, b880 ER(0x33, 0, d, a, b, 0); // add d, a, b
875 break;881 break;
876 case '-':882 case '-':
877 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); //sub d, a, b883 ER(0x33, 0, d, a, b, 0x20); // sub d, a, b
878 break;884 break;
879 case TOK_SAR:885 case TOK_SAR:
880 o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12) | (1 << 30)); //sra d, a, b886 ER(0x33 | ll, 5, d, a, b, 0x20); // sra d, a, b
881 break;887 break;
882 case TOK_SHR:888 case TOK_SHR:
883 o(0x33 | ll | (d << 7) | (a << 15) | (b << 20) | (5 << 12)); //srl d, a, b889 ER(0x33 | ll, 5, d, a, b, 0); // srl d, a, b
884 break;890 break;
885 case TOK_SHL:891 case TOK_SHL:
886 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (1 << 12)); //sll d, a, b892 ER(0x33, 1, d, a, b, 0); // sll d, a, b
887 break;893 break;
888 case '*':894 case '*':
889 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25)); //mul d, a, b895 ER(0x33, 0, d, a, b, 1); // mul d, a, b
890 break;896 break;
891 case '/':897 case '/':
892 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (4 << 12)); //div d, a, b898 ER(0x33, 4, d, a, b, 1); // div d, a, b
893 break;899 break;
894 case '&':900 case '&':
895 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (7 << 12)); // and d, a, b901 ER(0x33, 7, d, a, b, 0); // and d, a, b
896 break;902 break;
897 case '^':903 case '^':
898 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (4 << 12)); // xor d, a, b904 ER(0x33, 4, d, a, b, 0); // xor d, a, b
899 break;905 break;
900 case '|':906 case '|':
901 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (6 << 12)); // or d, a, b907 ER(0x33, 6, d, a, b, 0); // or d, a, b
902 break;908 break;
903 case '%':909 case '%':
904 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (6 << 12)); //rem d, a, b910 ER(0x33, 6, d, a, b, 1); // rem d, a, b
905 break;911 break;
906 case TOK_UMOD:912 case TOK_UMOD:
907 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (7 << 12)); //remu d, a, b913 ER(0x33, 7, d, a, b, 1); // remu d, a, b
908 break;914 break;
909 case TOK_PDIV:915 case TOK_PDIV:
910 case TOK_UDIV:916 case TOK_UDIV:
911 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x01 << 25) | (5 << 12)); //divu d, a, b917 ER(0x33, 5, d, a, b, 1); // divu d, a, b
912 break;918 break;
913 919
914 case TOK_ULT:920 case TOK_ULT:
@@ -927,7 +933,7 @@ static void gen_opil(int op, int ll) · 12 unmodified lines
927 int t = a; a = b; b = t;933 int t = a; a = b; b = t;
928 inv ^= 1;934 inv ^= 1;
929 }935 }
930 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (((op > TOK_UGT) ? 2 : 3) << 12)); // slt[u] d, a, b936 ER(0x33, (op > TOK_UGT) ? 2 : 3, d, a, b, 0); // slt[u] d, a, b
931 if (inv)937 if (inv)
932 EI(0x13, 4, d, d, 1); // xori d, d, 1938 EI(0x13, 4, d, d, 1); // xori d, d, 1
933 vset_VT_CMP(TOK_NE);939 vset_VT_CMP(TOK_NE);
@@ -935,9 +941,9 @@ static void gen_opil(int op, int ll) · 1 unmodified line
935 break;941 break;
936 case TOK_NE:942 case TOK_NE:
937 case TOK_EQ:943 case TOK_EQ:
938 o(0x33 | (d << 7) | (a << 15) | (b << 20) | (0x20 << 25)); // sub d, a, b944 ER(0x33, 0, d, a, b, 0x20); // sub d, a, b
939 if (op == TOK_NE)945 if (op == TOK_NE)
940 o(0x33 | (3 << 12) | (d << 7) | (0 << 15) | (d << 20)); // sltu d, x0, d == snez d,d946 ER(0x33, 3, d, 0, d, 0); // sltu d, x0, d == snez d,d
941 else947 else
942 EI(0x13, 3, d, d, 1); // sltiu d, d, 1 == seqz d,d948 EI(0x13, 3, d, d, 1); // sltiu d, d, 1 == seqz d,d
943 vset_VT_CMP(TOK_NE);949 vset_VT_CMP(TOK_NE);
@@ -1007,7 +1013,7 @@ ST_FUNC void gen_opf(int op) · 63 unmodified lines
1007 rd = get_reg(RC_FLOAT);1013 rd = get_reg(RC_FLOAT);
1008 vtop->r = rd;1014 vtop->r = rd;
1009 rd = freg(rd);1015 rd = freg(rd);
1010 o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (7 << 12) | (dbl << 25) | (op << 27)); // fop.[sd] RD, RS1, RS2 (dyn rm)1016 ER(0x53, 7, rd, rs1, rs2, dbl | (op << 2)); // fop.[sd] RD, RS1, RS2 (dyn rm)
1011 break;1017 break;
1012 case '-':1018 case '-':
1013 op = 1; // fsub1019 op = 1; // fsub
@@ -1024,7 +1030,7 @@ ST_FUNC void gen_opf(int op) · 10 unmodified lines
1024 rd = get_reg(RC_INT);1030 rd = get_reg(RC_INT);
1025 vtop->r = rd;1031 vtop->r = rd;
1026 rd = ireg(rd);1032 rd = ireg(rd);
1027 o(0x53 | (rd << 7) | (rs1 << 15) | (rs2 << 20) | (op << 12) | (dbl << 25) | (0x14 << 27)); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)1033 ER(0x53, op, rd, rs1, rs2, dbl | 0x50); // fcmp.[sd] RD, RS1, RS2 (op == eq/lt/le)
1028 if (invert)1034 if (invert)
1029 EI(0x13, 4, rd, rd, 1); // xori RD, 11035 EI(0x13, 4, rd, rd, 1); // xori RD, 1
1030 break;1036 break;
@@ -1175,7 +1181,7 @@ ST_FUNC void gen_vla_alloc(CType *type, int align) · 144 unmodified lines
1175 int rr = ireg(gv(RC_INT));1181 int rr = ireg(gv(RC_INT));
1176 EI(0x13, 0, rr, rr, 15); // addi RR, RR, 151182 EI(0x13, 0, rr, rr, 15); // addi RR, RR, 15
1177 EI(0x13, 7, rr, rr, -16); // andi, RR, RR, -161183 EI(0x13, 7, rr, rr, -16); // andi, RR, RR, -16
1178 o(0x33 | (2 << 7) | (2 << 15) | (rr << 20) | (0x20 << 25)); //sub sp, sp, rr1184 ER(0x33, 0, 2, 2, rr, 0x20); // sub sp, sp, rr
1179 vpop();1185 vpop();
1180}1186}
1181#endif1187#endif

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