first support of x86_64 assembly

Frederic Feret committed 17 years ago

Commit 526c4641 parent 0d768b98 files · +1973 −221Browse files

Unified · Split

8 files

Makefile +4 −4
libtcc.c +6 −0
tcc.h +18 −2
tccasm.c +6 −0
tcctok.h +6 −215
x86_64-asm.c +1263 −0
x86_64-asm.h +446 −0
x86_64-tok.h +224 −0

@@ -79,10 +79,10 @@ C67_CROSS = c67-tcc$(EXESUF) · 78 unmodified lines
79	79
80	80	CORE_FILES = tcc.c libtcc.c tccpp.c tccgen.c tccelf.c tccasm.c \
81	81	tcc.h config.h libtcc.h tcctok.h
82		−I386_FILES = $(CORE_FILES) i386-gen.c i386-asm.c i386-asm.h
83		−WIN32_FILES = $(CORE_FILES) i386-gen.c i386-asm.c i386-asm.h tccpe.c
84		−WIN64_FILES = $(CORE_FILES) x86_64-gen.c tccpe.c
85		−X86_64_FILES = $(CORE_FILES) x86_64-gen.c
	82	+I386_FILES = $(CORE_FILES) i386-gen.c i386-asm.c i386-asm.h i386-tok.h
	83	+WIN32_FILES = $(CORE_FILES) i386-gen.c i386-asm.c i386-asm.h i386-tok.h tccpe.c
	84	+WIN64_FILES = $(CORE_FILES) x86_64-gen.c x86_64-asm.c x86_64-asm.h x86_64-tok.h tccpe.c
	85	+X86_64_FILES = $(CORE_FILES) x86_64-gen.c x86_64-asm.c x86_64-asm.h x86_64-tok.h
86	86	ARM_FILES = $(CORE_FILES) arm-gen.c
87	87	C67_FILES = $(CORE_FILES) c67-gen.c tcccoff.c
88	88

libtcc.c+6−0

@@ -324,9 +324,15 @@ static inline int toup(int c) · 323 unmodified lines
324	324	#include "tccgen.c"
325	325
326	326	#ifdef CONFIG_TCC_ASM
	327	+
327	328	#ifdef TCC_TARGET_I386
328	329	#include "i386-asm.c"
329	330	#endif
	331	+
	332	+#ifdef TCC_TARGET_X86_64
	333	+#include "x86_64-asm.c"
	334	+#endif
	335	+
330	336	#include "tccasm.c"
331	337	#else
332	338	static void asm_instr(void)

tcc.h+18−2

@@ -118,8 +118,7 @@ · 117 unmodified lines
118	118	#endif
119	119
120	120	/* define it to include assembler support */
121		−#if !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_C67) && \
122		− !defined(TCC_TARGET_X86_64)
	121	+#if !defined(TCC_TARGET_ARM) && !defined(TCC_TARGET_C67)
123	122	#define CONFIG_TCC_ASM
124	123	#endif
125	124
@@ -675,6 +674,23 @@ struct TCCState { · 549 unmodified lines
675	674	DEF(TOK_ASM_ ## x ## l, #x "l") \
676	675	DEF(TOK_ASM_ ## x, #x)
677	676
	677	+#ifdef TCC_TARGET_X86_64
	678	+
	679	+#define DEF_BWLQ(x) \
	680	+ DEF(TOK_ASM_ ## x ## b, #x "b") \
	681	+ DEF(TOK_ASM_ ## x ## w, #x "w") \
	682	+ DEF(TOK_ASM_ ## x ## l, #x "l") \
	683	+ DEF(TOK_ASM_ ## x ## q, #x "q") \
	684	+ DEF(TOK_ASM_ ## x, #x)
	685	+
	686	+#define DEF_WLQ(x) \
	687	+ DEF(TOK_ASM_ ## x ## w, #x "w") \
	688	+ DEF(TOK_ASM_ ## x ## l, #x "l") \
	689	+ DEF(TOK_ASM_ ## x ## q, #x "q") \
	690	+ DEF(TOK_ASM_ ## x, #x)
	691	+
	692	+#endif
	693	+
678	694	#define DEF_FP1(x) \
679	695	DEF(TOK_ASM_ ## f ## x ## s, "f" #x "s") \
680	696	DEF(TOK_ASM_ ## fi ## x ## l, "fi" #x "l") \

tccasm.c+6−0

@@ -584,6 +584,12 @@ static void asm_parse_directive(TCCState *s1) · 583 unmodified lines
584	584	s1->seg_size = 32;
585	585	}
586	586	break;
	587	+#endif
	588	+#ifdef TCC_TARGET_X86_64
	589	+ /* added for compatibility with GAS */
	590	+ case TOK_ASM_code64:
	591	+ next();
	592	+ break;
587	593	#endif
588	594	default:
589	595	error("unknown assembler directive '.%s'", get_tok_str(tok, NULL));

tcctok.h+6−215

@@ -254,222 +254,13 @@ · 253 unmodified lines
254	254	#if defined(TCC_TARGET_I386)
255	255	DEF_ASM(code16)
256	256	DEF_ASM(code32)
	257	+#elif defined(TCC_TARGET_X86_64)
	258	+ DEF_ASM(code64)
257	259	#endif
258	260
259	261	#ifdef TCC_TARGET_I386
260		−
261		−/* WARNING: relative order of tokens is important. */
262		− DEF_ASM(al)
263		− DEF_ASM(cl)
264		− DEF_ASM(dl)
265		− DEF_ASM(bl)
266		− DEF_ASM(ah)
267		− DEF_ASM(ch)
268		− DEF_ASM(dh)
269		− DEF_ASM(bh)
270		− DEF_ASM(ax)
271		− DEF_ASM(cx)
272		− DEF_ASM(dx)
273		− DEF_ASM(bx)
274		− DEF_ASM(sp)
275		− DEF_ASM(bp)
276		− DEF_ASM(si)
277		− DEF_ASM(di)
278		− DEF_ASM(eax)
279		− DEF_ASM(ecx)
280		− DEF_ASM(edx)
281		− DEF_ASM(ebx)
282		− DEF_ASM(esp)
283		− DEF_ASM(ebp)
284		− DEF_ASM(esi)
285		− DEF_ASM(edi)
286		− DEF_ASM(mm0)
287		− DEF_ASM(mm1)
288		− DEF_ASM(mm2)
289		− DEF_ASM(mm3)
290		− DEF_ASM(mm4)
291		− DEF_ASM(mm5)
292		− DEF_ASM(mm6)
293		− DEF_ASM(mm7)
294		− DEF_ASM(xmm0)
295		− DEF_ASM(xmm1)
296		− DEF_ASM(xmm2)
297		− DEF_ASM(xmm3)
298		− DEF_ASM(xmm4)
299		− DEF_ASM(xmm5)
300		− DEF_ASM(xmm6)
301		− DEF_ASM(xmm7)
302		− DEF_ASM(cr0)
303		− DEF_ASM(cr1)
304		− DEF_ASM(cr2)
305		− DEF_ASM(cr3)
306		− DEF_ASM(cr4)
307		− DEF_ASM(cr5)
308		− DEF_ASM(cr6)
309		− DEF_ASM(cr7)
310		− DEF_ASM(tr0)
311		− DEF_ASM(tr1)
312		− DEF_ASM(tr2)
313		− DEF_ASM(tr3)
314		− DEF_ASM(tr4)
315		− DEF_ASM(tr5)
316		− DEF_ASM(tr6)
317		− DEF_ASM(tr7)
318		− DEF_ASM(db0)
319		− DEF_ASM(db1)
320		− DEF_ASM(db2)
321		− DEF_ASM(db3)
322		− DEF_ASM(db4)
323		− DEF_ASM(db5)
324		− DEF_ASM(db6)
325		− DEF_ASM(db7)
326		− DEF_ASM(dr0)
327		− DEF_ASM(dr1)
328		− DEF_ASM(dr2)
329		− DEF_ASM(dr3)
330		− DEF_ASM(dr4)
331		− DEF_ASM(dr5)
332		− DEF_ASM(dr6)
333		− DEF_ASM(dr7)
334		− DEF_ASM(es)
335		− DEF_ASM(cs)
336		− DEF_ASM(ss)
337		− DEF_ASM(ds)
338		− DEF_ASM(fs)
339		− DEF_ASM(gs)
340		− DEF_ASM(st)
341		−
342		− DEF_BWL(mov)
343		−
344		− /* generic two operands */
345		− DEF_BWL(add)
346		− DEF_BWL(or)
347		− DEF_BWL(adc)
348		− DEF_BWL(sbb)
349		− DEF_BWL(and)
350		− DEF_BWL(sub)
351		− DEF_BWL(xor)
352		− DEF_BWL(cmp)
353		−
354		− /* unary ops */
355		− DEF_BWL(inc)
356		− DEF_BWL(dec)
357		− DEF_BWL(not)
358		− DEF_BWL(neg)
359		− DEF_BWL(mul)
360		− DEF_BWL(imul)
361		− DEF_BWL(div)
362		− DEF_BWL(idiv)
363		−
364		− DEF_BWL(xchg)
365		− DEF_BWL(test)
366		−
367		− /* shifts */
368		− DEF_BWL(rol)
369		− DEF_BWL(ror)
370		− DEF_BWL(rcl)
371		− DEF_BWL(rcr)
372		− DEF_BWL(shl)
373		− DEF_BWL(shr)
374		− DEF_BWL(sar)
375		−
376		− DEF_ASM(shldw)
377		− DEF_ASM(shldl)
378		− DEF_ASM(shld)
379		− DEF_ASM(shrdw)
380		− DEF_ASM(shrdl)
381		− DEF_ASM(shrd)
382		−
383		− DEF_ASM(pushw)
384		− DEF_ASM(pushl)
385		− DEF_ASM(push)
386		− DEF_ASM(popw)
387		− DEF_ASM(popl)
388		− DEF_ASM(pop)
389		− DEF_BWL(in)
390		− DEF_BWL(out)
391		−
392		− DEF_WL(movzb)
393		−
394		− DEF_ASM(movzwl)
395		− DEF_ASM(movsbw)
396		− DEF_ASM(movsbl)
397		− DEF_ASM(movswl)
398		−
399		− DEF_WL(lea)
400		−
401		− DEF_ASM(les)
402		− DEF_ASM(lds)
403		− DEF_ASM(lss)
404		− DEF_ASM(lfs)
405		− DEF_ASM(lgs)
406		−
407		− DEF_ASM(call)
408		− DEF_ASM(jmp)
409		− DEF_ASM(lcall)
410		− DEF_ASM(ljmp)
411		−
412		− DEF_ASMTEST(j)
413		−
414		− DEF_ASMTEST(set)
415		− DEF_ASMTEST(cmov)
416		−
417		− DEF_WL(bsf)
418		− DEF_WL(bsr)
419		− DEF_WL(bt)
420		− DEF_WL(bts)
421		− DEF_WL(btr)
422		− DEF_WL(btc)
423		−
424		− DEF_WL(lsl)
425		−
426		− /* generic FP ops */
427		− DEF_FP(add)
428		− DEF_FP(mul)
429		−
430		− DEF_ASM(fcom)
431		− DEF_ASM(fcom_1) /* non existant op, just to have a regular table */
432		− DEF_FP1(com)
433		−
434		− DEF_FP(comp)
435		− DEF_FP(sub)
436		− DEF_FP(subr)
437		− DEF_FP(div)
438		− DEF_FP(divr)
439		−
440		− DEF_BWL(xadd)
441		− DEF_BWL(cmpxchg)
442		−
443		− /* string ops */
444		− DEF_BWL(cmps)
445		− DEF_BWL(scmp)
446		− DEF_BWL(ins)
447		− DEF_BWL(outs)
448		− DEF_BWL(lods)
449		− DEF_BWL(slod)
450		− DEF_BWL(movs)
451		− DEF_BWL(smov)
452		− DEF_BWL(scas)
453		− DEF_BWL(ssca)
454		− DEF_BWL(stos)
455		− DEF_BWL(ssto)
456		−
457		− /* generic asm ops */
458		−
459		−#define ALT(x)
460		−#define DEF_ASM_OP0(name, opcode) DEF_ASM(name)
461		−#define DEF_ASM_OP0L(name, opcode, group, instr_type)
462		−#define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
463		−#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
464		−#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
465		−#include "i386-asm.h"
466		−
467		−#define ALT(x)
468		−#define DEF_ASM_OP0(name, opcode)
469		−#define DEF_ASM_OP0L(name, opcode, group, instr_type) DEF_ASM(name)
470		−#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) DEF_ASM(name)
471		−#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) DEF_ASM(name)
472		−#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) DEF_ASM(name)
473		−#include "i386-asm.h"
474		−
	262	+#include "i386-tok.h"
	263	+#elif TCC_TARGET_X86_64
	264	+#include "x86_64-tok.h"
475	265	#endif
	266	+

x86_64-asm.c+1263−0

@@ -0,0 +1,1263 @@
	1	+/*
	2	+ * x86_64 specific functions for TCC assembler
	3	+ *
	4	+ * Copyright (c) 2009 Frédéric Feret
	5	+ *
	6	+ * Based on i386-asm.c by Fabrice Bellard
	7	+ *
	8	+ * This library is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU Lesser General Public
	10	+ * License as published by the Free Software Foundation; either
	11	+ * version 2 of the License, or (at your option) any later version.
	12	+ *
	13	+ * This library is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	+ * Lesser General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU Lesser General Public
	19	+ * License along with this library; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	+ */
	22	+
	23	+#define MAX_OPERANDS 3
	24	+
	25	+typedef struct ASMInstr {
	26	+ uint16_t sym;
	27	+ uint16_t opcode;
	28	+ uint16_t instr_type;
	29	+#define OPC_JMP 0x01 /* jmp operand */
	30	+#define OPC_B 0x02 /* only used zith OPC_WL */
	31	+#define OPC_WL 0x04 /* accepts w, l or no suffix */
	32	+#define OPC_BWL (OPC_B \| OPC_WL) /* accepts b, w, l or no suffix */
	33	+#define OPC_REG 0x08 /* register is added to opcode */
	34	+#define OPC_MODRM 0x10 /* modrm encoding */
	35	+#define OPC_FWAIT 0x20 /* add fwait opcode */
	36	+#define OPC_TEST 0x40 /* test opcodes */
	37	+#define OPC_SHIFT 0x80 /* shift opcodes */
	38	+#define OPC_D16 0x0100 /* generate data16 prefix */
	39	+#define OPC_ARITH 0x0200 /* arithmetic opcodes */
	40	+#define OPC_SHORTJMP 0x0400 /* short jmp operand */
	41	+#define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
	42	+#define OPC_WLQ 0x1000 /* accepts w, l, q or no suffix */
	43	+#define OPC_BWLQ (OPC_B \| OPC_WLQ) /* accepts b, w, l, q or no suffix */
	44	+#define OPC_GROUP_SHIFT 13
	45	+
	46	+/* in order to compress the operand type, we use specific operands and
	47	+ we or only with EA */
	48	+#define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
	49	+#define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
	50	+#define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
	51	+#define OPT_REG64 3
	52	+#define OPT_MMX 4 /* warning: value is hardcoded from TOK_ASM_xxx */
	53	+#define OPT_SSE 5 /* warning: value is hardcoded from TOK_ASM_xxx */
	54	+#define OPT_CR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
	55	+#define OPT_TR 7 /* warning: value is hardcoded from TOK_ASM_xxx */
	56	+#define OPT_DB 8 /* warning: value is hardcoded from TOK_ASM_xxx */
	57	+#define OPT_SEG 9
	58	+#define OPT_ST 10
	59	+#define OPT_IM8 11
	60	+#define OPT_IM8S 12
	61	+#define OPT_IM16 13
	62	+#define OPT_IM32 14
	63	+#define OPT_IM64 15
	64	+#define OPT_EAX 16 /* %al, %ax, %eax or %rax register */
	65	+#define OPT_ST0 17 /* %st(0) register */
	66	+#define OPT_CL 18 /* %cl register */
	67	+#define OPT_DX 19 /* %dx register */
	68	+#define OPT_ADDR 20 /* OP_EA with only offset */
	69	+#define OPT_INDIR 21 /* (expr) /
	70	+
	71	+/* composite types */
	72	+#define OPT_COMPOSITE_FIRST 22
	73	+#define OPT_IM 23 /* IM8 \| IM16 \| IM32 \| IM64 */
	74	+#define OPT_REG 24 /* REG8 \| REG16 \| REG32 \| REG64 */
	75	+#define OPT_REGW 25 /* REG16 \| REG32 \| REG64 */
	76	+#define OPT_IMW 26 /* IM16 \| IM32 \| IM64 */
	77	+#define OPT_IMNO64 27 /* IM16 \| IM32 */
	78	+
	79	+/* can be ored with any OPT_xxx */
	80	+#define OPT_EA 0x80
	81	+
	82	+ uint8_t nb_ops;
	83	+ uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
	84	+} ASMInstr;
	85	+
	86	+typedef struct Operand {
	87	+ uint32_t type;
	88	+#define OP_REG8 (1 << OPT_REG8)
	89	+#define OP_REG16 (1 << OPT_REG16)
	90	+#define OP_REG32 (1 << OPT_REG32)
	91	+#define OP_MMX (1 << OPT_MMX)
	92	+#define OP_SSE (1 << OPT_SSE)
	93	+#define OP_CR (1 << OPT_CR)
	94	+#define OP_TR (1 << OPT_TR)
	95	+#define OP_DB (1 << OPT_DB)
	96	+#define OP_SEG (1 << OPT_SEG)
	97	+#define OP_ST (1 << OPT_ST)
	98	+#define OP_IM8 (1 << OPT_IM8)
	99	+#define OP_IM8S (1 << OPT_IM8S)
	100	+#define OP_IM16 (1 << OPT_IM16)
	101	+#define OP_IM32 (1 << OPT_IM32)
	102	+#define OP_EAX (1 << OPT_EAX)
	103	+#define OP_ST0 (1 << OPT_ST0)
	104	+#define OP_CL (1 << OPT_CL)
	105	+#define OP_DX (1 << OPT_DX)
	106	+#define OP_ADDR (1 << OPT_ADDR)
	107	+#define OP_INDIR (1 << OPT_INDIR)
	108	+#define OP_REG64 (1 << OPT_REG64)
	109	+#define OP_IM64 (1 << OPT_IM64)
	110	+
	111	+#define OP_EA 0x40000000
	112	+#define OP_REG (OP_REG8 \| OP_REG16 \| OP_REG32 \| OP_REG64)
	113	+#define OP_IM OP_IM64
	114	+ int8_t reg; /* register, -1 if none */
	115	+ int8_t reg2; /* second register, -1 if none */
	116	+ uint8_t shift;
	117	+ ExprValue e;
	118	+} Operand;
	119	+
	120	+static const uint8_t reg_to_size[7] = {
	121	+/*
	122	+ [OP_REG8] = 0,
	123	+ [OP_REG16] = 1,
	124	+ [OP_REG32] = 2,
	125	+ [OP_REG64] = 3,
	126	+*/
	127	+ 0, 0, 1, 0, 2, 0, 3
	128	+};
	129	+
	130	+#define NB_TEST_OPCODES 30
	131	+
	132	+static const uint8_t test_bits[NB_TEST_OPCODES] = {
	133	+ 0x00, /* o */
	134	+ 0x01, /* no */
	135	+ 0x02, /* b */
	136	+ 0x02, /* c */
	137	+ 0x02, /* nae */
	138	+ 0x03, /* nb */
	139	+ 0x03, /* nc */
	140	+ 0x03, /* ae */
	141	+ 0x04, /* e */
	142	+ 0x04, /* z */
	143	+ 0x05, /* ne */
	144	+ 0x05, /* nz */
	145	+ 0x06, /* be */
	146	+ 0x06, /* na */
	147	+ 0x07, /* nbe */
	148	+ 0x07, /* a */
	149	+ 0x08, /* s */
	150	+ 0x09, /* ns */
	151	+ 0x0a, /* p */
	152	+ 0x0a, /* pe */
	153	+ 0x0b, /* np */
	154	+ 0x0b, /* po */
	155	+ 0x0c, /* l */
	156	+ 0x0c, /* nge */
	157	+ 0x0d, /* nl */
	158	+ 0x0d, /* ge */
	159	+ 0x0e, /* le */
	160	+ 0x0e, /* ng */
	161	+ 0x0f, /* nle */
	162	+ 0x0f, /* g */
	163	+};
	164	+
	165	+static const uint8_t segment_prefixes[] = {
	166	+ 0x26, /* es */
	167	+ 0x2e, /* cs */
	168	+ 0x36, /* ss */
	169	+ 0x3e, /* ds */
	170	+ 0x64, /* fs */
	171	+ 0x65 /* gs */
	172	+};
	173	+
	174	+static const ASMInstr asm_instrs[] = {
	175	+#define ALT(x) x
	176	+#define DEF_ASM_OP0(name, opcode)
	177	+#define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type \| group << OPC_GROUP_SHIFT), 0 },
	178	+#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type \| group << OPC_GROUP_SHIFT), 1, { op0 }},
	179	+#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type \| group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
	180	+#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type \| group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
	181	+#include "x86_64-asm.h"
	182	+
	183	+ /* last operation */
	184	+ { 0, },
	185	+};
	186	+
	187	+static const uint16_t op0_codes[] = {
	188	+#define ALT(x)
	189	+#define DEF_ASM_OP0(x, opcode) opcode,
	190	+#define DEF_ASM_OP0L(name, opcode, group, instr_type)
	191	+#define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
	192	+#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
	193	+#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
	194	+#include "x86_64-asm.h"
	195	+};
	196	+
	197	+static inline int get_reg_shift(TCCState *s1)
	198	+{
	199	+ int shift, v;
	200	+
	201	+ v = asm_int_expr(s1);
	202	+ switch(v) {
	203	+ case 1:
	204	+ shift = 0;
	205	+ break;
	206	+ case 2:
	207	+ shift = 1;
	208	+ break;
	209	+ case 4:
	210	+ shift = 2;
	211	+ break;
	212	+ case 8:
	213	+ shift = 3;
	214	+ break;
	215	+ default:
	216	+ expect("1, 2, 4 or 8 constant");
	217	+ shift = 0;
	218	+ break;
	219	+ }
	220	+ return shift;
	221	+}
	222	+
	223	+static int asm_parse_reg(void)
	224	+{
	225	+ int reg;
	226	+ if (tok != '%')
	227	+ goto error_32;
	228	+ next();
	229	+ if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
	230	+ reg = tok - TOK_ASM_rax;
	231	+ next();
	232	+ return reg;
	233	+ } else if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
	234	+ reg = tok - TOK_ASM_eax;
	235	+ next();
	236	+ return reg;
	237	+ } else {
	238	+ error_32:
	239	+ expect("64 bit register");
	240	+ return 0;
	241	+ }
	242	+}
	243	+
	244	+static void parse_operand(TCCState s1, Operand op)
	245	+{
	246	+ ExprValue e;
	247	+ int reg, indir;
	248	+ const char *p;
	249	+
	250	+ indir = 0;
	251	+ if (tok == '*') {
	252	+ next();
	253	+ indir = OP_INDIR;
	254	+ }
	255	+
	256	+ if (tok == '%') {
	257	+ next();
	258	+ if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
	259	+ reg = tok - TOK_ASM_al;
	260	+ op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
	261	+ op->reg = reg & 7;
	262	+ if ((op->type & OP_REG) && op->reg == TREG_RAX)
	263	+ op->type \|= OP_EAX;
	264	+ else if (op->type == OP_REG8 && op->reg == TREG_RCX)
	265	+ op->type \|= OP_CL;
	266	+ else if (op->type == OP_REG16 && op->reg == TREG_RDX)
	267	+ op->type \|= OP_DX;
	268	+ } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
	269	+ op->type = OP_DB;
	270	+ op->reg = tok - TOK_ASM_dr0;
	271	+ } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
	272	+ op->type = OP_SEG;
	273	+ op->reg = tok - TOK_ASM_es;
	274	+ } else if (tok == TOK_ASM_st) {
	275	+ op->type = OP_ST;
	276	+ op->reg = 0;
	277	+ next();
	278	+ if (tok == '(') {
	279	+ next();
	280	+ if (tok != TOK_PPNUM)
	281	+ goto reg_error;
	282	+ p = tokc.cstr->data;
	283	+ reg = p[0] - '0';
	284	+ if ((unsigned)reg >= 8 \|\| p[1] != '\0')
	285	+ goto reg_error;
	286	+ op->reg = reg;
	287	+ next();
	288	+ skip(')');
	289	+ }
	290	+ if (op->reg == 0)
	291	+ op->type \|= OP_ST0;
	292	+ goto no_skip;
	293	+ } else {
	294	+ reg_error:
	295	+ error("unknown register");
	296	+ }
	297	+ next();
	298	+ no_skip: ;
	299	+ } else if (tok == '$') {
	300	+ /* constant value */
	301	+ next();
	302	+ asm_expr(s1, &e);
	303	+ op->type = OP_IM64;
	304	+ op->e.v = e.v;
	305	+ op->e.sym = e.sym;
	306	+ if (!op->e.sym) {
	307	+ if (op->e.v == (uint8_t)op->e.v)
	308	+ op->type \|= OP_IM8;
	309	+ if (op->e.v == (int8_t)op->e.v)
	310	+ op->type \|= OP_IM8S;
	311	+ if (op->e.v == (uint16_t)op->e.v)
	312	+ op->type \|= OP_IM16;
	313	+ if (op->e.v == (uint32_t)op->e.v)
	314	+ op->type \|= OP_IM32;
	315	+ }
	316	+ } else {
	317	+ /* address(reg,reg2,shift) with all variants */
	318	+ op->type = OP_EA;
	319	+ op->reg = -1;
	320	+ op->reg2 = -1;
	321	+ op->shift = 0;
	322	+ if (tok != '(') {
	323	+ asm_expr(s1, &e);
	324	+ op->e.v = e.v;
	325	+ op->e.sym = e.sym;
	326	+ } else {
	327	+ op->e.v = 0;
	328	+ op->e.sym = NULL;
	329	+ }
	330	+ if (tok == '(') {
	331	+ next();
	332	+ if (tok != ',') {
	333	+ op->reg = asm_parse_reg();
	334	+ }
	335	+ if (tok == ',') {
	336	+ next();
	337	+ if (tok != ',') {
	338	+ op->reg2 = asm_parse_reg();
	339	+ }
	340	+ if (tok == ',') {
	341	+ next();
	342	+ op->shift = get_reg_shift(s1);
	343	+ }
	344	+ }
	345	+ skip(')');
	346	+ }
	347	+ if (op->reg == -1 && op->reg2 == -1)
	348	+ op->type \|= OP_ADDR;
	349	+ }
	350	+ op->type \|= indir;
	351	+}
	352	+
	353	+/* XXX: unify with C code output ? */
	354	+static void gen_expr32(ExprValue *pe)
	355	+{
	356	+ if (pe->sym)
	357	+ greloc(cur_text_section, pe->sym, ind, R_X86_64_32);
	358	+ gen_le32(pe->v);
	359	+}
	360	+
	361	+static void gen_expr64(ExprValue *pe)
	362	+{
	363	+ if (pe->sym)
	364	+ greloc(cur_text_section, pe->sym, ind, R_X86_64_64);
	365	+ gen_le64(pe->v);
	366	+}
	367	+
	368	+/* XXX: unify with C code output ? */
	369	+static void gen_disp32(ExprValue *pe)
	370	+{
	371	+ Sym *sym;
	372	+ sym = pe->sym;
	373	+ if (sym) {
	374	+ if (sym->r == cur_text_section->sh_num) {
	375	+ /* same section: we can output an absolute value. Note
	376	+ that the TCC compiler behaves differently here because
	377	+ it always outputs a relocation to ease (future) code
	378	+ elimination in the linker */
	379	+ gen_le32(pe->v + (long)sym->next - ind - 4);
	380	+ } else {
	381	+ greloc(cur_text_section, sym, ind, R_X86_64_PC32);
	382	+ gen_le32(pe->v - 4);
	383	+ }
	384	+ } else {
	385	+ /* put an empty PC32 relocation */
	386	+ put_elf_reloc(symtab_section, cur_text_section,
	387	+ ind, R_X86_64_PC32, 0);
	388	+ gen_le32(pe->v - 4);
	389	+ }
	390	+}
	391	+
	392	+
	393	+static void gen_le16(int v)
	394	+{
	395	+ g(v);
	396	+ g(v >> 8);
	397	+}
	398	+
	399	+/* generate the modrm operand */
	400	+static inline void asm_modrm(int reg, Operand *op)
	401	+{
	402	+ int mod, reg1, reg2, sib_reg1;
	403	+
	404	+ if (op->type & (OP_REG \| OP_MMX \| OP_SSE)) {
	405	+ g(0xc0 + (reg << 3) + op->reg);
	406	+ } else if (op->reg == -1 && op->reg2 == -1) {
	407	+ /* displacement only */
	408	+ g(0x05 + (reg << 3));
	409	+ gen_expr32(&op->e);
	410	+ } else {
	411	+ sib_reg1 = op->reg;
	412	+ /* fist compute displacement encoding */
	413	+ if (sib_reg1 == -1) {
	414	+ sib_reg1 = 5;
	415	+ mod = 0x00;
	416	+ } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
	417	+ mod = 0x00;
	418	+ } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
	419	+ mod = 0x40;
	420	+ } else {
	421	+ mod = 0x80;
	422	+ }
	423	+ /* compute if sib byte needed */
	424	+ reg1 = op->reg;
	425	+ if (op->reg2 != -1)
	426	+ reg1 = 4;
	427	+ g(mod + (reg << 3) + reg1);
	428	+ if (reg1 == 4) {
	429	+ /* add sib byte */
	430	+ reg2 = op->reg2;
	431	+ if (reg2 == -1)
	432	+ reg2 = 4; /* indicate no index */
	433	+ g((op->shift << 6) + (reg2 << 3) + sib_reg1);
	434	+ }
	435	+
	436	+ /* add offset */
	437	+ if (mod == 0x40) {
	438	+ g(op->e.v);
	439	+ } else if (mod == 0x80 \|\| op->reg == -1) {
	440	+ gen_expr32(&op->e);
	441	+ }
	442	+ }
	443	+}
	444	+
	445	+static void asm_opcode(TCCState *s1, int opcode)
	446	+{
	447	+ const ASMInstr *pa;
	448	+ int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
	449	+ int nb_ops, s, ss;
	450	+ Operand ops[MAX_OPERANDS], *pop;
	451	+ int op_type[3]; /* decoded op type */
	452	+ char rex;
	453	+
	454	+ /* get operands */
	455	+ pop = ops;
	456	+ nb_ops = 0;
	457	+ seg_prefix = 0;
	458	+ rex = 0x48;
	459	+ for(;;) {
	460	+ if (tok == ';' \|\| tok == TOK_LINEFEED)
	461	+ break;
	462	+ if (nb_ops >= MAX_OPERANDS) {
	463	+ error("incorrect number of operands");
	464	+ }
	465	+ parse_operand(s1, pop);
	466	+ if (tok == ':') {
	467	+ if (pop->type != OP_SEG \|\| seg_prefix) {
	468	+ error("incorrect prefix");
	469	+ }
	470	+ seg_prefix = segment_prefixes[pop->reg];
	471	+ next();
	472	+ parse_operand(s1, pop);
	473	+ if (!(pop->type & OP_EA)) {
	474	+ error("segment prefix must be followed by memory reference");
	475	+ }
	476	+ }
	477	+ pop++;
	478	+ nb_ops++;
	479	+ if (tok != ',')
	480	+ break;
	481	+ next();
	482	+ }
	483	+
	484	+ is_short_jmp = 0;
	485	+ s = 0; /* avoid warning */
	486	+
	487	+ /* optimize matching by using a lookup table (no hashing is needed
	488	+ !) */
	489	+ for(pa = asm_instrs; pa->sym != 0; pa++) {
	490	+ s = 0;
	491	+ if (pa->instr_type & OPC_FARITH) {
	492	+ v = opcode - pa->sym;
	493	+ if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
	494	+ continue;
	495	+ } else if (pa->instr_type & OPC_ARITH) {
	496	+ if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
	497	+ continue;
	498	+ goto compute_size;
	499	+ } else if (pa->instr_type & OPC_SHIFT) {
	500	+ if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
	501	+ continue;
	502	+ goto compute_size;
	503	+ } else if (pa->instr_type & OPC_TEST) {
	504	+ if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
	505	+ continue;
	506	+ } else if (pa->instr_type & OPC_B) {
	507	+ if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
	508	+ continue;
	509	+ compute_size:
	510	+ s = (opcode - pa->sym) & 3;
	511	+ } else if (pa->instr_type & OPC_WLQ) {
	512	+ if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
	513	+ continue;
	514	+ s = opcode - pa->sym + 1;
	515	+ } else {
	516	+ if (pa->sym != opcode)
	517	+ continue;
	518	+ }
	519	+ if (pa->nb_ops != nb_ops)
	520	+ continue;
	521	+ /* now decode and check each operand */
	522	+ for(i = 0; i < nb_ops; i++) {
	523	+ int op1, op2;
	524	+ op1 = pa->op_type[i];
	525	+ op2 = op1 & 0x1f;
	526	+ switch(op2) {
	527	+ case OPT_IM:
	528	+ v = OP_IM8 \| OP_IM16 \| OP_IM32 \| OP_IM64;
	529	+ break;
	530	+ case OPT_REG:
	531	+ v = OP_REG8 \| OP_REG16 \| OP_REG32 \| OP_REG64;
	532	+ break;
	533	+ case OPT_REGW:
	534	+ v = OP_REG16 \| OP_REG32 \| OP_REG64;
	535	+ break;
	536	+ case OPT_IMW:
	537	+ v = OP_IM16 \| OP_IM32 \| OP_IM64;
	538	+ break;
	539	+ case OPT_IMNO64:
	540	+ v = OP_IM16 \| OP_IM32;
	541	+ break;
	542	+ default:
	543	+ v = 1 << op2;
	544	+ break;
	545	+ }
	546	+ if (op1 & OPT_EA)
	547	+ v \|= OP_EA;
	548	+ op_type[i] = v;
	549	+ if ((ops[i].type & v) == 0)
	550	+ goto next;
	551	+ }
	552	+ /* all is matching ! */
	553	+ break;
	554	+ next: ;
	555	+ }
	556	+ if (pa->sym == 0) {
	557	+ if (opcode >= TOK_ASM_clc && opcode <= TOK_ASM_emms) {
	558	+ int b;
	559	+ b = op0_codes[opcode - TOK_ASM_clc];
	560	+ if (b & 0xff00)
	561	+ g(b >> 8);
	562	+ g(b);
	563	+ return;
	564	+ } else {
	565	+ error("unknown opcode '%s'",
	566	+ get_tok_str(opcode, NULL));
	567	+ }
	568	+ }
	569	+ /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
	570	+ if (s == 4) {
	571	+ for(i = 0; s == 4 && i < nb_ops; i++) {
	572	+ if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL \| OP_DX)))
	573	+ s = reg_to_size[ops[i].type & OP_REG];
	574	+ }
	575	+ if (s == 4) {
	576	+ if ((opcode == TOK_ASM_push \|\| opcode == TOK_ASM_pop) &&
	577	+ (ops[0].type & (OP_SEG \| OP_IM8S \| OP_IM32 \| OP_IM64)))
	578	+ s = 2;
	579	+ else
	580	+ error("cannot infer opcode suffix");
	581	+ }
	582	+ }
	583	+
	584	+ /* generate data16 prefix if needed */
	585	+ ss = s;
	586	+ if (s == 1 \|\| (pa->instr_type & OPC_D16))
	587	+ g(0x66);
	588	+ else if (s == 2)
	589	+ s = 1;
	590	+ else if (s == 3) {
	591	+ /* generate REX prefix */
	592	+ g(rex);
	593	+ s = 1;
	594	+ }
	595	+ /* now generates the operation */
	596	+ if (pa->instr_type & OPC_FWAIT)
	597	+ g(0x9b);
	598	+ if (seg_prefix)
	599	+ g(seg_prefix);
	600	+
	601	+ v = pa->opcode;
	602	+ if (v == 0x69 \|\| v == 0x69) {
	603	+ /* kludge for imul $im, %reg */
	604	+ nb_ops = 3;
	605	+ ops[2] = ops[1];
	606	+ } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
	607	+ v--; /* int $3 case */
	608	+ nb_ops = 0;
	609	+ } else if ((v == 0x06 \|\| v == 0x07)) {
	610	+ if (ops[0].reg >= 4) {
	611	+ /* push/pop %fs or %gs */
	612	+ v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
	613	+ } else {
	614	+ v += ops[0].reg << 3;
	615	+ }
	616	+ nb_ops = 0;
	617	+ } else if (v <= 0x05) {
	618	+ /* arith case */
	619	+ v += ((opcode - TOK_ASM_addb) >> 2) << 3;
	620	+ } else if ((pa->instr_type & (OPC_FARITH \| OPC_MODRM)) == OPC_FARITH) {
	621	+ /* fpu arith case */
	622	+ v += ((opcode - pa->sym) / 6) << 3;
	623	+ }
	624	+ if (pa->instr_type & OPC_REG) {
	625	+ for(i = 0; i < nb_ops; i++) {
	626	+ if (op_type[i] & (OP_REG \| OP_ST)) {
	627	+ v += ops[i].reg;
	628	+ break;
	629	+ }
	630	+ }
	631	+ /* mov $im, %reg case */
	632	+ if (pa->opcode == 0xb0 && s >= 1)
	633	+ v += 7;
	634	+ }
	635	+ if (pa->instr_type & OPC_B)
	636	+ v += s;
	637	+ if (pa->instr_type & OPC_TEST)
	638	+ v += test_bits[opcode - pa->sym];
	639	+ if (pa->instr_type & OPC_SHORTJMP) {
	640	+ Sym *sym;
	641	+ int jmp_disp;
	642	+
	643	+ /* see if we can really generate the jump with a byte offset */
	644	+ sym = ops[0].e.sym;
	645	+ if (!sym)
	646	+ goto no_short_jump;
	647	+ if (sym->r != cur_text_section->sh_num)
	648	+ goto no_short_jump;
	649	+ jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
	650	+ if (jmp_disp == (int8_t)jmp_disp) {
	651	+ /* OK to generate jump */
	652	+ is_short_jmp = 1;
	653	+ ops[0].e.v = jmp_disp;
	654	+ } else {
	655	+ no_short_jump:
	656	+ if (pa->instr_type & OPC_JMP) {
	657	+ /* long jump will be allowed. need to modify the
	658	+ opcode slightly */
	659	+ if (v == 0xeb)
	660	+ v = 0xe9;
	661	+ else
	662	+ v += 0x0f10;
	663	+ } else {
	664	+ error("invalid displacement");
	665	+ }
	666	+ }
	667	+ }
	668	+ op1 = v >> 8;
	669	+ if (op1)
	670	+ g(op1);
	671	+ g(v);
	672	+
	673	+ /* search which operand will used for modrm */
	674	+ modrm_index = 0;
	675	+ if (pa->instr_type & OPC_SHIFT) {
	676	+ reg = (opcode - pa->sym) >> 2;
	677	+ if (reg == 6)
	678	+ reg = 7;
	679	+ } else if (pa->instr_type & OPC_ARITH) {
	680	+ reg = (opcode - pa->sym) >> 2;
	681	+ } else if (pa->instr_type & OPC_FARITH) {
	682	+ reg = (opcode - pa->sym) / 6;
	683	+ } else {
	684	+ reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
	685	+ }
	686	+ if (pa->instr_type & OPC_MODRM) {
	687	+ /* first look for an ea operand */
	688	+ for(i = 0;i < nb_ops; i++) {
	689	+ if (op_type[i] & OP_EA)
	690	+ goto modrm_found;
	691	+ }
	692	+ /* then if not found, a register or indirection (shift instructions) */
	693	+ for(i = 0;i < nb_ops; i++) {
	694	+ if (op_type[i] & (OP_REG \| OP_MMX \| OP_SSE \| OP_INDIR))
	695	+ goto modrm_found;
	696	+ }
	697	+#ifdef ASM_DEBUG
	698	+ error("bad op table");
	699	+#endif
	700	+ modrm_found:
	701	+ modrm_index = i;
	702	+ /* if a register is used in another operand then it is
	703	+ used instead of group */
	704	+ for(i = 0;i < nb_ops; i++) {
	705	+ v = op_type[i];
	706	+ if (i != modrm_index &&
	707	+ (v & (OP_REG \| OP_MMX \| OP_SSE \| OP_CR \| OP_TR \| OP_DB \| OP_SEG))) {
	708	+ reg = ops[i].reg;
	709	+ break;
	710	+ }
	711	+ }
	712	+
	713	+ asm_modrm(reg, &ops[modrm_index]);
	714	+ }
	715	+
	716	+ /* emit constants */
	717	+ {
	718	+ for(i = 0;i < nb_ops; i++) {
	719	+ v = op_type[i];
	720	+ if (v & (OP_IM8 \| OP_IM16 \| OP_IM32 \| OP_IM64 \| OP_IM8S \| OP_ADDR)) {
	721	+ /* if multiple sizes are given it means we must look
	722	+ at the op size */
	723	+ if (v == (OP_IM8 \| OP_IM16 \| OP_IM32 \| OP_IM64) \|\|
	724	+ v == (OP_IM16 \| OP_IM32 \| OP_IM64)) {
	725	+ if (ss == 0)
	726	+ v = OP_IM8;
	727	+ else if (ss == 1)
	728	+ v = OP_IM16;
	729	+ else if (ss == 2)
	730	+ v = OP_IM32;
	731	+ else
	732	+ v = OP_IM64;
	733	+ } else if (v == (OP_IM8 \| OP_IM16 \| OP_IM32) \|\|
	734	+ v == (OP_IM16 \| OP_IM32)) {
	735	+ if (ss == 0)
	736	+ v = OP_IM8;
	737	+ else if (ss == 1)
	738	+ v = OP_IM16;
	739	+ else
	740	+ v = OP_IM32;
	741	+ }
	742	+ if (v & (OP_IM8 \| OP_IM8S)) {
	743	+ if (ops[i].e.sym)
	744	+ goto error_relocate;
	745	+ g(ops[i].e.v);
	746	+ } else if (v & OP_IM16) {
	747	+ if (ops[i].e.sym) {
	748	+ error_relocate:
	749	+ error("cannot relocate");
	750	+ }
	751	+ gen_le16(ops[i].e.v);
	752	+ } else {
	753	+ if (pa->instr_type & (OPC_JMP \| OPC_SHORTJMP)) {
	754	+ if (is_short_jmp)
	755	+ g(ops[i].e.v);
	756	+ else
	757	+ gen_disp32(&ops[i].e);
	758	+ } else {
	759	+ if (v & OP_IM64)
	760	+ gen_expr64(&ops[i].e);
	761	+ else
	762	+ gen_expr32(&ops[i].e);
	763	+ }
	764	+ }
	765	+ } else if (v & (OP_REG32 \| OP_REG64)) {
	766	+ if (pa->instr_type & (OPC_JMP \| OPC_SHORTJMP)) {
	767	+ /* jmp $r */
	768	+ g(0xE0 + ops[i].reg);
	769	+ }
	770	+ }
	771	+ }
	772	+ }
	773	+}
	774	+
	775	+#define NB_SAVED_REGS 3
	776	+#define NB_ASM_REGS 8
	777	+
	778	+/* return the constraint priority (we allocate first the lowest
	779	+ numbered constraints) */
	780	+static inline int constraint_priority(const char *str)
	781	+{
	782	+ int priority, c, pr;
	783	+
	784	+ /* we take the lowest priority */
	785	+ priority = 0;
	786	+ for(;;) {
	787	+ c = *str;
	788	+ if (c == '\0')
	789	+ break;
	790	+ str++;
	791	+ switch(c) {
	792	+ case 'A':
	793	+ pr = 0;
	794	+ break;
	795	+ case 'a':
	796	+ case 'b':
	797	+ case 'c':
	798	+ case 'd':
	799	+ case 'S':
	800	+ case 'D':
	801	+ pr = 1;
	802	+ break;
	803	+ case 'q':
	804	+ pr = 2;
	805	+ break;
	806	+ case 'r':
	807	+ pr = 3;
	808	+ break;
	809	+ case 'N':
	810	+ case 'M':
	811	+ case 'I':
	812	+ case 'i':
	813	+ case 'm':
	814	+ case 'g':
	815	+ pr = 4;
	816	+ break;
	817	+ default:
	818	+ error("unknown constraint '%c'", c);
	819	+ pr = 0;
	820	+ }
	821	+ if (pr > priority)
	822	+ priority = pr;
	823	+ }
	824	+ return priority;
	825	+}
	826	+
	827	+static const char skip_constraint_modifiers(const char p)
	828	+{
	829	+ while (p == '=' \|\| p == '&' \|\| p == '+' \|\| p == '%')
	830	+ p++;
	831	+ return p;
	832	+}
	833	+
	834	+#define REG_OUT_MASK 0x01
	835	+#define REG_IN_MASK 0x02
	836	+
	837	+#define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
	838	+
	839	+static void asm_compute_constraints(ASMOperand *operands,
	840	+ int nb_operands, int nb_outputs,
	841	+ const uint8_t *clobber_regs,
	842	+ int *pout_reg)
	843	+{
	844	+ ASMOperand *op;
	845	+ int sorted_op[MAX_ASM_OPERANDS];
	846	+ int i, j, k, p1, p2, tmp, reg, c, reg_mask;
	847	+ const char *str;
	848	+ uint8_t regs_allocated[NB_ASM_REGS];
	849	+
	850	+ /* init fields */
	851	+ for(i=0;i<nb_operands;i++) {
	852	+ op = &operands[i];
	853	+ op->input_index = -1;
	854	+ op->ref_index = -1;
	855	+ op->reg = -1;
	856	+ op->is_memory = 0;
	857	+ op->is_rw = 0;
	858	+ }
	859	+ /* compute constraint priority and evaluate references to output
	860	+ constraints if input constraints */
	861	+ for(i=0;i<nb_operands;i++) {
	862	+ op = &operands[i];
	863	+ str = op->constraint;
	864	+ str = skip_constraint_modifiers(str);
	865	+ if (isnum(str) \|\| str == '[') {
	866	+ /* this is a reference to another constraint */
	867	+ k = find_constraint(operands, nb_operands, str, NULL);
	868	+ if ((unsigned)k >= i \|\| i < nb_outputs)
	869	+ error("invalid reference in constraint %d ('%s')",
	870	+ i, str);
	871	+ op->ref_index = k;
	872	+ if (operands[k].input_index >= 0)
	873	+ error("cannot reference twice the same operand");
	874	+ operands[k].input_index = i;
	875	+ op->priority = 5;
	876	+ } else {
	877	+ op->priority = constraint_priority(str);
	878	+ }
	879	+ }
	880	+
	881	+ /* sort operands according to their priority */
	882	+ for(i=0;i<nb_operands;i++)
	883	+ sorted_op[i] = i;
	884	+ for(i=0;i<nb_operands - 1;i++) {
	885	+ for(j=i+1;j<nb_operands;j++) {
	886	+ p1 = operands[sorted_op[i]].priority;
	887	+ p2 = operands[sorted_op[j]].priority;
	888	+ if (p2 < p1) {
	889	+ tmp = sorted_op[i];
	890	+ sorted_op[i] = sorted_op[j];
	891	+ sorted_op[j] = tmp;
	892	+ }
	893	+ }
	894	+ }
	895	+
	896	+ for(i = 0;i < NB_ASM_REGS; i++) {
	897	+ if (clobber_regs[i])
	898	+ regs_allocated[i] = REG_IN_MASK \| REG_OUT_MASK;
	899	+ else
	900	+ regs_allocated[i] = 0;
	901	+ }
	902	+ /* esp cannot be used */
	903	+ regs_allocated[4] = REG_IN_MASK \| REG_OUT_MASK;
	904	+ /* ebp cannot be used yet */
	905	+ regs_allocated[5] = REG_IN_MASK \| REG_OUT_MASK;
	906	+
	907	+ /* allocate registers and generate corresponding asm moves */
	908	+ for(i=0;i<nb_operands;i++) {
	909	+ j = sorted_op[i];
	910	+ op = &operands[j];
	911	+ str = op->constraint;
	912	+ /* no need to allocate references */
	913	+ if (op->ref_index >= 0)
	914	+ continue;
	915	+ /* select if register is used for output, input or both */
	916	+ if (op->input_index >= 0) {
	917	+ reg_mask = REG_IN_MASK \| REG_OUT_MASK;
	918	+ } else if (j < nb_outputs) {
	919	+ reg_mask = REG_OUT_MASK;
	920	+ } else {
	921	+ reg_mask = REG_IN_MASK;
	922	+ }
	923	+ try_next:
	924	+ c = *str++;
	925	+ switch(c) {
	926	+ case '=':
	927	+ goto try_next;
	928	+ case '+':
	929	+ op->is_rw = 1;
	930	+ /* FALL THRU */
	931	+ case '&':
	932	+ if (j >= nb_outputs)
	933	+ error("'%c' modifier can only be applied to outputs", c);
	934	+ reg_mask = REG_IN_MASK \| REG_OUT_MASK;
	935	+ goto try_next;
	936	+ case 'A':
	937	+ /* allocate both eax and edx */
	938	+ if (is_reg_allocated(TREG_RAX) \|\|
	939	+ is_reg_allocated(TREG_RDX))
	940	+ goto try_next;
	941	+ op->is_llong = 1;
	942	+ op->reg = TREG_RAX;
	943	+ regs_allocated[TREG_RAX] \|= reg_mask;
	944	+ regs_allocated[TREG_RDX] \|= reg_mask;
	945	+ break;
	946	+ case 'a':
	947	+ reg = TREG_RAX;
	948	+ goto alloc_reg;
	949	+ case 'b':
	950	+ reg = 3;
	951	+ goto alloc_reg;
	952	+ case 'c':
	953	+ reg = TREG_RCX;
	954	+ goto alloc_reg;
	955	+ case 'd':
	956	+ reg = TREG_RDX;
	957	+ goto alloc_reg;
	958	+ case 'S':
	959	+ reg = 6;
	960	+ goto alloc_reg;
	961	+ case 'D':
	962	+ reg = 7;
	963	+ alloc_reg:
	964	+ if (is_reg_allocated(reg))
	965	+ goto try_next;
	966	+ goto reg_found;
	967	+ case 'q':
	968	+ /* eax, ebx, ecx or edx */
	969	+ for(reg = 0; reg < 4; reg++) {
	970	+ if (!is_reg_allocated(reg))
	971	+ goto reg_found;
	972	+ }
	973	+ goto try_next;
	974	+ case 'r':
	975	+ /* any general register */
	976	+ for(reg = 0; reg < 8; reg++) {
	977	+ if (!is_reg_allocated(reg))
	978	+ goto reg_found;
	979	+ }
	980	+ goto try_next;
	981	+ reg_found:
	982	+ /* now we can reload in the register */
	983	+ op->is_llong = 0;
	984	+ op->reg = reg;
	985	+ regs_allocated[reg] \|= reg_mask;
	986	+ break;
	987	+ case 'i':
	988	+ if (!((op->vt->r & (VT_VALMASK \| VT_LVAL)) == VT_CONST))
	989	+ goto try_next;
	990	+ break;
	991	+ case 'I':
	992	+ case 'N':
	993	+ case 'M':
	994	+ if (!((op->vt->r & (VT_VALMASK \| VT_LVAL \| VT_SYM)) == VT_CONST))
	995	+ goto try_next;
	996	+ break;
	997	+ case 'm':
	998	+ case 'g':
	999	+ /* nothing special to do because the operand is already in
	1000	+ memory, except if the pointer itself is stored in a
	1001	+ memory variable (VT_LLOCAL case) */
	1002	+ /* XXX: fix constant case */
	1003	+ /* if it is a reference to a memory zone, it must lie
	1004	+ in a register, so we reserve the register in the
	1005	+ input registers and a load will be generated
	1006	+ later */
	1007	+ if (j < nb_outputs \|\| c == 'm') {
	1008	+ if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
	1009	+ /* any general register */
	1010	+ for(reg = 0; reg < 8; reg++) {
	1011	+ if (!(regs_allocated[reg] & REG_IN_MASK))
	1012	+ goto reg_found1;
	1013	+ }
	1014	+ goto try_next;
	1015	+ reg_found1:
	1016	+ /* now we can reload in the register */
	1017	+ regs_allocated[reg] \|= REG_IN_MASK;
	1018	+ op->reg = reg;
	1019	+ op->is_memory = 1;
	1020	+ }
	1021	+ }
	1022	+ break;
	1023	+ default:
	1024	+ error("asm constraint %d ('%s') could not be satisfied",
	1025	+ j, op->constraint);
	1026	+ break;
	1027	+ }
	1028	+ /* if a reference is present for that operand, we assign it too */
	1029	+ if (op->input_index >= 0) {
	1030	+ operands[op->input_index].reg = op->reg;
	1031	+ operands[op->input_index].is_llong = op->is_llong;
	1032	+ }
	1033	+ }
	1034	+
	1035	+ /* compute out_reg. It is used to store outputs registers to memory
	1036	+ locations references by pointers (VT_LLOCAL case) */
	1037	+ *pout_reg = -1;
	1038	+ for(i=0;i<nb_operands;i++) {
	1039	+ op = &operands[i];
	1040	+ if (op->reg >= 0 &&
	1041	+ (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
	1042	+ !op->is_memory) {
	1043	+ for(reg = 0; reg < 8; reg++) {
	1044	+ if (!(regs_allocated[reg] & REG_OUT_MASK))
	1045	+ goto reg_found2;
	1046	+ }
	1047	+ error("could not find free output register for reloading");
	1048	+ reg_found2:
	1049	+ *pout_reg = reg;
	1050	+ break;
	1051	+ }
	1052	+ }
	1053	+
	1054	+ /* print sorted constraints */
	1055	+#ifdef ASM_DEBUG
	1056	+ for(i=0;i<nb_operands;i++) {
	1057	+ j = sorted_op[i];
	1058	+ op = &operands[j];
	1059	+ printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
	1060	+ j,
	1061	+ op->id ? get_tok_str(op->id, NULL) : "",
	1062	+ op->constraint,
	1063	+ op->vt->r,
	1064	+ op->reg);
	1065	+ }
	1066	+ if (*pout_reg >= 0)
	1067	+ printf("out_reg=%d\n", *pout_reg);
	1068	+#endif
	1069	+}
	1070	+
	1071	+static void subst_asm_operand(CString *add_str,
	1072	+ SValue *sv, int modifier)
	1073	+{
	1074	+ int r, reg, size, val;
	1075	+ char buf[64];
	1076	+
	1077	+ r = sv->r;
	1078	+ if ((r & VT_VALMASK) == VT_CONST) {
	1079	+ if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
	1080	+ cstr_ccat(add_str, '$');
	1081	+ if (r & VT_SYM) {
	1082	+ cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
	1083	+ if (sv->c.i != 0) {
	1084	+ cstr_ccat(add_str, '+');
	1085	+ } else {
	1086	+ return;
	1087	+ }
	1088	+ }
	1089	+ val = sv->c.i;
	1090	+ if (modifier == 'n')
	1091	+ val = -val;
	1092	+ snprintf(buf, sizeof(buf), "%d", sv->c.i);
	1093	+ cstr_cat(add_str, buf);
	1094	+ } else if ((r & VT_VALMASK) == VT_LOCAL) {
	1095	+ snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
	1096	+ cstr_cat(add_str, buf);
	1097	+ } else if (r & VT_LVAL) {
	1098	+ reg = r & VT_VALMASK;
	1099	+ if (reg >= VT_CONST)
	1100	+ error("internal compiler error");
	1101	+ snprintf(buf, sizeof(buf), "(%%%s)",
	1102	+ get_tok_str(TOK_ASM_eax + reg, NULL));
	1103	+ cstr_cat(add_str, buf);
	1104	+ } else {
	1105	+ /* register case */
	1106	+ reg = r & VT_VALMASK;
	1107	+ if (reg >= VT_CONST)
	1108	+ error("internal compiler error");
	1109	+
	1110	+ /* choose register operand size */
	1111	+ if ((sv->type.t & VT_BTYPE) == VT_BYTE)
	1112	+ size = 1;
	1113	+ else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
	1114	+ size = 2;
	1115	+ else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
	1116	+ size = 8;
	1117	+ else
	1118	+ size = 4;
	1119	+ if (size == 1 && reg >= 4)
	1120	+ size = 4;
	1121	+
	1122	+ if (modifier == 'b') {
	1123	+ if (reg >= 4)
	1124	+ error("cannot use byte register");
	1125	+ size = 1;
	1126	+ } else if (modifier == 'h') {
	1127	+ if (reg >= 4)
	1128	+ error("cannot use byte register");
	1129	+ size = -1;
	1130	+ } else if (modifier == 'w') {
	1131	+ size = 2;
	1132	+ } else if (modifier == 'q') {
	1133	+ size = 8;
	1134	+ }
	1135	+
	1136	+ switch(size) {
	1137	+ case -1:
	1138	+ reg = TOK_ASM_ah + reg;
	1139	+ break;
	1140	+ case 1:
	1141	+ reg = TOK_ASM_al + reg;
	1142	+ break;
	1143	+ case 2:
	1144	+ reg = TOK_ASM_ax + reg;
	1145	+ break;
	1146	+ case 4:
	1147	+ reg = TOK_ASM_eax + reg;
	1148	+ break;
	1149	+ default:
	1150	+ reg = TOK_ASM_rax + reg;
	1151	+ break;
	1152	+ }
	1153	+ snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
	1154	+ cstr_cat(add_str, buf);
	1155	+ }
	1156	+}
	1157	+
	1158	+/* generate prolog and epilog code for asm statment */
	1159	+static void asm_gen_code(ASMOperand *operands, int nb_operands,
	1160	+ int nb_outputs, int is_output,
	1161	+ uint8_t *clobber_regs,
	1162	+ int out_reg)
	1163	+{
	1164	+ uint8_t regs_allocated[NB_ASM_REGS];
	1165	+ ASMOperand *op;
	1166	+ int i, reg;
	1167	+ static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
	1168	+
	1169	+ /* mark all used registers */
	1170	+ memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
	1171	+ for(i = 0; i < nb_operands;i++) {
	1172	+ op = &operands[i];
	1173	+ if (op->reg >= 0)
	1174	+ regs_allocated[op->reg] = 1;
	1175	+ }
	1176	+ if (!is_output) {
	1177	+ /* generate reg save code */
	1178	+ for(i = 0; i < NB_SAVED_REGS; i++) {
	1179	+ reg = reg_saved[i];
	1180	+ if (regs_allocated[reg])
	1181	+ g(0x50 + reg);
	1182	+ }
	1183	+
	1184	+ /* generate load code */
	1185	+ for(i = 0; i < nb_operands; i++) {
	1186	+ op = &operands[i];
	1187	+ if (op->reg >= 0) {
	1188	+ if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
	1189	+ op->is_memory) {
	1190	+ /* memory reference case (for both input and
	1191	+ output cases) */
	1192	+ SValue sv;
	1193	+ sv = *op->vt;
	1194	+ sv.r = (sv.r & ~VT_VALMASK) \| VT_LOCAL;
	1195	+ load(op->reg, &sv);
	1196	+ } else if (i >= nb_outputs \|\| op->is_rw) {
	1197	+ /* load value in register */
	1198	+ load(op->reg, op->vt);
	1199	+ if (op->is_llong) {
	1200	+ SValue sv;
	1201	+ sv = *op->vt;
	1202	+ sv.c.ul += 4;
	1203	+ load(TREG_RDX, &sv);
	1204	+ }
	1205	+ }
	1206	+ }
	1207	+ }
	1208	+ } else {
	1209	+ /* generate save code */
	1210	+ for(i = 0 ; i < nb_outputs; i++) {
	1211	+ op = &operands[i];
	1212	+ if (op->reg >= 0) {
	1213	+ if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
	1214	+ if (!op->is_memory) {
	1215	+ SValue sv;
	1216	+ sv = *op->vt;
	1217	+ sv.r = (sv.r & ~VT_VALMASK) \| VT_LOCAL;
	1218	+ load(out_reg, &sv);
	1219	+
	1220	+ sv.r = (sv.r & ~VT_VALMASK) \| out_reg;
	1221	+ store(op->reg, &sv);
	1222	+ }
	1223	+ } else {
	1224	+ store(op->reg, op->vt);
	1225	+ if (op->is_llong) {
	1226	+ SValue sv;
	1227	+ sv = *op->vt;
	1228	+ sv.c.ul += 4;
	1229	+ store(TREG_RDX, &sv);
	1230	+ }
	1231	+ }
	1232	+ }
	1233	+ }
	1234	+ /* generate reg restore code */
	1235	+ for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
	1236	+ reg = reg_saved[i];
	1237	+ if (regs_allocated[reg])
	1238	+ g(0x58 + reg);
	1239	+ }
	1240	+ }
	1241	+}
	1242	+
	1243	+static void asm_clobber(uint8_t clobber_regs, const char str)
	1244	+{
	1245	+ int reg;
	1246	+ TokenSym *ts;
	1247	+
	1248	+ if (!strcmp(str, "memory") \|\|
	1249	+ !strcmp(str, "cc"))
	1250	+ return;
	1251	+ ts = tok_alloc(str, strlen(str));
	1252	+ reg = ts->tok;
	1253	+ if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
	1254	+ reg -= TOK_ASM_rax;
	1255	+ } else if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
	1256	+ reg -= TOK_ASM_eax;
	1257	+ } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
	1258	+ reg -= TOK_ASM_ax;
	1259	+ } else {
	1260	+ error("invalid clobber register '%s'", str);
	1261	+ }
	1262	+ clobber_regs[reg] = 1;
	1263	+}

x86_64-asm.h+446−0

@@ -0,0 +1,446 @@
	1	+ DEF_ASM_OP0(clc, 0xf8) /* must be first OP0 */
	2	+ DEF_ASM_OP0(cld, 0xfc)
	3	+ DEF_ASM_OP0(cli, 0xfa)
	4	+ DEF_ASM_OP0(clts, 0x0f06)
	5	+ DEF_ASM_OP0(cmc, 0xf5)
	6	+ DEF_ASM_OP0(lahf, 0x9f)
	7	+ DEF_ASM_OP0(sahf, 0x9e)
	8	+ DEF_ASM_OP0(pushfl, 0x9c)
	9	+ DEF_ASM_OP0(popfl, 0x9d)
	10	+ DEF_ASM_OP0(pushf, 0x9c)
	11	+ DEF_ASM_OP0(popf, 0x9d)
	12	+ DEF_ASM_OP0(stc, 0xf9)
	13	+ DEF_ASM_OP0(std, 0xfd)
	14	+ DEF_ASM_OP0(sti, 0xfb)
	15	+ DEF_ASM_OP0(aaa, 0x37)
	16	+ DEF_ASM_OP0(aas, 0x3f)
	17	+ DEF_ASM_OP0(daa, 0x27)
	18	+ DEF_ASM_OP0(das, 0x2f)
	19	+ DEF_ASM_OP0(aad, 0xd50a)
	20	+ DEF_ASM_OP0(aam, 0xd40a)
	21	+ DEF_ASM_OP0(cbw, 0x6698)
	22	+ DEF_ASM_OP0(cwd, 0x6699)
	23	+ DEF_ASM_OP0(cwde, 0x98)
	24	+ DEF_ASM_OP0(cdq, 0x99)
	25	+ DEF_ASM_OP0(cbtw, 0x6698)
	26	+ DEF_ASM_OP0(cwtl, 0x98)
	27	+ DEF_ASM_OP0(cwtd, 0x6699)
	28	+ DEF_ASM_OP0(cltd, 0x99)
	29	+ DEF_ASM_OP0(int3, 0xcc)
	30	+ DEF_ASM_OP0(into, 0xce)
	31	+ DEF_ASM_OP0(iret, 0xcf)
	32	+ DEF_ASM_OP0(rsm, 0x0faa)
	33	+ DEF_ASM_OP0(hlt, 0xf4)
	34	+ DEF_ASM_OP0(wait, 0x9b)
	35	+ DEF_ASM_OP0(nop, 0x90)
	36	+ DEF_ASM_OP0(xlat, 0xd7)
	37	+
	38	+ /* strings */
	39	+ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWLQ))
	40	+ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWLQ))
	41	+
	42	+ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWLQ))
	43	+ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWLQ))
	44	+
	45	+ALT(DEF_ASM_OP0L(lodsb, 0xac, 0, OPC_BWLQ))
	46	+ALT(DEF_ASM_OP0L(slodb, 0xac, 0, OPC_BWLQ))
	47	+
	48	+ALT(DEF_ASM_OP0L(movsb, 0xa4, 0, OPC_BWLQ))
	49	+ALT(DEF_ASM_OP0L(smovb, 0xa4, 0, OPC_BWLQ))
	50	+
	51	+ALT(DEF_ASM_OP0L(scasb, 0xae, 0, OPC_BWLQ))
	52	+ALT(DEF_ASM_OP0L(sscab, 0xae, 0, OPC_BWLQ))
	53	+
	54	+ALT(DEF_ASM_OP0L(stosb, 0xaa, 0, OPC_BWLQ))
	55	+ALT(DEF_ASM_OP0L(sstob, 0xaa, 0, OPC_BWLQ))
	56	+
	57	+ /* bits */
	58	+
	59	+ALT(DEF_ASM_OP2(bsfw, 0x0fbc, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW \| OPT_EA, OPT_REGW))
	60	+ALT(DEF_ASM_OP2(bsrw, 0x0fbd, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW \| OPT_EA, OPT_REGW))
	61	+
	62	+ALT(DEF_ASM_OP2(btw, 0x0fa3, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_REGW \| OPT_EA))
	63	+ALT(DEF_ASM_OP2(btw, 0x0fba, 4, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW \| OPT_EA))
	64	+
	65	+ALT(DEF_ASM_OP2(btsw, 0x0fab, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_REGW \| OPT_EA))
	66	+ALT(DEF_ASM_OP2(btsw, 0x0fba, 5, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW \| OPT_EA))
	67	+
	68	+ALT(DEF_ASM_OP2(btrw, 0x0fb3, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_REGW \| OPT_EA))
	69	+ALT(DEF_ASM_OP2(btrw, 0x0fba, 6, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW \| OPT_EA))
	70	+
	71	+ALT(DEF_ASM_OP2(btcw, 0x0fbb, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_REGW \| OPT_EA))
	72	+ALT(DEF_ASM_OP2(btcw, 0x0fba, 7, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW \| OPT_EA))
	73	+
	74	+ /* prefixes */
	75	+ DEF_ASM_OP0(lock, 0xf0)
	76	+ DEF_ASM_OP0(rep, 0xf3)
	77	+ DEF_ASM_OP0(repe, 0xf3)
	78	+ DEF_ASM_OP0(repz, 0xf3)
	79	+ DEF_ASM_OP0(repne, 0xf2)
	80	+ DEF_ASM_OP0(repnz, 0xf2)
	81	+
	82	+ DEF_ASM_OP0(invd, 0x0f08)
	83	+ DEF_ASM_OP0(wbinvd, 0x0f09)
	84	+ DEF_ASM_OP0(cpuid, 0x0fa2)
	85	+ DEF_ASM_OP0(wrmsr, 0x0f30)
	86	+ DEF_ASM_OP0(rdtsc, 0x0f31)
	87	+ DEF_ASM_OP0(rdmsr, 0x0f32)
	88	+ DEF_ASM_OP0(rdpmc, 0x0f33)
	89	+ DEF_ASM_OP0(ud2, 0x0f0b)
	90	+
	91	+ /* NOTE: we took the same order as gas opcode definition order */
	92	+ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWLQ, OPT_ADDR, OPT_EAX))
	93	+ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR))
	94	+ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG))
	95	+ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
	96	+ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG \| OPC_BWLQ, OPT_IM, OPT_REG))
	97	+ALT(DEF_ASM_OP2(movb, 0xc6, 0, OPC_MODRM \| OPC_BWLQ, OPT_IM, OPT_REG \| OPT_EA))
	98	+
	99	+ALT(DEF_ASM_OP2(movw, 0x8c, 0, OPC_MODRM \| OPC_WLQ, OPT_SEG, OPT_EA \| OPT_REG))
	100	+ALT(DEF_ASM_OP2(movw, 0x8e, 0, OPC_MODRM \| OPC_WLQ, OPT_EA \| OPT_REG, OPT_SEG))
	101	+
	102	+ALT(DEF_ASM_OP2(movw, 0x0f20, 0, OPC_MODRM \| OPC_WLQ, OPT_CR, OPT_REG64))
	103	+ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM \| OPC_WLQ, OPT_DB, OPT_REG64))
	104	+ALT(DEF_ASM_OP2(movw, 0x0f24, 0, OPC_MODRM \| OPC_WLQ, OPT_TR, OPT_REG64))
	105	+ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_CR))
	106	+ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_DB))
	107	+ALT(DEF_ASM_OP2(movw, 0x0f26, 0, OPC_MODRM \| OPC_WLQ, OPT_REG64, OPT_TR))
	108	+
	109	+ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 \| OPT_EA, OPT_REG32))
	110	+ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM \| OPC_D16, OPT_REG8 \| OPT_EA, OPT_REG16))
	111	+ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 \| OPT_EA, OPT_REG32))
	112	+ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM \| OPC_WL, OPT_REG8 \| OPT_EA, OPT_REGW))
	113	+ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 \| OPT_EA, OPT_REG32))
	114	+
	115	+ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG \| OPC_WLQ, OPT_REG64))
	116	+ALT(DEF_ASM_OP1(pushw, 0xff, 6, OPC_MODRM \| OPC_WLQ, OPT_REG64 \| OPT_EA))
	117	+ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_WLQ, OPT_IM32))
	118	+ALT(DEF_ASM_OP1(pushw, 0x06, 0, OPC_WLQ, OPT_SEG))
	119	+ DEF_ASM_OP1(pushb, 0x6a, 0, OPC_B, OPT_IM8S)
	120	+
	121	+ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG \| OPC_WLQ, OPT_REGW))
	122	+ALT(DEF_ASM_OP1(popw, 0x8f, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW \| OPT_EA))
	123	+ALT(DEF_ASM_OP1(popw, 0x07, 0, OPC_WLQ, OPT_SEG))
	124	+
	125	+ALT(DEF_ASM_OP2(xchgw, 0x90, 0, OPC_REG \| OPC_WLQ, OPT_REG, OPT_EAX))
	126	+ALT(DEF_ASM_OP2(xchgw, 0x90, 0, OPC_REG \| OPC_WLQ, OPT_EAX, OPT_REG))
	127	+ALT(DEF_ASM_OP2(xchgb, 0x86, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG))
	128	+ALT(DEF_ASM_OP2(xchgb, 0x86, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
	129	+
	130	+ALT(DEF_ASM_OP2(inb, 0xe4, 0, OPC_BWL, OPT_IM8, OPT_EAX))
	131	+ALT(DEF_ASM_OP1(inb, 0xe4, 0, OPC_BWL, OPT_IM8))
	132	+ALT(DEF_ASM_OP2(inb, 0xec, 0, OPC_BWL, OPT_DX, OPT_EAX))
	133	+ALT(DEF_ASM_OP1(inb, 0xec, 0, OPC_BWL, OPT_DX))
	134	+
	135	+ALT(DEF_ASM_OP2(outb, 0xe6, 0, OPC_BWL, OPT_EAX, OPT_IM8))
	136	+ALT(DEF_ASM_OP1(outb, 0xe6, 0, OPC_BWL, OPT_IM8))
	137	+ALT(DEF_ASM_OP2(outb, 0xee, 0, OPC_BWL, OPT_EAX, OPT_DX))
	138	+ALT(DEF_ASM_OP1(outb, 0xee, 0, OPC_BWL, OPT_DX))
	139	+
	140	+ALT(DEF_ASM_OP2(leaw, 0x8d, 0, OPC_MODRM \| OPC_WLQ, OPT_EA, OPT_REG))
	141	+
	142	+ALT(DEF_ASM_OP2(les, 0xc4, 0, OPC_MODRM, OPT_EA, OPT_REG32))
	143	+ALT(DEF_ASM_OP2(lds, 0xc5, 0, OPC_MODRM, OPT_EA, OPT_REG32))
	144	+ALT(DEF_ASM_OP2(lss, 0x0fb2, 0, OPC_MODRM, OPT_EA, OPT_REG32))
	145	+ALT(DEF_ASM_OP2(lfs, 0x0fb4, 0, OPC_MODRM, OPT_EA, OPT_REG32))
	146	+ALT(DEF_ASM_OP2(lgs, 0x0fb5, 0, OPC_MODRM, OPT_EA, OPT_REG32))
	147	+
	148	+ /* arith */
	149	+ALT(DEF_ASM_OP2(addb, 0x00, 0, OPC_ARITH \| OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG)) /* XXX: use D bit ? */
	150	+ALT(DEF_ASM_OP2(addb, 0x02, 0, OPC_ARITH \| OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
	151	+ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH \| OPC_BWLQ, OPT_IMNO64, OPT_EAX))
	152	+ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH \| OPC_MODRM \| OPC_BWLQ, OPT_IMNO64, OPT_EA \| OPT_REG))
	153	+ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH \| OPC_MODRM \| OPC_WLQ, OPT_IM8S, OPT_EA \| OPT_REG))
	154	+
	155	+ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWLQ, OPT_EA \| OPT_REG, OPT_REG))
	156	+ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG, OPT_EA \| OPT_REG))
	157	+ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IMNO64, OPT_EAX))
	158	+ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM \| OPC_BWLQ, OPT_IMNO64, OPT_EA \| OPT_REG))
	159	+
	160	+ALT(DEF_ASM_OP1(incw, 0x40, 0, OPC_REG \| OPC_WLQ, OPT_REGW))
	161	+ALT(DEF_ASM_OP1(incb, 0xfe, 0, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	162	+ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG \| OPC_WLQ, OPT_REGW))
	163	+ALT(DEF_ASM_OP1(decb, 0xfe, 1, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	164	+
	165	+ALT(DEF_ASM_OP1(notb, 0xf6, 2, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	166	+ALT(DEF_ASM_OP1(negb, 0xf6, 3, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	167	+
	168	+ALT(DEF_ASM_OP1(mulb, 0xf6, 4, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	169	+ALT(DEF_ASM_OP1(imulb, 0xf6, 5, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	170	+
	171	+ALT(DEF_ASM_OP2(imulw, 0x0faf, 0, OPC_MODRM \| OPC_WLQ, OPT_REG \| OPT_EA, OPT_REG))
	172	+ALT(DEF_ASM_OP3(imulw, 0x6b, 0, OPC_MODRM \| OPC_WLQ, OPT_IM8S, OPT_REGW \| OPT_EA, OPT_REGW))
	173	+ALT(DEF_ASM_OP2(imulw, 0x6b, 0, OPC_MODRM \| OPC_WLQ, OPT_IM8S, OPT_REGW))
	174	+ALT(DEF_ASM_OP3(imulw, 0x69, 0, OPC_MODRM \| OPC_WLQ, OPT_IMW, OPT_REGW \| OPT_EA, OPT_REGW))
	175	+ALT(DEF_ASM_OP2(imulw, 0x69, 0, OPC_MODRM \| OPC_WLQ, OPT_IMW, OPT_REGW))
	176	+
	177	+ALT(DEF_ASM_OP1(divb, 0xf6, 6, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	178	+ALT(DEF_ASM_OP2(divb, 0xf6, 6, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA, OPT_EAX))
	179	+ALT(DEF_ASM_OP1(idivb, 0xf6, 7, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA))
	180	+ALT(DEF_ASM_OP2(idivb, 0xf6, 7, OPC_MODRM \| OPC_BWLQ, OPT_REG \| OPT_EA, OPT_EAX))
	181	+
	182	+ /* shifts */
	183	+ALT(DEF_ASM_OP2(rolb, 0xc0, 0, OPC_MODRM \| OPC_BWLQ \| OPC_SHIFT, OPT_IM8, OPT_EA \| OPT_REG))
	184	+ALT(DEF_ASM_OP2(rolb, 0xd2, 0, OPC_MODRM \| OPC_BWLQ \| OPC_SHIFT, OPT_CL, OPT_EA \| OPT_REG))
	185	+ALT(DEF_ASM_OP1(rolb, 0xd0, 0, OPC_MODRM \| OPC_BWLQ \| OPC_SHIFT, OPT_EA \| OPT_REG))
	186	+
	187	+ALT(DEF_ASM_OP3(shldw, 0x0fa4, 0, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW, OPT_EA \| OPT_REGW))
	188	+ALT(DEF_ASM_OP3(shldw, 0x0fa5, 0, OPC_MODRM \| OPC_WLQ, OPT_CL, OPT_REGW, OPT_EA \| OPT_REGW))
	189	+ALT(DEF_ASM_OP2(shldw, 0x0fa5, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_EA \| OPT_REGW))
	190	+ALT(DEF_ASM_OP3(shrdw, 0x0fac, 0, OPC_MODRM \| OPC_WLQ, OPT_IM8, OPT_REGW, OPT_EA \| OPT_REGW))
	191	+ALT(DEF_ASM_OP3(shrdw, 0x0fad, 0, OPC_MODRM \| OPC_WLQ, OPT_CL, OPT_REGW, OPT_EA \| OPT_REGW))
	192	+ALT(DEF_ASM_OP2(shrdw, 0x0fad, 0, OPC_MODRM \| OPC_WLQ, OPT_REGW, OPT_EA \| OPT_REGW))
	193	+
	194	+ALT(DEF_ASM_OP1(call, 0xff, 2, OPC_MODRM, OPT_INDIR))
	195	+ALT(DEF_ASM_OP1(call, 0xe8, 0, OPC_JMP, OPT_ADDR))
	196	+ALT(DEF_ASM_OP1(jmp, 0xff, 4, OPC_MODRM, OPT_INDIR))
	197	+ALT(DEF_ASM_OP1(jmp, 0xff, 0, OPC_JMP \| OPC_WL, OPT_REGW))
	198	+ALT(DEF_ASM_OP1(jmp, 0xeb, 0, OPC_SHORTJMP \| OPC_JMP, OPT_ADDR))
	199	+
	200	+ALT(DEF_ASM_OP1(lcall, 0xff, 3, 0, OPT_EA))
	201	+ALT(DEF_ASM_OP1(ljmp, 0xff, 5, 0, OPT_EA))
	202	+
	203	+ALT(DEF_ASM_OP1(int, 0xcd, 0, 0, OPT_IM8))
	204	+ALT(DEF_ASM_OP1(seto, 0x0f90, 0, OPC_MODRM \| OPC_TEST, OPT_REG8 \| OPT_EA))
	205	+ DEF_ASM_OP2(enter, 0xc8, 0, 0, OPT_IM16, OPT_IM8)
	206	+ DEF_ASM_OP0(leave, 0xc9)
	207	+ DEF_ASM_OP0(ret, 0xc3)
	208	+ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
	209	+ DEF_ASM_OP0(lret, 0xcb)
	210	+ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
	211	+
	212	+ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP \| OPC_JMP \| OPC_TEST, OPT_ADDR))
	213	+ DEF_ASM_OP1(loopne, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
	214	+ DEF_ASM_OP1(loopnz, 0xe0, 0, OPC_SHORTJMP, OPT_ADDR)
	215	+ DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
	216	+ DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
	217	+ DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
	218	+ DEF_ASM_OP1(jecxz, 0xe3, 0, OPC_SHORTJMP, OPT_ADDR)
	219	+
	220	+ /* float */
	221	+ /* specific fcomp handling */
	222	+ALT(DEF_ASM_OP0L(fcomp, 0xd8d9, 0, 0))
	223	+
	224	+ALT(DEF_ASM_OP1(fadd, 0xd8c0, 0, OPC_FARITH \| OPC_REG, OPT_ST))
	225	+ALT(DEF_ASM_OP2(fadd, 0xd8c0, 0, OPC_FARITH \| OPC_REG, OPT_ST, OPT_ST0))
	226	+ALT(DEF_ASM_OP0L(fadd, 0xdec1, 0, OPC_FARITH))
	227	+ALT(DEF_ASM_OP1(faddp, 0xdec0, 0, OPC_FARITH \| OPC_REG, OPT_ST))
	228	+ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH \| OPC_REG, OPT_ST, OPT_ST0))
	229	+ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH \| OPC_REG, OPT_ST0, OPT_ST))
	230	+ALT(DEF_ASM_OP0L(faddp, 0xdec1, 0, OPC_FARITH))
	231	+ALT(DEF_ASM_OP1(fadds, 0xd8, 0, OPC_FARITH \| OPC_MODRM, OPT_EA))
	232	+ALT(DEF_ASM_OP1(fiaddl, 0xda, 0, OPC_FARITH \| OPC_MODRM, OPT_EA))
	233	+ALT(DEF_ASM_OP1(faddl, 0xdc, 0, OPC_FARITH \| OPC_MODRM, OPT_EA))
	234	+ALT(DEF_ASM_OP1(fiadds, 0xde, 0, OPC_FARITH \| OPC_MODRM, OPT_EA))
	235	+
	236	+ DEF_ASM_OP0(fucompp, 0xdae9)
	237	+ DEF_ASM_OP0(ftst, 0xd9e4)
	238	+ DEF_ASM_OP0(fxam, 0xd9e5)
	239	+ DEF_ASM_OP0(fld1, 0xd9e8)
	240	+ DEF_ASM_OP0(fldl2t, 0xd9e9)
	241	+ DEF_ASM_OP0(fldl2e, 0xd9ea)
	242	+ DEF_ASM_OP0(fldpi, 0xd9eb)
	243	+ DEF_ASM_OP0(fldlg2, 0xd9ec)
	244	+ DEF_ASM_OP0(fldln2, 0xd9ed)
	245	+ DEF_ASM_OP0(fldz, 0xd9ee)
	246	+
	247	+ DEF_ASM_OP0(f2xm1, 0xd9f0)
	248	+ DEF_ASM_OP0(fyl2x, 0xd9f1)
	249	+ DEF_ASM_OP0(fptan, 0xd9f2)
	250	+ DEF_ASM_OP0(fpatan, 0xd9f3)
	251	+ DEF_ASM_OP0(fxtract, 0xd9f4)
	252	+ DEF_ASM_OP0(fprem1, 0xd9f5)
	253	+ DEF_ASM_OP0(fdecstp, 0xd9f6)
	254	+ DEF_ASM_OP0(fincstp, 0xd9f7)
	255	+ DEF_ASM_OP0(fprem, 0xd9f8)
	256	+ DEF_ASM_OP0(fyl2xp1, 0xd9f9)
	257	+ DEF_ASM_OP0(fsqrt, 0xd9fa)
	258	+ DEF_ASM_OP0(fsincos, 0xd9fb)
	259	+ DEF_ASM_OP0(frndint, 0xd9fc)
	260	+ DEF_ASM_OP0(fscale, 0xd9fd)
	261	+ DEF_ASM_OP0(fsin, 0xd9fe)
	262	+ DEF_ASM_OP0(fcos, 0xd9ff)
	263	+ DEF_ASM_OP0(fchs, 0xd9e0)
	264	+ DEF_ASM_OP0(fabs, 0xd9e1)
	265	+ DEF_ASM_OP0(fninit, 0xdbe3)
	266	+ DEF_ASM_OP0(fnclex, 0xdbe2)
	267	+ DEF_ASM_OP0(fnop, 0xd9d0)
	268	+ DEF_ASM_OP0(fwait, 0x9b)
	269	+
	270	+ /* fp load */
	271	+ DEF_ASM_OP1(fld, 0xd9c0, 0, OPC_REG, OPT_ST)
	272	+ DEF_ASM_OP1(fldl, 0xd9c0, 0, OPC_REG, OPT_ST)
	273	+ DEF_ASM_OP1(flds, 0xd9, 0, OPC_MODRM, OPT_EA)
	274	+ALT(DEF_ASM_OP1(fldl, 0xdd, 0, OPC_MODRM, OPT_EA))
	275	+ DEF_ASM_OP1(fildl, 0xdb, 0, OPC_MODRM, OPT_EA)
	276	+ DEF_ASM_OP1(fildq, 0xdf, 5, OPC_MODRM, OPT_EA)
	277	+ DEF_ASM_OP1(fildll, 0xdf, 5, OPC_MODRM,OPT_EA)
	278	+ DEF_ASM_OP1(fldt, 0xdb, 5, OPC_MODRM, OPT_EA)
	279	+ DEF_ASM_OP1(fbld, 0xdf, 4, OPC_MODRM, OPT_EA)
	280	+
	281	+ /* fp store */
	282	+ DEF_ASM_OP1(fst, 0xddd0, 0, OPC_REG, OPT_ST)
	283	+ DEF_ASM_OP1(fstl, 0xddd0, 0, OPC_REG, OPT_ST)
	284	+ DEF_ASM_OP1(fsts, 0xd9, 2, OPC_MODRM, OPT_EA)
	285	+ DEF_ASM_OP1(fstps, 0xd9, 3, OPC_MODRM, OPT_EA)
	286	+ALT(DEF_ASM_OP1(fstl, 0xdd, 2, OPC_MODRM, OPT_EA))
	287	+ DEF_ASM_OP1(fstpl, 0xdd, 3, OPC_MODRM, OPT_EA)
	288	+ DEF_ASM_OP1(fist, 0xdf, 2, OPC_MODRM, OPT_EA)
	289	+ DEF_ASM_OP1(fistp, 0xdf, 3, OPC_MODRM, OPT_EA)
	290	+ DEF_ASM_OP1(fistl, 0xdb, 2, OPC_MODRM, OPT_EA)
	291	+ DEF_ASM_OP1(fistpl, 0xdb, 3, OPC_MODRM, OPT_EA)
	292	+
	293	+ DEF_ASM_OP1(fstp, 0xddd8, 0, OPC_REG, OPT_ST)
	294	+ DEF_ASM_OP1(fistpq, 0xdf, 7, OPC_MODRM, OPT_EA)
	295	+ DEF_ASM_OP1(fistpll, 0xdf, 7, OPC_MODRM, OPT_EA)
	296	+ DEF_ASM_OP1(fstpt, 0xdb, 7, OPC_MODRM, OPT_EA)
	297	+ DEF_ASM_OP1(fbstp, 0xdf, 6, OPC_MODRM, OPT_EA)
	298	+
	299	+ /* exchange */
	300	+ DEF_ASM_OP0(fxch, 0xd9c9)
	301	+ALT(DEF_ASM_OP1(fxch, 0xd9c8, 0, OPC_REG, OPT_ST))
	302	+
	303	+ /* misc FPU */
	304	+ DEF_ASM_OP1(fucom, 0xdde0, 0, OPC_REG, OPT_ST )
	305	+ DEF_ASM_OP1(fucomp, 0xdde8, 0, OPC_REG, OPT_ST )
	306	+
	307	+ DEF_ASM_OP0L(finit, 0xdbe3, 0, OPC_FWAIT)
	308	+ DEF_ASM_OP1(fldcw, 0xd9, 5, OPC_MODRM, OPT_EA )
	309	+ DEF_ASM_OP1(fnstcw, 0xd9, 7, OPC_MODRM, OPT_EA )
	310	+ DEF_ASM_OP1(fstcw, 0xd9, 7, OPC_MODRM \| OPC_FWAIT, OPT_EA )
	311	+ DEF_ASM_OP0(fnstsw, 0xdfe0)
	312	+ALT(DEF_ASM_OP1(fnstsw, 0xdfe0, 0, 0, OPT_EAX ))
	313	+ALT(DEF_ASM_OP1(fnstsw, 0xdd, 7, OPC_MODRM, OPT_EA ))
	314	+ DEF_ASM_OP1(fstsw, 0xdfe0, 0, OPC_FWAIT, OPT_EAX )
	315	+ALT(DEF_ASM_OP0L(fstsw, 0xdfe0, 0, OPC_FWAIT))
	316	+ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM \| OPC_FWAIT, OPT_EA ))
	317	+ DEF_ASM_OP0L(fclex, 0xdbe2, 0, OPC_FWAIT)
	318	+ DEF_ASM_OP1(fnstenv, 0xd9, 6, OPC_MODRM, OPT_EA )
	319	+ DEF_ASM_OP1(fstenv, 0xd9, 6, OPC_MODRM \| OPC_FWAIT, OPT_EA )
	320	+ DEF_ASM_OP1(fldenv, 0xd9, 4, OPC_MODRM, OPT_EA )
	321	+ DEF_ASM_OP1(fnsave, 0xdd, 6, OPC_MODRM, OPT_EA )
	322	+ DEF_ASM_OP1(fsave, 0xdd, 6, OPC_MODRM \| OPC_FWAIT, OPT_EA )
	323	+ DEF_ASM_OP1(frstor, 0xdd, 4, OPC_MODRM, OPT_EA )
	324	+ DEF_ASM_OP1(ffree, 0xddc0, 4, OPC_REG, OPT_ST )
	325	+ DEF_ASM_OP1(ffreep, 0xdfc0, 4, OPC_REG, OPT_ST )
	326	+ DEF_ASM_OP1(fxsave, 0x0fae, 0, OPC_MODRM, OPT_EA )
	327	+ DEF_ASM_OP1(fxrstor, 0x0fae, 1, OPC_MODRM, OPT_EA )
	328	+
	329	+ /* segments */
	330	+ DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 \| OPT_EA)
	331	+ DEF_ASM_OP2(lar, 0x0f02, 0, OPC_MODRM, OPT_REG32 \| OPT_EA, OPT_REG32)
	332	+ DEF_ASM_OP1(lgdt, 0x0f01, 2, OPC_MODRM, OPT_EA)
	333	+ DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)
	334	+ DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA \| OPT_REG)
	335	+ DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA \| OPT_REG)
	336	+ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM \| OPC_WL, OPT_EA \| OPT_REG, OPT_REG))
	337	+ DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA \| OPT_REG)
	338	+ DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)
	339	+ DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)
	340	+ DEF_ASM_OP1(sldt, 0x0f00, 0, OPC_MODRM, OPT_REG \| OPT_EA)
	341	+ DEF_ASM_OP1(smsw, 0x0f01, 4, OPC_MODRM, OPT_REG \| OPT_EA)
	342	+ DEF_ASM_OP1(str, 0x0f00, 1, OPC_MODRM, OPT_REG16\| OPT_EA)
	343	+ DEF_ASM_OP1(verr, 0x0f00, 4, OPC_MODRM, OPT_REG \| OPT_EA)
	344	+ DEF_ASM_OP1(verw, 0x0f00, 5, OPC_MODRM, OPT_REG \| OPT_EA)
	345	+
	346	+ /* 486 */
	347	+ DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )
	348	+ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM \| OPC_BWL, OPT_REG, OPT_REG \| OPT_EA ))
	349	+ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM \| OPC_BWL, OPT_REG, OPT_REG \| OPT_EA ))
	350	+ DEF_ASM_OP1(invlpg, 0x0f01, 7, OPC_MODRM, OPT_EA )
	351	+
	352	+ DEF_ASM_OP2(boundl, 0x62, 0, OPC_MODRM, OPT_REG32, OPT_EA)
	353	+ DEF_ASM_OP2(boundw, 0x62, 0, OPC_MODRM \| OPC_D16, OPT_REG16, OPT_EA)
	354	+
	355	+ /* pentium */
	356	+ DEF_ASM_OP1(cmpxchg8b, 0x0fc7, 1, OPC_MODRM, OPT_EA )
	357	+
	358	+ /* pentium pro */
	359	+ALT(DEF_ASM_OP2(cmovo, 0x0f40, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	360	+ALT(DEF_ASM_OP2(cmovno, 0x0f41, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	361	+ALT(DEF_ASM_OP2(cmovc, 0x0f42, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	362	+ALT(DEF_ASM_OP2(cmovnc, 0x0f43, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	363	+ALT(DEF_ASM_OP2(cmovz, 0x0f44, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	364	+ALT(DEF_ASM_OP2(cmovnz, 0x0f45, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	365	+ALT(DEF_ASM_OP2(cmovna, 0x0f46, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	366	+ALT(DEF_ASM_OP2(cmova, 0x0f47, 0, OPC_MODRM \| OPC_TEST, OPT_REG32 \| OPT_EA, OPT_REG32))
	367	+
	368	+ DEF_ASM_OP2(fcmovb, 0xdac0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	369	+ DEF_ASM_OP2(fcmove, 0xdac8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	370	+ DEF_ASM_OP2(fcmovbe, 0xdad0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	371	+ DEF_ASM_OP2(fcmovu, 0xdad8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	372	+ DEF_ASM_OP2(fcmovnb, 0xdbc0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	373	+ DEF_ASM_OP2(fcmovne, 0xdbc8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	374	+ DEF_ASM_OP2(fcmovnbe, 0xdbd0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	375	+ DEF_ASM_OP2(fcmovnu, 0xdbd8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	376	+
	377	+ DEF_ASM_OP2(fucomi, 0xdbe8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	378	+ DEF_ASM_OP2(fcomi, 0xdbf0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	379	+ DEF_ASM_OP2(fucomip, 0xdfe8, 0, OPC_REG, OPT_ST, OPT_ST0 )
	380	+ DEF_ASM_OP2(fcomip, 0xdff0, 0, OPC_REG, OPT_ST, OPT_ST0 )
	381	+
	382	+ /* mmx */
	383	+ DEF_ASM_OP0(emms, 0x0f77) /* must be last OP0 */
	384	+ DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA \| OPT_REG32, OPT_MMX )
	385	+ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMX, OPT_EA \| OPT_REG32 ))
	386	+ALT(DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX ))
	387	+ALT(DEF_ASM_OP2(movq, 0x0f7f, 0, OPC_MODRM, OPT_MMX, OPT_EA \| OPT_MMX ))
	388	+ DEF_ASM_OP2(packssdw, 0x0f6b, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	389	+ DEF_ASM_OP2(packsswb, 0x0f63, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	390	+ DEF_ASM_OP2(packuswb, 0x0f67, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	391	+ DEF_ASM_OP2(paddb, 0x0ffc, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	392	+ DEF_ASM_OP2(paddw, 0x0ffd, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	393	+ DEF_ASM_OP2(paddd, 0x0ffe, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	394	+ DEF_ASM_OP2(paddsb, 0x0fec, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	395	+ DEF_ASM_OP2(paddsw, 0x0fed, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	396	+ DEF_ASM_OP2(paddusb, 0x0fdc, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	397	+ DEF_ASM_OP2(paddusw, 0x0fdd, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	398	+ DEF_ASM_OP2(pand, 0x0fdb, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	399	+ DEF_ASM_OP2(pandn, 0x0fdf, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	400	+ DEF_ASM_OP2(pcmpeqb, 0x0f74, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	401	+ DEF_ASM_OP2(pcmpeqw, 0x0f75, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	402	+ DEF_ASM_OP2(pcmpeqd, 0x0f76, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	403	+ DEF_ASM_OP2(pcmpgtb, 0x0f64, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	404	+ DEF_ASM_OP2(pcmpgtw, 0x0f65, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	405	+ DEF_ASM_OP2(pcmpgtd, 0x0f66, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	406	+ DEF_ASM_OP2(pmaddwd, 0x0ff5, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	407	+ DEF_ASM_OP2(pmulhw, 0x0fe5, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	408	+ DEF_ASM_OP2(pmullw, 0x0fd5, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	409	+ DEF_ASM_OP2(por, 0x0feb, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	410	+ DEF_ASM_OP2(psllw, 0x0ff1, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	411	+ALT(DEF_ASM_OP2(psllw, 0x0f71, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
	412	+ DEF_ASM_OP2(pslld, 0x0ff2, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	413	+ALT(DEF_ASM_OP2(pslld, 0x0f72, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
	414	+ DEF_ASM_OP2(psllq, 0x0ff3, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	415	+ALT(DEF_ASM_OP2(psllq, 0x0f73, 6, OPC_MODRM, OPT_IM8, OPT_MMX ))
	416	+ DEF_ASM_OP2(psraw, 0x0fe1, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	417	+ALT(DEF_ASM_OP2(psraw, 0x0f71, 4, OPC_MODRM, OPT_IM8, OPT_MMX ))
	418	+ DEF_ASM_OP2(psrad, 0x0fe2, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	419	+ALT(DEF_ASM_OP2(psrad, 0x0f72, 4, OPC_MODRM, OPT_IM8, OPT_MMX ))
	420	+ DEF_ASM_OP2(psrlw, 0x0fd1, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	421	+ALT(DEF_ASM_OP2(psrlw, 0x0f71, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
	422	+ DEF_ASM_OP2(psrld, 0x0fd2, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	423	+ALT(DEF_ASM_OP2(psrld, 0x0f72, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
	424	+ DEF_ASM_OP2(psrlq, 0x0fd3, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	425	+ALT(DEF_ASM_OP2(psrlq, 0x0f73, 2, OPC_MODRM, OPT_IM8, OPT_MMX ))
	426	+ DEF_ASM_OP2(psubb, 0x0ff8, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	427	+ DEF_ASM_OP2(psubw, 0x0ff9, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	428	+ DEF_ASM_OP2(psubd, 0x0ffa, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	429	+ DEF_ASM_OP2(psubsb, 0x0fe8, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	430	+ DEF_ASM_OP2(psubsw, 0x0fe9, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	431	+ DEF_ASM_OP2(psubusb, 0x0fd8, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	432	+ DEF_ASM_OP2(psubusw, 0x0fd9, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	433	+ DEF_ASM_OP2(punpckhbw, 0x0f68, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	434	+ DEF_ASM_OP2(punpckhwd, 0x0f69, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	435	+ DEF_ASM_OP2(punpckhdq, 0x0f6a, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	436	+ DEF_ASM_OP2(punpcklbw, 0x0f60, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	437	+ DEF_ASM_OP2(punpcklwd, 0x0f61, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	438	+ DEF_ASM_OP2(punpckldq, 0x0f62, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	439	+ DEF_ASM_OP2(pxor, 0x0fef, 0, OPC_MODRM, OPT_EA \| OPT_MMX, OPT_MMX )
	440	+
	441	+#undef ALT
	442	+#undef DEF_ASM_OP0
	443	+#undef DEF_ASM_OP0L
	444	+#undef DEF_ASM_OP1
	445	+#undef DEF_ASM_OP2
	446	+#undef DEF_ASM_OP3

x86_64-tok.h+224−0

@@ -0,0 +1,224 @@
	1	+
	2	+/* WARNING: relative order of tokens is important. */
	3	+ DEF_ASM(al)
	4	+ DEF_ASM(cl)
	5	+ DEF_ASM(dl)
	6	+ DEF_ASM(bl)
	7	+ DEF_ASM(ah)
	8	+ DEF_ASM(ch)
	9	+ DEF_ASM(dh)
	10	+ DEF_ASM(bh)
	11	+ DEF_ASM(ax)
	12	+ DEF_ASM(cx)
	13	+ DEF_ASM(dx)
	14	+ DEF_ASM(bx)
	15	+ DEF_ASM(sp)
	16	+ DEF_ASM(bp)
	17	+ DEF_ASM(si)
	18	+ DEF_ASM(di)
	19	+ DEF_ASM(eax)
	20	+ DEF_ASM(ecx)
	21	+ DEF_ASM(edx)
	22	+ DEF_ASM(ebx)
	23	+ DEF_ASM(esp)
	24	+ DEF_ASM(ebp)
	25	+ DEF_ASM(esi)
	26	+ DEF_ASM(edi)
	27	+ DEF_ASM(rax)
	28	+ DEF_ASM(rcx)
	29	+ DEF_ASM(rdx)
	30	+ DEF_ASM(rbx)
	31	+ DEF_ASM(rsp)
	32	+ DEF_ASM(rbp)
	33	+ DEF_ASM(rsi)
	34	+ DEF_ASM(rdi)
	35	+ DEF_ASM(mm0)
	36	+ DEF_ASM(mm1)
	37	+ DEF_ASM(mm2)
	38	+ DEF_ASM(mm3)
	39	+ DEF_ASM(mm4)
	40	+ DEF_ASM(mm5)
	41	+ DEF_ASM(mm6)
	42	+ DEF_ASM(mm7)
	43	+ DEF_ASM(xmm0)
	44	+ DEF_ASM(xmm1)
	45	+ DEF_ASM(xmm2)
	46	+ DEF_ASM(xmm3)
	47	+ DEF_ASM(xmm4)
	48	+ DEF_ASM(xmm5)
	49	+ DEF_ASM(xmm6)
	50	+ DEF_ASM(xmm7)
	51	+ DEF_ASM(cr0)
	52	+ DEF_ASM(cr1)
	53	+ DEF_ASM(cr2)
	54	+ DEF_ASM(cr3)
	55	+ DEF_ASM(cr4)
	56	+ DEF_ASM(cr5)
	57	+ DEF_ASM(cr6)
	58	+ DEF_ASM(cr7)
	59	+ DEF_ASM(tr0)
	60	+ DEF_ASM(tr1)
	61	+ DEF_ASM(tr2)
	62	+ DEF_ASM(tr3)
	63	+ DEF_ASM(tr4)
	64	+ DEF_ASM(tr5)
	65	+ DEF_ASM(tr6)
	66	+ DEF_ASM(tr7)
	67	+ DEF_ASM(db0)
	68	+ DEF_ASM(db1)
	69	+ DEF_ASM(db2)
	70	+ DEF_ASM(db3)
	71	+ DEF_ASM(db4)
	72	+ DEF_ASM(db5)
	73	+ DEF_ASM(db6)
	74	+ DEF_ASM(db7)
	75	+ DEF_ASM(dr0)
	76	+ DEF_ASM(dr1)
	77	+ DEF_ASM(dr2)
	78	+ DEF_ASM(dr3)
	79	+ DEF_ASM(dr4)
	80	+ DEF_ASM(dr5)
	81	+ DEF_ASM(dr6)
	82	+ DEF_ASM(dr7)
	83	+ DEF_ASM(es)
	84	+ DEF_ASM(cs)
	85	+ DEF_ASM(ss)
	86	+ DEF_ASM(ds)
	87	+ DEF_ASM(fs)
	88	+ DEF_ASM(gs)
	89	+ DEF_ASM(st)
	90	+
	91	+ DEF_BWLQ(mov)
	92	+
	93	+ /* generic two operands */
	94	+ DEF_BWLQ(add)
	95	+ DEF_BWLQ(or)
	96	+ DEF_BWLQ(adc)
	97	+ DEF_BWLQ(sbb)
	98	+ DEF_BWLQ(and)
	99	+ DEF_BWLQ(sub)
	100	+ DEF_BWLQ(xor)
	101	+ DEF_BWLQ(cmp)
	102	+
	103	+ /* unary ops */
	104	+ DEF_BWLQ(inc)
	105	+ DEF_BWLQ(dec)
	106	+ DEF_BWLQ(not)
	107	+ DEF_BWLQ(neg)
	108	+ DEF_BWLQ(mul)
	109	+ DEF_BWLQ(imul)
	110	+ DEF_BWLQ(div)
	111	+ DEF_BWLQ(idiv)
	112	+
	113	+ DEF_BWLQ(xchg)
	114	+ DEF_BWLQ(test)
	115	+
	116	+ /* shifts */
	117	+ DEF_BWLQ(rol)
	118	+ DEF_BWLQ(ror)
	119	+ DEF_BWLQ(rcl)
	120	+ DEF_BWLQ(rcr)
	121	+ DEF_BWLQ(shl)
	122	+ DEF_BWLQ(shr)
	123	+ DEF_BWLQ(sar)
	124	+
	125	+ DEF_ASM(shldw)
	126	+ DEF_ASM(shldl)
	127	+ DEF_ASM(shld)
	128	+ DEF_ASM(shrdw)
	129	+ DEF_ASM(shrdl)
	130	+ DEF_ASM(shrd)
	131	+
	132	+ DEF_ASM(pushw)
	133	+ DEF_ASM(pushl)
	134	+ DEF_ASM(pushq)
	135	+ DEF_ASM(push)
	136	+ DEF_ASM(popw)
	137	+ DEF_ASM(popl)
	138	+ DEF_ASM(popq)
	139	+ DEF_ASM(pop)
	140	+ DEF_BWL(in)
	141	+ DEF_BWL(out)
	142	+
	143	+ DEF_WL(movzb)
	144	+
	145	+ DEF_ASM(movzwl)
	146	+ DEF_ASM(movsbw)
	147	+ DEF_ASM(movsbl)
	148	+ DEF_ASM(movswl)
	149	+
	150	+ DEF_WLQ(lea)
	151	+
	152	+ DEF_ASM(les)
	153	+ DEF_ASM(lds)
	154	+ DEF_ASM(lss)
	155	+ DEF_ASM(lfs)
	156	+ DEF_ASM(lgs)
	157	+
	158	+ DEF_ASM(call)
	159	+ DEF_ASM(jmp)
	160	+ DEF_ASM(lcall)
	161	+ DEF_ASM(ljmp)
	162	+
	163	+ DEF_ASMTEST(j)
	164	+
	165	+ DEF_ASMTEST(set)
	166	+ DEF_ASMTEST(cmov)
	167	+
	168	+ DEF_WLQ(bsf)
	169	+ DEF_WLQ(bsr)
	170	+ DEF_WLQ(bt)
	171	+ DEF_WLQ(bts)
	172	+ DEF_WLQ(btr)
	173	+ DEF_WLQ(btc)
	174	+
	175	+ DEF_WLQ(lsl)
	176	+
	177	+ /* generic FP ops */
	178	+ DEF_FP(add)
	179	+ DEF_FP(mul)
	180	+
	181	+ DEF_ASM(fcom)
	182	+ DEF_ASM(fcom_1) /* non existant op, just to have a regular table */
	183	+ DEF_FP1(com)
	184	+
	185	+ DEF_FP(comp)
	186	+ DEF_FP(sub)
	187	+ DEF_FP(subr)
	188	+ DEF_FP(div)
	189	+ DEF_FP(divr)
	190	+
	191	+ DEF_BWLQ(xadd)
	192	+ DEF_BWLQ(cmpxchg)
	193	+
	194	+ /* string ops */
	195	+ DEF_BWLQ(cmps)
	196	+ DEF_BWLQ(scmp)
	197	+ DEF_BWL(ins)
	198	+ DEF_BWL(outs)
	199	+ DEF_BWLQ(lods)
	200	+ DEF_BWLQ(slod)
	201	+ DEF_BWLQ(movs)
	202	+ DEF_BWLQ(smov)
	203	+ DEF_BWLQ(scas)
	204	+ DEF_BWLQ(ssca)
	205	+ DEF_BWLQ(stos)
	206	+ DEF_BWLQ(ssto)
	207	+
	208	+ /* generic asm ops */
	209	+
	210	+#define ALT(x)
	211	+#define DEF_ASM_OP0(name, opcode) DEF_ASM(name)
	212	+#define DEF_ASM_OP0L(name, opcode, group, instr_type)
	213	+#define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
	214	+#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
	215	+#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
	216	+#include "x86_64-asm.h"
	217	+
	218	+#define ALT(x)
	219	+#define DEF_ASM_OP0(name, opcode)
	220	+#define DEF_ASM_OP0L(name, opcode, group, instr_type) DEF_ASM(name)
	221	+#define DEF_ASM_OP1(name, opcode, group, instr_type, op0) DEF_ASM(name)
	222	+#define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) DEF_ASM(name)
	223	+#define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) DEF_ASM(name)
	224	+#include "x86_64-asm.h"

first support of x86_64 assembly

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