This code was inactive since a long time (and was deactivated because it was wrong to start with) and just clutters the sources. Remove it.
Unified · Split
| @@ -244,10 +244,6 @@ static const uint16_t op0_codes[] = { · 243 unmodified lines | ||
| 244 | 244 | static inline int get_reg_shift(TCCState *s1) |
| 245 | 245 | { |
| 246 | 246 | int shift, v; |
| 247 | −#ifdef I386_ASM_16 | |
| 248 | − if (s1->seg_size == 16) | |
| 249 | − tcc_error("invalid effective address"); | |
| 250 | −#endif | |
| 251 | 247 | v = asm_int_expr(s1); |
| 252 | 248 | switch(v) { |
| 253 | 249 | case 1: |
| @@ -283,10 +279,6 @@ static int asm_parse_reg(int *type) · 29 unmodified lines | ||
| 283 | 279 | *type = OP_EA32; |
| 284 | 280 | } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) { |
| 285 | 281 | reg = tok - TOK_ASM_rax; |
| 286 | −#endif | |
| 287 | −#ifdef I386_ASM_16 | |
| 288 | − } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) { | |
| 289 | − reg = tok - TOK_ASM_ax; | |
| 290 | 282 | #endif |
| 291 | 283 | } else { |
| 292 | 284 | error_32: |
| @@ -454,37 +446,6 @@ static void gen_disp32(ExprValue *pe) · 161 unmodified lines | ||
| 454 | 446 | } |
| 455 | 447 | } |
| 456 | 448 | |
| 457 | −#ifdef I386_ASM_16 | |
| 458 | −static void gen_expr16(ExprValue *pe) | |
| 459 | −{ | |
| 460 | − if (pe->sym) | |
| 461 | − greloc(cur_text_section, pe->sym, ind, R_386_16); | |
| 462 | − gen_le16(pe->v); | |
| 463 | −} | |
| 464 | −static void gen_disp16(ExprValue *pe) | |
| 465 | −{ | |
| 466 | − Sym *sym; | |
| 467 | − sym = pe->sym; | |
| 468 | − if (sym) { | |
| 469 | − if (sym->r == cur_text_section->sh_num) { | |
| 470 | − /* same section: we can output an absolute value. Note | |
| 471 | − that the TCC compiler behaves differently here because | |
| 472 | − it always outputs a relocation to ease (future) code | |
| 473 | − elimination in the linker */ | |
| 474 | − gen_le16(pe->v + sym->jnext - ind - 2); | |
| 475 | − } else { | |
| 476 | − greloc(cur_text_section, sym, ind, R_386_PC16); | |
| 477 | − gen_le16(pe->v - 2); | |
| 478 | − } | |
| 479 | − } else { | |
| 480 | − /* put an empty PC32 relocation */ | |
| 481 | − put_elf_reloc(symtab_section, cur_text_section, | |
| 482 | − ind, R_386_PC16, 0); | |
| 483 | − gen_le16(pe->v - 2); | |
| 484 | − } | |
| 485 | −} | |
| 486 | −#endif | |
| 487 | − | |
| 488 | 449 | /* generate the modrm operand */ |
| 489 | 450 | static inline void asm_modrm(int reg, Operand *op) |
| 490 | 451 | { |
| @@ -494,21 +455,13 @@ static inline void asm_modrm(int reg, Operand *op) · 3 unmodified lines | ||
| 494 | 455 | g(0xc0 + (reg << 3) + op->reg); |
| 495 | 456 | } else if (op->reg == -1 && op->reg2 == -1) { |
| 496 | 457 | /* displacement only */ |
| 497 | −#ifdef I386_ASM_16 | |
| 498 | − if (tcc_state->seg_size == 16) { | |
| 499 | − g(0x06 + (reg << 3)); | |
| 500 | − gen_expr16(&op->e); | |
| 501 | − } else if (tcc_state->seg_size == 32) | |
| 502 | −#endif | |
| 503 | − { | |
| 504 | 458 | #ifdef TCC_TARGET_X86_64 |
| 505 | − g(0x04 + (reg << 3)); | |
| 506 | − g(0x25); | |
| 459 | + g(0x04 + (reg << 3)); | |
| 460 | + g(0x25); | |
| 507 | 461 | #else |
| 508 | − g(0x05 + (reg << 3)); | |
| 462 | + g(0x05 + (reg << 3)); | |
| 509 | 463 | #endif |
| 510 | − gen_expr32(&op->e); | |
| 511 | − } | |
| 464 | + gen_expr32(&op->e); | |
| 512 | 465 | } else { |
| 513 | 466 | sib_reg1 = op->reg; |
| 514 | 467 | /* fist compute displacement encoding */ |
| @@ -526,9 +479,6 @@ static inline void asm_modrm(int reg, Operand *op) · 11 unmodified lines | ||
| 526 | 479 | reg1 = op->reg; |
| 527 | 480 | if (op->reg2 != -1) |
| 528 | 481 | reg1 = 4; |
| 529 | −#ifdef I386_ASM_16 | |
| 530 | − if (tcc_state->seg_size == 32) { | |
| 531 | −#endif | |
| 532 | 482 | g(mod + (reg << 3) + reg1); |
| 533 | 483 | if (reg1 == 4) { |
| 534 | 484 | /* add sib byte */ |
| @@ -537,53 +487,11 @@ static inline void asm_modrm(int reg, Operand *op) · 2 unmodified lines | ||
| 537 | 487 | reg2 = 4; /* indicate no index */ |
| 538 | 488 | g((op->shift << 6) + (reg2 << 3) + sib_reg1); |
| 539 | 489 | } |
| 540 | −#ifdef I386_ASM_16 | |
| 541 | − } else if (tcc_state->seg_size == 16) { | |
| 542 | − /* edi = 7, esi = 6 --> di = 5, si = 4 */ | |
| 543 | − if ((reg1 == 6) || (reg1 == 7)) { | |
| 544 | − reg1 -= 2; | |
| 545 | − /* ebx = 3 --> bx = 7 */ | |
| 546 | − } else if (reg1 == 3) { | |
| 547 | − reg1 = 7; | |
| 548 | − /* o32 = 5 --> o16 = 6 */ | |
| 549 | − } else if (reg1 == 5) { | |
| 550 | − reg1 = 6; | |
| 551 | − /* sib not valid in 16-bit mode */ | |
| 552 | − } else if (reg1 == 4) { | |
| 553 | − reg2 = op->reg2; | |
| 554 | − /* bp + si + offset */ | |
| 555 | − if ((sib_reg1 == 5) && (reg2 == 6)) { | |
| 556 | − reg1 = 2; | |
| 557 | − /* bp + di + offset */ | |
| 558 | − } else if ((sib_reg1 == 5) && (reg2 == 7)) { | |
| 559 | − reg1 = 3; | |
| 560 | − /* bx + si + offset */ | |
| 561 | − } else if ((sib_reg1 == 3) && (reg2 == 6)) { | |
| 562 | − reg1 = 0; | |
| 563 | − /* bx + di + offset */ | |
| 564 | − } else if ((sib_reg1 == 3) && (reg2 == 7)) { | |
| 565 | − reg1 = 1; | |
| 566 | − } else { | |
| 567 | − tcc_error("invalid effective address"); | |
| 568 | − } | |
| 569 | − if (op->e.v == 0) | |
| 570 | − mod = 0; | |
| 571 | − } else { | |
| 572 | − tcc_error("invalid register"); | |
| 573 | − } | |
| 574 | − g(mod + (reg << 3) + reg1); | |
| 575 | − } | |
| 576 | −#endif | |
| 577 | 490 | /* add offset */ |
| 578 | 491 | if (mod == 0x40) { |
| 579 | 492 | g(op->e.v); |
| 580 | 493 | } else if (mod == 0x80 || op->reg == -1) { |
| 581 | −#ifdef I386_ASM_16 | |
| 582 | − if (tcc_state->seg_size == 16) | |
| 583 | − gen_expr16(&op->e); | |
| 584 | − else if (tcc_state->seg_size == 32) | |
| 585 | −#endif | |
| 586 | − gen_expr32(&op->e); | |
| 494 | + gen_expr32(&op->e); | |
| 587 | 495 | } |
| 588 | 496 | } |
| 589 | 497 | } |
| @@ -597,9 +505,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 7 unmodified lines | ||
| 597 | 505 | int op_type[3]; /* decoded op type */ |
| 598 | 506 | int alltypes; /* OR of all operand types */ |
| 599 | 507 | int autosize; |
| 600 | −#ifdef I386_ASM_16 | |
| 601 | − static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0; | |
| 602 | −#endif | |
| 603 | 508 | |
| 604 | 509 | /* force synthetic ';' after prefix instruction, so we can handle */ |
| 605 | 510 | /* one-line things like "rep stosb" instead of only "rep\nstosb" */ |
| @@ -624,11 +529,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 18 unmodified lines | ||
| 624 | 529 | seg_prefix = segment_prefixes[pop->reg]; |
| 625 | 530 | next(); |
| 626 | 531 | parse_operand(s1, pop); |
| 627 | −#ifndef I386_ASM_16 | |
| 628 | 532 | if (!(pop->type & OP_EA)) { |
| 629 | 533 | tcc_error("segment prefix must be followed by memory reference"); |
| 630 | 534 | } |
| 631 | −#endif | |
| 632 | 535 | } |
| 633 | 536 | pop++; |
| 634 | 537 | nb_ops++; |
| @@ -728,19 +631,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 93 unmodified lines | ||
| 728 | 631 | if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) { |
| 729 | 632 | int b; |
| 730 | 633 | b = op0_codes[opcode - TOK_ASM_first]; |
| 731 | −#ifdef I386_ASM_16 | |
| 732 | − if (opcode == TOK_ASM_o32) { | |
| 733 | − if (s1->seg_size == 32) | |
| 734 | − tcc_error("incorrect prefix"); | |
| 735 | − else | |
| 736 | − o32 = data32 = 1; | |
| 737 | − } else if (opcode == TOK_ASM_a32) { | |
| 738 | − if (s1->seg_size == 32) | |
| 739 | − tcc_error("incorrect prefix"); | |
| 740 | − else | |
| 741 | − a32 = addr32 = 1; | |
| 742 | − } | |
| 743 | −#endif | |
| 744 | 634 | if (b & 0xff00) |
| 745 | 635 | g(b >> 8); |
| 746 | 636 | g(b); |
| @@ -775,37 +665,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 28 unmodified lines | ||
| 775 | 665 | } |
| 776 | 666 | } |
| 777 | 667 | |
| 778 | −#ifdef I386_ASM_16 | |
| 779 | − for(i = 0; i < nb_ops; i++) { | |
| 780 | − if (ops[i].type & OP_REG32) { | |
| 781 | − if (s1->seg_size == 16) | |
| 782 | − o32 = 1; | |
| 783 | − } else if (!(ops[i].type & OP_REG32)) { | |
| 784 | − if (s1->seg_size == 32) | |
| 785 | − o32 = 1; | |
| 786 | − } | |
| 787 | − } | |
| 788 | − | |
| 789 | − | |
| 790 | − if (s == 1 || (pa->instr_type & OPC_D16)) { | |
| 791 | − if (s1->seg_size == 32) | |
| 792 | − o32 = 1; | |
| 793 | − } else if (s == 2) { | |
| 794 | − if (s1->seg_size == 16) { | |
| 795 | − if (!(pa->instr_type & OPC_D16)) | |
| 796 | − o32 = 1; | |
| 797 | − } | |
| 798 | − } | |
| 799 | − | |
| 800 | − /* generate a16/a32 prefix if needed */ | |
| 801 | − if ((a32 == 1) && (addr32 == 0)) | |
| 802 | − g(0x67); | |
| 803 | − /* generate o16/o32 prefix if needed */ | |
| 804 | − if ((o32 == 1) && (data32 == 0)) | |
| 805 | − g(0x66); | |
| 806 | − | |
| 807 | − addr32 = data32 = 0; | |
| 808 | −#else | |
| 809 | 668 | #ifdef TCC_TARGET_X86_64 |
| 810 | 669 | /* Generate addr32 prefix if needed */ |
| 811 | 670 | for(i = 0; i < nb_ops; i++) { |
| @@ -840,7 +699,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 28 unmodified lines | ||
| 840 | 699 | && !default64) |
| 841 | 700 | g(0x48); |
| 842 | 701 | } |
| 843 | −#endif | |
| 844 | 702 | #endif |
| 845 | 703 | |
| 846 | 704 | /* now generates the operation */ |
| @@ -969,12 +827,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 122 unmodified lines | ||
| 969 | 827 | #ifndef TCC_TARGET_X86_64 |
| 970 | 828 | if (pa->opcode == 0x9a || pa->opcode == 0xea) { |
| 971 | 829 | /* ljmp or lcall kludge */ |
| 972 | −#ifdef I386_ASM_16 | |
| 973 | − if (s1->seg_size == 16 && o32 == 0) | |
| 974 | − gen_expr16(&ops[1].e); | |
| 975 | − else | |
| 976 | −#endif | |
| 977 | − gen_expr32(&ops[1].e); | |
| 830 | + gen_expr32(&ops[1].e); | |
| 978 | 831 | if (ops[0].e.sym) |
| 979 | 832 | tcc_error("cannot relocate"); |
| 980 | 833 | gen_le16(ops[0].e.v); |
| @@ -1001,11 +854,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 20 unmodified lines | ||
| 1001 | 854 | goto error_relocate; |
| 1002 | 855 | g(ops[i].e.v); |
| 1003 | 856 | } else if (v & OP_IM16) { |
| 1004 | −#ifdef I386_ASM_16 | |
| 1005 | − if (s1->seg_size == 16) | |
| 1006 | − gen_expr16(&ops[i].e); | |
| 1007 | − else | |
| 1008 | −#endif | |
| 1009 | 857 | if (ops[i].e.sym) |
| 1010 | 858 | error_relocate: |
| 1011 | 859 | tcc_error("cannot relocate"); |
| @@ -1015,18 +863,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 3 unmodified lines | ||
| 1015 | 863 | if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) { |
| 1016 | 864 | if (is_short_jmp) |
| 1017 | 865 | g(ops[i].e.v); |
| 1018 | −#ifdef I386_ASM_16 | |
| 1019 | − else if (s1->seg_size == 16) | |
| 1020 | − gen_disp16(&ops[i].e); | |
| 1021 | −#endif | |
| 1022 | 866 | else |
| 1023 | 867 | gen_disp32(&ops[i].e); |
| 1024 | 868 | } else { |
| 1025 | −#ifdef I386_ASM_16 | |
| 1026 | − if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32))) | |
| 1027 | − gen_expr16(&ops[i].e); | |
| 1028 | − else | |
| 1029 | −#endif | |
| 1030 | 869 | #ifdef TCC_TARGET_X86_64 |
| 1031 | 870 | if (v & OP_IM64) |
| 1032 | 871 | gen_expr64(&ops[i].e); |
| @@ -1035,18 +874,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 2 unmodified lines | ||
| 1035 | 874 | gen_expr32(&ops[i].e); |
| 1036 | 875 | } |
| 1037 | 876 | } |
| 1038 | −#ifdef I386_ASM_16 | |
| 1039 | − } else if (v & (OP_REG16 | OP_REG32)) { | |
| 1040 | − if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) { | |
| 1041 | − /* jmp $r */ | |
| 1042 | − g(0xE0 + ops[i].reg); | |
| 1043 | − } | |
| 1044 | −#endif | |
| 1045 | 877 | } |
| 1046 | 878 | } |
| 1047 | −#ifdef I386_ASM_16 | |
| 1048 | − a32 = o32 = 0; | |
| 1049 | −#endif | |
| 1050 | 879 | } |
| 1051 | 880 | |
| 1052 | 881 | /* return the constraint priority (we allocate first the lowest |
| @@ -1462,10 +1291,6 @@ ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, · 409 unmodified lines | ||
| 1462 | 1291 | for(i = 0; i < NB_SAVED_REGS; i++) { |
| 1463 | 1292 | reg = reg_saved[i]; |
| 1464 | 1293 | if (regs_allocated[reg]) { |
| 1465 | −#ifdef I386_ASM_16 | |
| 1466 | − if (tcc_state->seg_size == 16) | |
| 1467 | − g(0x66); | |
| 1468 | −#endif | |
| 1469 | 1294 | g(0x50 + reg); |
| 1470 | 1295 | } |
| 1471 | 1296 | } |
| @@ -1524,10 +1349,6 @@ ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, · 52 unmodified lines | ||
| 1524 | 1349 | for(i = NB_SAVED_REGS - 1; i >= 0; i--) { |
| 1525 | 1350 | reg = reg_saved[i]; |
| 1526 | 1351 | if (regs_allocated[reg]) { |
| 1527 | −#ifdef I386_ASM_16 | |
| 1528 | − if (tcc_state->seg_size == 16) | |
| 1529 | − g(0x66); | |
| 1530 | −#endif | |
| 1531 | 1352 | g(0x58 + reg); |
| 1532 | 1353 | } |
| 1533 | 1354 | } |
| @@ -76,15 +76,10 @@ ALT(DEF_ASM_OP2(btcw, 0x0fba, 7, OPC_MODRM | OPC_WL, OPT_IM8, OPT_REGW | OPT_EA) · 75 unmodified lines | ||
| 76 | 76 | /* prefixes */ |
| 77 | 77 | DEF_ASM_OP0(wait, 0x9b) |
| 78 | 78 | DEF_ASM_OP0(fwait, 0x9b) |
| 79 | −#ifdef I386_ASM_16 | |
| 80 | − DEF_ASM_OP0(a32, 0x67) | |
| 81 | − DEF_ASM_OP0(o32, 0x66) | |
| 82 | −#else | |
| 83 | 79 | DEF_ASM_OP0(aword, 0x67) |
| 84 | 80 | DEF_ASM_OP0(addr16, 0x67) |
| 85 | 81 | ALT(DEF_ASM_OP0(word, 0x66)) |
| 86 | 82 | DEF_ASM_OP0(data16, 0x66) |
| 87 | −#endif | |
| 88 | 83 | DEF_ASM_OP0(lock, 0xf0) |
| 89 | 84 | DEF_ASM_OP0(rep, 0xf3) |
| 90 | 85 | DEF_ASM_OP0(repe, 0xf3) |
| @@ -208,9 +203,6 @@ ALT(DEF_ASM_OP1(call, 0xff, 2, OPC_MODRM, OPT_INDIR)) · 117 unmodified lines | ||
| 208 | 203 | ALT(DEF_ASM_OP1(call, 0xe8, 0, OPC_JMP, OPT_ADDR)) |
| 209 | 204 | ALT(DEF_ASM_OP1(jmp, 0xff, 4, OPC_MODRM, OPT_INDIR)) |
| 210 | 205 | ALT(DEF_ASM_OP1(jmp, 0xeb, 0, OPC_SHORTJMP | OPC_JMP, OPT_ADDR)) |
| 211 | −#ifdef I386_ASM_16 | |
| 212 | −ALT(DEF_ASM_OP1(jmp, 0xff, 0, OPC_JMP | OPC_WL, OPT_REGW)) | |
| 213 | −#endif | |
| 214 | 206 | |
| 215 | 207 | ALT(DEF_ASM_OP2(lcall, 0x9a, 0, 0, OPT_IM16, OPT_IM32)) |
| 216 | 208 | ALT(DEF_ASM_OP1(lcall, 0xff, 3, OPC_MODRM, OPT_EA)) |
| @@ -364,11 +356,6 @@ ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WL, OPT_EA | OPT_REG, OPT_REG)) · 147 unmodified lines | ||
| 364 | 356 | DEF_ASM_OP1(verr, 0x0f00, 4, OPC_MODRM, OPT_REG | OPT_EA) |
| 365 | 357 | DEF_ASM_OP1(verw, 0x0f00, 5, OPC_MODRM, OPT_REG | OPT_EA) |
| 366 | 358 | |
| 367 | −#ifdef I386_ASM_16 | |
| 368 | − /* 386 */ | |
| 369 | − DEF_ASM_OP0(loadall386, 0x0f07) | |
| 370 | −#endif | |
| 371 | − | |
| 372 | 359 | /* 486 */ |
| 373 | 360 | DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 ) |
| 374 | 361 | ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT_EA )) |
| @@ -383,15 +370,6 @@ ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT · 8 unmodified lines | ||
| 383 | 370 | |
| 384 | 371 | /* pentium pro */ |
| 385 | 372 | ALT(DEF_ASM_OP2(cmovo, 0x0f40, 0, OPC_MODRM | OPC_TEST | OPC_WL, OPT_REGW | OPT_EA, OPT_REGW)) |
| 386 | −#ifdef I386_ASM_16 | |
| 387 | −ALT(DEF_ASM_OP2(cmovno, 0x0f41, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 388 | −ALT(DEF_ASM_OP2(cmovc, 0x0f42, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 389 | −ALT(DEF_ASM_OP2(cmovnc, 0x0f43, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 390 | −ALT(DEF_ASM_OP2(cmovz, 0x0f44, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 391 | −ALT(DEF_ASM_OP2(cmovnz, 0x0f45, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 392 | −ALT(DEF_ASM_OP2(cmovna, 0x0f46, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 393 | −ALT(DEF_ASM_OP2(cmova, 0x0f47, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_REG32)) | |
| 394 | −#endif | |
| 395 | 373 | DEF_ASM_OP2(fcmovb, 0xdac0, 0, OPC_REG, OPT_ST, OPT_ST0 ) |
| 396 | 374 | DEF_ASM_OP2(fcmove, 0xdac8, 0, OPC_REG, OPT_ST, OPT_ST0 ) |
| 397 | 375 | DEF_ASM_OP2(fcmovbe, 0xdad0, 0, OPC_REG, OPT_ST, OPT_ST0 ) |