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x86-asm: Fix lar opcode operands

lar can accept multiple sizes as well (wlx), like lsl. When using autosize it's important to look at the destination operand first; when it's a register that one determines the size, not the input operand.

Michael Matz committed 10 years ago

Commit 56927161 parent e3f2a685 files · +15 −3Browse files

Unified · Split

5 files
  1. i386-asm.c +5 −1
  2. i386-asm.h +1 −1
  3. i386-tok.h +1 −0
  4. tests/asmtest.S +7 −0
  5. x86_64-asm.h +1 −1
i386-asm.c+5−1
@@ -733,7 +733,11 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 732 unmodified lines
733733 autosize = NBWLX-2;
734734 #endif
735735 if (s == autosize) {
736− for(i = 0; s == autosize && i < nb_ops; i++) {
736+ /* Check for register operands providing hints about the size.
737+ Start from the end, i.e. destination operands. This matters
738+ only for opcodes accepting different sized registers, lar and lsl
739+ are such opcodes. */
740+ for(i = nb_ops - 1; s == autosize && i >= 0; i--) {
737741 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
738742 s = reg_to_size[ops[i].type & OP_REG];
739743 }
i386-asm.h+1−1
@@ -341,7 +341,7 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA )) · 340 unmodified lines
341341
342342 /* segments */
343343 DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA)
344− DEF_ASM_OP2(lar, 0x0f02, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG32)
344+ALT(DEF_ASM_OP2(larw, 0x0f02, 0, OPC_MODRM | OPC_WLX, OPT_REG | OPT_EA, OPT_REG))
345345 DEF_ASM_OP1(lgdt, 0x0f01, 2, OPC_MODRM, OPT_EA)
346346 DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)
347347 DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA | OPT_REG)
i386-tok.h+1−0
@@ -185,6 +185,7 @@ · 184 unmodified lines
185185 DEF_WLX(btr)
186186 DEF_WLX(btc)
187187
188+ DEF_WLX(lar)
188189 DEF_WLX(lsl)
189190
190191 /* generic FP ops */
tests/asmtest.S+7−0
@@ -625,8 +625,15 @@ int $0x10 · 624 unmodified lines
625625 clflush 0x1000(%rax,%rcx)
626626 fxsaveq (%rdx)
627627 fxrstorq (%rcx)
628+
628629 #endif
629630
631+ lar %ax,%dx
632+ lar %eax,%dx
633+ lar %ax,%edx
634+ lar %eax,%edx
635+ lar %ax,%rdx
636+ lar %eax,%rdx
630637 emms
631638 movd %edx, %mm3
632639 movd 0x1000, %mm2
x86_64-asm.h+1−1
@@ -359,7 +359,7 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA )) · 358 unmodified lines
359359
360360 /* segments */
361361 DEF_ASM_OP2(arpl, 0x63, 0, OPC_MODRM, OPT_REG16, OPT_REG16 | OPT_EA)
362− DEF_ASM_OP2(lar, 0x0f02, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG32)
362+ALT(DEF_ASM_OP2(larw, 0x0f02, 0, OPC_MODRM | OPC_WLX, OPT_REG | OPT_EA, OPT_REG))
363363 DEF_ASM_OP1(lgdt, 0x0f01, 2, OPC_MODRM, OPT_EA)
364364 DEF_ASM_OP1(lgdtq, 0x0f01, 2, OPC_MODRM, OPT_EA)
365365 DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)

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