History

[x86] Fix some asm problems

A bag of assembler fixes, to be either compatible with GAS (e.g. order of 'test' operands), accept more instructions, count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes on x86_64 to not use %rip relative addressing mode, to not use invalid insns in tests/asmtest.S for x86_64. Result is that now output of GAS and of tcc on tests/asmtest.S is mostly the same.

Michael Matz committed 10 years ago

Commit 5e47b081 parent f5f82ab5 files · +168 −47Browse files

Unified · Split

5 files
  1. i386-asm.c +71 −16
  2. i386-asm.h +1 −1
  3. i386-tok.h +3 −7
  4. tests/asmtest.S +67 −8
  5. x86_64-asm.h +26 −15
i386-asm.c+71−16
@@ -115,11 +115,13 @@ enum { · 114 unmodified lines
115#define OP_ADDR (1 << OPT_ADDR)115#define OP_ADDR (1 << OPT_ADDR)
116#define OP_INDIR (1 << OPT_INDIR)116#define OP_INDIR (1 << OPT_INDIR)
117#ifdef TCC_TARGET_X86_64117#ifdef TCC_TARGET_X86_64
118# define OP_REG64 (1 << OPT_REG64)118# define OP_REG64 (1 << OPT_REG64)
119# define OP_IM64 (1 << OPT_IM64)119# define OP_IM64 (1 << OPT_IM64)
120# define OP_EA32 (OP_EA << 1)
120#else121#else
121# define OP_REG64 0122# define OP_REG64 0
122# define OP_IM64 0123# define OP_IM64 0
124# define OP_EA32 0
123#endif125#endif
124 126
125#define OP_EA 0x40000000127#define OP_EA 0x40000000
@@ -268,15 +270,17 @@ static inline int get_reg_shift(TCCState *s1) · 142 unmodified lines
268 return shift;270 return shift;
269}271}
270 272
271static int asm_parse_reg(void)273static int asm_parse_reg(int *type)
272{274{
273 int reg = 0;275 int reg = 0;
276 *type = 0;
274 if (tok != '%')277 if (tok != '%')
275 goto error_32;278 goto error_32;
276 next();279 next();
277 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {280 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
278 reg = tok - TOK_ASM_eax;281 reg = tok - TOK_ASM_eax;
279#ifdef TCC_TARGET_X86_64282#ifdef TCC_TARGET_X86_64
283 *type = OP_EA32;
280 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {284 } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
281 reg = tok - TOK_ASM_rax;285 reg = tok - TOK_ASM_rax;
282#endif286#endif
@@ -393,20 +397,23 @@ static void parse_operand(TCCState *s1, Operand *op) · 110 unmodified lines
393 }397 }
394 }398 }
395 if (tok == '(') {399 if (tok == '(') {
400 int type = 0;
396 next();401 next();
397 if (tok != ',') {402 if (tok != ',') {
398 op->reg = asm_parse_reg();403 op->reg = asm_parse_reg(&type);
399 }404 }
400 if (tok == ',') {405 if (tok == ',') {
401 next();406 next();
402 if (tok != ',') {407 if (tok != ',') {
403 op->reg2 = asm_parse_reg();408 op->reg2 = asm_parse_reg(&type);
404 }409 }
405 if (tok == ',') {410 if (tok == ',') {
406 next();411 next();
407 op->shift = get_reg_shift(s1);412 op->shift = get_reg_shift(s1);
408 }413 }
409 }414 }
415 if (type & OP_EA32)
416 op->type |= OP_EA32;
410 skip(')');417 skip(')');
411 }418 }
412 if (op->reg == -1 && op->reg2 == -1)419 if (op->reg == -1 && op->reg2 == -1)
@@ -493,10 +500,15 @@ static inline void asm_modrm(int reg, Operand *op) · 80 unmodified lines
493 gen_expr16(&op->e);500 gen_expr16(&op->e);
494 } else if (tcc_state->seg_size == 32)501 } else if (tcc_state->seg_size == 32)
495#endif502#endif
496 {503 {
504#ifdef TCC_TARGET_X86_64
505 g(0x04 + (reg << 3));
506 g(0x25);
507#else
497 g(0x05 + (reg << 3));508 g(0x05 + (reg << 3));
498 gen_expr32(&op->e);509#endif
499 }510 gen_expr32(&op->e);
511 }
500 } else {512 } else {
501 sib_reg1 = op->reg;513 sib_reg1 = op->reg;
502 /* fist compute displacement encoding */514 /* fist compute displacement encoding */
@@ -583,6 +595,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 80 unmodified lines
583 int nb_ops, s;595 int nb_ops, s;
584 Operand ops[MAX_OPERANDS], *pop;596 Operand ops[MAX_OPERANDS], *pop;
585 int op_type[3]; /* decoded op type */597 int op_type[3]; /* decoded op type */
598 int alltypes; /* OR of all operand types */
599 int autosize;
586#ifdef I386_ASM_16600#ifdef I386_ASM_16
587 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;601 static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
588#endif602#endif
@@ -596,6 +610,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 7 unmodified lines
596 pop = ops;610 pop = ops;
597 nb_ops = 0;611 nb_ops = 0;
598 seg_prefix = 0;612 seg_prefix = 0;
613 alltypes = 0;
599 for(;;) {614 for(;;) {
600 if (tok == ';' || tok == TOK_LINEFEED)615 if (tok == ';' || tok == TOK_LINEFEED)
601 break;616 break;
@@ -645,6 +660,13 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 43 unmodified lines
645 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))660 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
646 continue;661 continue;
647 } else if (pa->instr_type & OPC_B) {662 } else if (pa->instr_type & OPC_B) {
663#ifdef TCC_TARGET_X86_64
664 /* Some instructions don't have the full size but only
665 bwl form. insb e.g. */
666 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ
667 && !(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
668 continue;
669#endif
648 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))670 if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
649 continue;671 continue;
650 s = opcode - pa->sym;672 s = opcode - pa->sym;
@@ -659,6 +681,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 8 unmodified lines
659 if (pa->nb_ops != nb_ops)681 if (pa->nb_ops != nb_ops)
660 continue;682 continue;
661 /* now decode and check each operand */683 /* now decode and check each operand */
684 alltypes = 0;
662 for(i = 0; i < nb_ops; i++) {685 for(i = 0; i < nb_ops; i++) {
663 int op1, op2;686 int op1, op2;
664 op1 = pa->op_type[i];687 op1 = pa->op_type[i];
@@ -687,9 +710,10 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 22 unmodified lines
687 }710 }
688 if (op1 & OPT_EA)711 if (op1 & OPT_EA)
689 v |= OP_EA;712 v |= OP_EA;
690 op_type[i] = v;713 op_type[i] = v;
691 if ((ops[i].type & v) == 0)714 if ((ops[i].type & v) == 0)
692 goto next;715 goto next;
716 alltypes |= ops[i].type;
693 }717 }
694 /* all is matching ! */718 /* all is matching ! */
695 break;719 break;
@@ -725,12 +749,19 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 29 unmodified lines
725 }749 }
726 }750 }
727 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */751 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
728 if (s == NBWLX-1) {752 autosize = NBWLX-1;
729 for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {753#ifdef TCC_TARGET_X86_64
754 /* XXX the autosize should rather be zero, to not have to adjust this
755 all the time. */
756 if ((pa->instr_type & OPC_WLQ) != OPC_WLQ)
757 autosize = NBWLX-2;
758#endif
759 if (s == autosize) {
760 for(i = 0; s == autosize && i < nb_ops; i++) {
730 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))761 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
731 s = reg_to_size[ops[i].type & OP_REG];762 s = reg_to_size[ops[i].type & OP_REG];
732 }763 }
733 if (s == NBWLX-1) {764 if (s == autosize) {
734 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&765 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
735 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))766 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
736 s = 2;767 s = 2;
@@ -770,14 +801,38 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 33 unmodified lines
770 801
771 addr32 = data32 = 0;802 addr32 = data32 = 0;
772#else803#else
804#ifdef TCC_TARGET_X86_64
805 /* Generate addr32 prefix if needed */
806 for(i = 0; i < nb_ops; i++) {
807 if (ops[i].type & OP_EA32) {
808 g(0x67);
809 break;
810 }
811 }
812#endif
773 /* generate data16 prefix if needed */813 /* generate data16 prefix if needed */
774 if (s == 1 || (pa->instr_type & OPC_D16))814 if (s == 1 || (pa->instr_type & OPC_D16))
775 g(0x66);815 g(0x66);
776#ifdef TCC_TARGET_X86_64816#ifdef TCC_TARGET_X86_64
777 else if (s == 3) {817 if (s == 3 || (alltypes & OP_REG64)) {
778 /* generate REX prefix */818 /* generate REX prefix */
779 if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)819 int default64 = 0;
780 || !(ops[0].type & OP_REG64))820 for(i = 0; i < nb_ops; i++) {
821 if (op_type[i] == OP_REG64) {
822 /* If only 64bit regs are accepted in one operand
823 this is a default64 instruction without need for
824 REX prefixes. */
825 default64 = 1;
826 break;
827 }
828 }
829 /* XXX find better encoding for the default64 instructions. */
830 if (((opcode != TOK_ASM_push && opcode != TOK_ASM_pop
831 && opcode != TOK_ASM_pushw && opcode != TOK_ASM_pushl
832 && opcode != TOK_ASM_pushq && opcode != TOK_ASM_popw
833 && opcode != TOK_ASM_popl && opcode != TOK_ASM_popq
834 && opcode != TOK_ASM_call && opcode != TOK_ASM_jmp))
835 && !default64)
781 g(0x48);836 g(0x48);
782 }837 }
783#endif838#endif
@@ -838,7 +893,7 @@ ST_FUNC void asm_opcode(TCCState *s1, int opcode) · 54 unmodified lines
838 goto no_short_jump;893 goto no_short_jump;
839 if (sym->r != cur_text_section->sh_num)894 if (sym->r != cur_text_section->sh_num)
840 goto no_short_jump;895 goto no_short_jump;
841 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;896 jmp_disp = ops[0].e.v + sym->jnext - ind - 2 - (v >= 0xff);
842 if (jmp_disp == (int8_t)jmp_disp) {897 if (jmp_disp == (int8_t)jmp_disp) {
843 /* OK to generate jump */898 /* OK to generate jump */
844 is_short_jmp = 1;899 is_short_jmp = 1;
i386-asm.h+1−1
@@ -165,8 +165,8 @@ ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWL, OPT_IM, OPT_EAX)) · 164 unmodified lines
165ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))165ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))
166ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WL, OPT_IM8S, OPT_EA | OPT_REG))166ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WL, OPT_IM8S, OPT_EA | OPT_REG))
167 167
168ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
169ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG))168ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_EA | OPT_REG))
169ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWL, OPT_EA | OPT_REG, OPT_REG))
170ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWL, OPT_IM, OPT_EAX))170ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWL, OPT_IM, OPT_EAX))
171ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))171ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWL, OPT_IM, OPT_EA | OPT_REG))
172 172
i386-tok.h+3−7
@@ -126,12 +126,8 @@ · 125 unmodified lines
126 DEF_BWLX(shr)126 DEF_BWLX(shr)
127 DEF_BWLX(sar)127 DEF_BWLX(sar)
128 128
129 DEF_ASM(shldw)129 DEF_WLX(shld)
130 DEF_ASM(shldl)130 DEF_WLX(shrd)
131 DEF_ASM(shld)
132 DEF_ASM(shrdw)
133 DEF_ASM(shrdl)
134 DEF_ASM(shrd)
135 131
136 DEF_ASM(pushw)132 DEF_ASM(pushw)
137 DEF_ASM(pushl)133 DEF_ASM(pushl)
@@ -150,7 +146,7 @@ · 12 unmodified lines
150 DEF_BWL(in)146 DEF_BWL(in)
151 DEF_BWL(out)147 DEF_BWL(out)
152 148
153 DEF_WL(movzb)149 DEF_WLX(movzb)
154 DEF_ASM(movzwl)150 DEF_ASM(movzwl)
155 DEF_ASM(movsbw)151 DEF_ASM(movsbw)
156 DEF_ASM(movsbl)152 DEF_ASM(movsbl)
tests/asmtest.S+67−8
@@ -38,7 +38,7 @@ mov %al, 0x10000 · 37 unmodified lines
38 38
39mov $1, %edx39mov $1, %edx
40mov $1, %dx40mov $1, %dx
41mov $1, %dl41mov $1, %cl
42movb $2, 0x100(%ebx,%edx,2)42movb $2, 0x100(%ebx,%edx,2)
43movw $2, 0x100(%ebx,%edx,2)43movw $2, 0x100(%ebx,%edx,2)
44movl $2, 0x100(%ebx,%edx,2)44movl $2, 0x100(%ebx,%edx,2)
@@ -48,12 +48,20 @@ movw %ax, 0x100(%ebx,%edx,2) · 3 unmodified lines
48 48
49mov %eax, 0x12(,%edx,2)49mov %eax, 0x12(,%edx,2)
50 50
51#ifdef __i386__
51mov %cr3, %edx52mov %cr3, %edx
52mov %ecx, %cr353mov %ecx, %cr3
53movl %cr3, %eax54movl %cr3, %eax
54movl %tr3, %eax55movl %tr3, %eax
55movl %db3, %ebx56movl %db3, %ebx
56movl %dr6, %eax57movl %dr6, %eax
58#else
59mov %cr3, %rdx
60mov %rcx, %cr3
61movq %cr3, %rax
62movq %db3, %rbx
63movq %dr6, %rax
64#endif
57movl %fs, %ecx65movl %fs, %ecx
58movl %ebx, %fs66movl %ebx, %fs
59 67
@@ -69,18 +77,28 @@ movl %ebx, %fs · 9 unmodified lines
69 movzb 0x1000, %ax77 movzb 0x1000, %ax
70 78
71 79
80#ifdef __i386__
72 pushl %eax81 pushl %eax
73 pushw %ax
74 push %eax82 push %eax
75 push %cs83 push %cs
84#else
85 pushq %rax
86 push %rax
87#endif
88 pushw %ax
76 push %gs89 push %gs
77 push $190 push $1
78 push $10091 push $100
79 92
93#ifdef __i386__
80 popl %eax94 popl %eax
81 popw %ax
82 pop %eax95 pop %eax
83 pop %ds96 pop %ds
97#else
98 popq %rax
99 pop %rax
100#endif
101 popw %ax
84 pop %fs102 pop %fs
85 103
86 xchg %eax, %ecx104 xchg %eax, %ecx
@@ -111,11 +129,13 @@ movl %ebx, %fs · 24 unmodified lines
111 leal 0x1000(%ebx), %ecx129 leal 0x1000(%ebx), %ecx
112 lea 0x1000(%ebx), %ecx130 lea 0x1000(%ebx), %ecx
113 131
132#ifdef __i386__
114 les 0x2000, %eax133 les 0x2000, %eax
115 lds 0x2000, %ebx134 lds 0x2000, %ebx
135 lss 0x2000, %edx
136#endif
116 lfs 0x2000, %ecx137 lfs 0x2000, %ecx
117 lgs 0x2000, %edx138 lgs 0x2000, %edx
118 lss 0x2000, %edx
119 139
120addl $0x123, %eax140addl $0x123, %eax
121add $0x123, %ebx141add $0x123, %ebx
@@ -195,7 +215,11 @@ shrd %eax, %edx · 73 unmodified lines
195L4:215L4:
196call 0x1000216call 0x1000
197call L4217call L4
218#ifdef __i386__
198call *%eax219call *%eax
220#else
221call *%rax
222#endif
199call *0x1000223call *0x1000
200call func1224call func1
201 225
@@ -204,19 +228,37 @@ call func1 · 2 unmodified lines
204L5:228L5:
205L6:229L6:
206 230
231#ifdef __i386__
207lcall $0x100, $0x1000232lcall $0x100, $0x1000
233#else
234lcall *0x100
235lcall *(%rax)
236#endif
208 237
209jmp 0x1000238jmp 0x1000
239#ifdef __i386__
210jmp *%eax240jmp *%eax
241#else
242jmp *%rax
243#endif
211jmp *0x1000244jmp *0x1000
212 245
246#ifdef __i386__
213ljmp $0x100, $0x1000247ljmp $0x100, $0x1000
248#else
249ljmp *0x100
250ljmp *(%rdi)
251#endif
214 252
215ret253ret
216retl
217
218ret $10254ret $10
255#ifdef __i386__
256retl
219retl $10257retl $10
258#else
259retq
260retq $10
261#endif
220 262
221lret263lret
222 264
@@ -436,8 +478,10 @@ fucomip %st(5), %st · 213 unmodified lines
436int $3478int $3
437int $0x10479int $0x10
438 480
481#ifdef __i386__
439 pusha482 pusha
440 popa483 popa
484#endif
441 clc485 clc
442 cld486 cld
443 cli487 cli
@@ -445,19 +489,27 @@ int $0x10 · 1 unmodified line
445 cmc489 cmc
446 lahf490 lahf
447 sahf491 sahf
492#ifdef __i386__
448 pushfl493 pushfl
449 popfl494 popfl
495#else
496 pushfq
497 popfq
498#endif
450 pushf499 pushf
451 popf500 popf
452 stc501 stc
453 std502 std
454 sti503 sti
504#ifdef __i386__
455 aaa505 aaa
456 aas506 aas
457 daa507 daa
458 das508 das
459 aad509 aad
460 aam510 aam
511 into
512#endif
461 cbw513 cbw
462 cwd514 cwd
463 cwde515 cwde
@@ -468,7 +520,6 @@ int $0x10 · 4 unmodified lines
468 cltd520 cltd
469 leave521 leave
470 int3522 int3
471 into
472 iret523 iret
473 rsm524 rsm
474 hlt525 hlt
@@ -558,10 +609,12 @@ int $0x10 · 83 unmodified lines
558 609
559 610
560 611
612#ifdef __i386__
561 boundl %edx, 0x10000613 boundl %edx, 0x10000
562 boundw %bx, 0x1000614 boundw %bx, 0x1000
563 615
564 arpl %bx, 0x1000616 arpl %bx, 0x1000
617#endif
565 lar 0x1000, %eax618 lar 0x1000, %eax
566 lgdt 0x1000619 lgdt 0x1000
567 lidt 0x1000620 lidt 0x1000
@@ -579,15 +632,21 @@ int $0x10 · 11 unmodified lines
579 verr 0x1000632 verr 0x1000
580 verw 0x1000633 verw 0x1000
581 634
635#ifdef __i386__
582 push %ds636 push %ds
583 pushw %ds637 pushw %ds
584 pushl %ds638 pushl %ds
585 pop %ds639 pop %ds
586 popw %ds640 popw %ds
587 popl %ds641 popl %ds
642#endif
588 fxsave 1(%ebx)643 fxsave 1(%ebx)
589 fxrstor 1(%ecx)644 fxrstor 1(%ecx)
645#ifdef __i386__
590 pushl $1646 pushl $1
647#else
648 pushq $1
649#endif
591 pushw $1650 pushw $1
592 push $1651 push $1
593 652
x86_64-asm.h+26−15
@@ -5,8 +5,8 @@ · 4 unmodified lines
5 DEF_ASM_OP0(cmc, 0xf5)5 DEF_ASM_OP0(cmc, 0xf5)
6 DEF_ASM_OP0(lahf, 0x9f)6 DEF_ASM_OP0(lahf, 0x9f)
7 DEF_ASM_OP0(sahf, 0x9e)7 DEF_ASM_OP0(sahf, 0x9e)
8 DEF_ASM_OP0(pushfl, 0x9c)8 DEF_ASM_OP0(pushfq, 0x9c)
9 DEF_ASM_OP0(popfl, 0x9d)9 DEF_ASM_OP0(popfq, 0x9d)
10 DEF_ASM_OP0(pushf, 0x9c)10 DEF_ASM_OP0(pushf, 0x9c)
11 DEF_ASM_OP0(popf, 0x9d)11 DEF_ASM_OP0(popf, 0x9d)
12 DEF_ASM_OP0(stc, 0xf9)12 DEF_ASM_OP0(stc, 0xf9)
@@ -34,14 +34,15 @@ · 21 unmodified lines
34 DEF_ASM_OP0(hlt, 0xf4)34 DEF_ASM_OP0(hlt, 0xf4)
35 DEF_ASM_OP0(wait, 0x9b)35 DEF_ASM_OP0(wait, 0x9b)
36 DEF_ASM_OP0(nop, 0x90)36 DEF_ASM_OP0(nop, 0x90)
37 DEF_ASM_OP0(pause, 0xf390)
37 DEF_ASM_OP0(xlat, 0xd7)38 DEF_ASM_OP0(xlat, 0xd7)
38 39
39 /* strings */40 /* strings */
40ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWLQ))41ALT(DEF_ASM_OP0L(cmpsb, 0xa6, 0, OPC_BWLQ))
41ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWLQ))42ALT(DEF_ASM_OP0L(scmpb, 0xa6, 0, OPC_BWLQ))
42 43
43ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWLQ))44ALT(DEF_ASM_OP0L(insb, 0x6c, 0, OPC_BWL))
44ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWLQ))45ALT(DEF_ASM_OP0L(outsb, 0x6e, 0, OPC_BWL))
45 46
46ALT(DEF_ASM_OP0L(lodsb, 0xac, 0, OPC_BWLQ))47ALT(DEF_ASM_OP0L(lodsb, 0xac, 0, OPC_BWLQ))
47ALT(DEF_ASM_OP0L(slodb, 0xac, 0, OPC_BWLQ))48ALT(DEF_ASM_OP0L(slodb, 0xac, 0, OPC_BWLQ))
@@ -90,8 +91,10 @@ ALT(DEF_ASM_OP2(btcw, 0x0fba, 7, OPC_MODRM | OPC_WLQ, OPT_IM8, OPT_REGW | OPT_EA · 42 unmodified lines
90 DEF_ASM_OP0(ud2, 0x0f0b)91 DEF_ASM_OP0(ud2, 0x0f0b)
91 92
92 /* NOTE: we took the same order as gas opcode definition order */93 /* NOTE: we took the same order as gas opcode definition order */
94/* Right now we can't express the fact that 0xa1/0xa3 can't use $eax and a
95 32 bit moffset as operands.
93ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWLQ, OPT_ADDR, OPT_EAX))96ALT(DEF_ASM_OP2(movb, 0xa0, 0, OPC_BWLQ, OPT_ADDR, OPT_EAX))
94ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR))97ALT(DEF_ASM_OP2(movb, 0xa2, 0, OPC_BWLQ, OPT_EAX, OPT_ADDR)) */
95ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))98ALT(DEF_ASM_OP2(movb, 0x88, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))
96ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))99ALT(DEF_ASM_OP2(movb, 0x8a, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
97ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG | OPC_BWLQ, OPT_IM, OPT_REG))100ALT(DEF_ASM_OP2(movb, 0xb0, 0, OPC_REG | OPC_BWLQ, OPT_IM, OPT_REG))
@@ -102,25 +105,28 @@ ALT(DEF_ASM_OP2(movw, 0x8e, 0, OPC_MODRM | OPC_WLQ, OPT_EA | OPT_REG, OPT_SEG)) · 4 unmodified lines
102 105
103ALT(DEF_ASM_OP2(movw, 0x0f20, 0, OPC_MODRM | OPC_WLQ, OPT_CR, OPT_REG64))106ALT(DEF_ASM_OP2(movw, 0x0f20, 0, OPC_MODRM | OPC_WLQ, OPT_CR, OPT_REG64))
104ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM | OPC_WLQ, OPT_DB, OPT_REG64))107ALT(DEF_ASM_OP2(movw, 0x0f21, 0, OPC_MODRM | OPC_WLQ, OPT_DB, OPT_REG64))
105ALT(DEF_ASM_OP2(movw, 0x0f24, 0, OPC_MODRM | OPC_WLQ, OPT_TR, OPT_REG64))
106ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_CR))108ALT(DEF_ASM_OP2(movw, 0x0f22, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_CR))
107ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_DB))109ALT(DEF_ASM_OP2(movw, 0x0f23, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_DB))
108ALT(DEF_ASM_OP2(movw, 0x0f26, 0, OPC_MODRM | OPC_WLQ, OPT_REG64, OPT_TR))
109 110
110ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))111ALT(DEF_ASM_OP2(movsbl, 0x0fbe, 0, OPC_MODRM, OPT_REG8 | OPT_EA, OPT_REG32))
111ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16))112ALT(DEF_ASM_OP2(movsbw, 0x0fbe, 0, OPC_MODRM | OPC_D16, OPT_REG8 | OPT_EA, OPT_REG16))
112ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))113ALT(DEF_ASM_OP2(movswl, 0x0fbf, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
113ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG))114ALT(DEF_ASM_OP2(movslq, 0x4863, 0, OPC_MODRM, OPT_REG32 | OPT_EA, OPT_REG))
114ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WL, OPT_REG8 | OPT_EA, OPT_REGW))115ALT(DEF_ASM_OP2(movzbw, 0x0fb6, 0, OPC_MODRM | OPC_WLQ, OPT_REG8 | OPT_EA, OPT_REGW))
115ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))116ALT(DEF_ASM_OP2(movzwl, 0x0fb7, 0, OPC_MODRM, OPT_REG16 | OPT_EA, OPT_REG32))
116 117
118ALT(DEF_ASM_OP1(pushq, 0x6a, 0, 0, OPT_IM8S))
119ALT(DEF_ASM_OP1(push, 0x6a, 0, 0, OPT_IM8S))
120ALT(DEF_ASM_OP1(pushw, 0x6a, 0, OPC_D16, OPT_IM8S))
117ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG | OPC_WLQ, OPT_REG64))121ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG | OPC_WLQ, OPT_REG64))
122ALT(DEF_ASM_OP1(pushw, 0x50, 0, OPC_REG | OPC_WLQ, OPT_REG16))
118ALT(DEF_ASM_OP1(pushw, 0xff, 6, OPC_MODRM | OPC_WLQ, OPT_REG64 | OPT_EA))123ALT(DEF_ASM_OP1(pushw, 0xff, 6, OPC_MODRM | OPC_WLQ, OPT_REG64 | OPT_EA))
124ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_D16, OPT_IM16))
119ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_WLQ, OPT_IM32))125ALT(DEF_ASM_OP1(pushw, 0x68, 0, OPC_WLQ, OPT_IM32))
120ALT(DEF_ASM_OP1(pushw, 0x06, 0, OPC_WLQ, OPT_SEG))126ALT(DEF_ASM_OP1(pushw, 0x06, 0, OPC_WLQ, OPT_SEG))
121 DEF_ASM_OP1(pushb, 0x6a, 0, OPC_B, OPT_IM8S)
122 127
123ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG | OPC_WLQ, OPT_REGW))128ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG | OPC_WLQ, OPT_REG64))
129ALT(DEF_ASM_OP1(popw, 0x58, 0, OPC_REG | OPC_WLQ, OPT_REG16))
124ALT(DEF_ASM_OP1(popw, 0x8f, 0, OPC_MODRM | OPC_WLQ, OPT_REGW | OPT_EA))130ALT(DEF_ASM_OP1(popw, 0x8f, 0, OPC_MODRM | OPC_WLQ, OPT_REGW | OPT_EA))
125ALT(DEF_ASM_OP1(popw, 0x07, 0, OPC_WLQ, OPT_SEG))131ALT(DEF_ASM_OP1(popw, 0x07, 0, OPC_WLQ, OPT_SEG))
126 132
@@ -154,8 +160,8 @@ ALT(DEF_ASM_OP2(addb, 0x04, 0, OPC_ARITH | OPC_BWLQ, OPT_IMNO64, OPT_EAX)) · 27 unmodified lines
154ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))160ALT(DEF_ASM_OP2(addb, 0x80, 0, OPC_ARITH | OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))
155ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLQ, OPT_IM8S, OPT_EA | OPT_REG))161ALT(DEF_ASM_OP2(addw, 0x83, 0, OPC_ARITH | OPC_MODRM | OPC_WLQ, OPT_IM8S, OPT_EA | OPT_REG))
156 162
157ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
158ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))163ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_EA | OPT_REG))
164ALT(DEF_ASM_OP2(testb, 0x84, 0, OPC_MODRM | OPC_BWLQ, OPT_EA | OPT_REG, OPT_REG))
159ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IMNO64, OPT_EAX))165ALT(DEF_ASM_OP2(testb, 0xa8, 0, OPC_BWLQ, OPT_IMNO64, OPT_EAX))
160ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))166ALT(DEF_ASM_OP2(testb, 0xf6, 0, OPC_MODRM | OPC_BWLQ, OPT_IMNO64, OPT_EA | OPT_REG))
161 167
@@ -206,7 +212,9 @@ ALT(DEF_ASM_OP1(setob, 0x0f90, 0, OPC_MODRM | OPC_TEST, OPT_REG8 | OPT_EA)) · 44 unmodified lines
206 DEF_ASM_OP2(enter, 0xc8, 0, 0, OPT_IM16, OPT_IM8)212 DEF_ASM_OP2(enter, 0xc8, 0, 0, OPT_IM16, OPT_IM8)
207 DEF_ASM_OP0(leave, 0xc9)213 DEF_ASM_OP0(leave, 0xc9)
208 DEF_ASM_OP0(ret, 0xc3)214 DEF_ASM_OP0(ret, 0xc3)
215 DEF_ASM_OP0(retq, 0xc3)
209ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))216ALT(DEF_ASM_OP1(ret, 0xc2, 0, 0, OPT_IM16))
217ALT(DEF_ASM_OP1(retq, 0xc2, 0, 0, OPT_IM16))
210 DEF_ASM_OP0(lret, 0xcb)218 DEF_ASM_OP0(lret, 0xcb)
211ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))219ALT(DEF_ASM_OP1(lret, 0xca, 0, 0, OPT_IM16))
212 220
@@ -216,7 +224,7 @@ ALT(DEF_ASM_OP1(jo, 0x70, 0, OPC_SHORTJMP | OPC_JMP | OPC_TEST, OPT_ADDR)) · 3 unmodified lines
216 DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)224 DEF_ASM_OP1(loope, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
217 DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)225 DEF_ASM_OP1(loopz, 0xe1, 0, OPC_SHORTJMP, OPT_ADDR)
218 DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)226 DEF_ASM_OP1(loop, 0xe2, 0, OPC_SHORTJMP, OPT_ADDR)
219 DEF_ASM_OP1(jecxz, 0xe3, 0, OPC_SHORTJMP, OPT_ADDR)227 DEF_ASM_OP1(jecxz, 0x67e3, 0, OPC_SHORTJMP, OPT_ADDR)
220 228
221 /* float */229 /* float */
222 /* specific fcomp handling */230 /* specific fcomp handling */
@@ -224,6 +232,8 @@ ALT(DEF_ASM_OP0L(fcomp, 0xd8d9, 0, 0)) · 1 unmodified line
224 232
225ALT(DEF_ASM_OP1(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST))233ALT(DEF_ASM_OP1(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST))
226ALT(DEF_ASM_OP2(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))234ALT(DEF_ASM_OP2(fadd, 0xd8c0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))
235ALT(DEF_ASM_OP2(fadd, 0xdcc0, 0, OPC_FARITH | OPC_REG, OPT_ST0, OPT_ST))
236ALT(DEF_ASM_OP2(fmul, 0xdcc8, 0, OPC_FARITH | OPC_REG, OPT_ST0, OPT_ST))
227ALT(DEF_ASM_OP0L(fadd, 0xdec1, 0, OPC_FARITH))237ALT(DEF_ASM_OP0L(fadd, 0xdec1, 0, OPC_FARITH))
228ALT(DEF_ASM_OP1(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST))238ALT(DEF_ASM_OP1(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST))
229ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))239ALT(DEF_ASM_OP2(faddp, 0xdec0, 0, OPC_FARITH | OPC_REG, OPT_ST, OPT_ST0))
@@ -334,7 +344,7 @@ ALT(DEF_ASM_OP1(fstsw, 0xdd, 7, OPC_MODRM | OPC_FWAIT, OPT_EA )) · 104 unmodified lines
334 DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)344 DEF_ASM_OP1(lidt, 0x0f01, 3, OPC_MODRM, OPT_EA)
335 DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA | OPT_REG)345 DEF_ASM_OP1(lldt, 0x0f00, 2, OPC_MODRM, OPT_EA | OPT_REG)
336 DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA | OPT_REG)346 DEF_ASM_OP1(lmsw, 0x0f01, 6, OPC_MODRM, OPT_EA | OPT_REG)
337ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WL, OPT_EA | OPT_REG, OPT_REG))347ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WLQ, OPT_EA | OPT_REG, OPT_REG))
338 DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA | OPT_REG)348 DEF_ASM_OP1(ltr, 0x0f00, 3, OPC_MODRM, OPT_EA | OPT_REG)
339 DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)349 DEF_ASM_OP1(sgdt, 0x0f01, 0, OPC_MODRM, OPT_EA)
340 DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)350 DEF_ASM_OP1(sidt, 0x0f01, 1, OPC_MODRM, OPT_EA)
@@ -346,8 +356,8 @@ ALT(DEF_ASM_OP2(lslw, 0x0f03, 0, OPC_MODRM | OPC_WL, OPT_EA | OPT_REG, OPT_REG)) · 5 unmodified lines
346 356
347 /* 486 */357 /* 486 */
348 DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )358 DEF_ASM_OP1(bswap, 0x0fc8, 0, OPC_REG, OPT_REG32 )
349ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT_EA ))359ALT(DEF_ASM_OP2(xaddb, 0x0fc0, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_REG | OPT_EA ))
350ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWL, OPT_REG, OPT_REG | OPT_EA ))360ALT(DEF_ASM_OP2(cmpxchgb, 0x0fb0, 0, OPC_MODRM | OPC_BWLQ, OPT_REG, OPT_REG | OPT_EA ))
351 DEF_ASM_OP1(invlpg, 0x0f01, 7, OPC_MODRM, OPT_EA )361 DEF_ASM_OP1(invlpg, 0x0f01, 7, OPC_MODRM, OPT_EA )
352 362
353 DEF_ASM_OP2(boundl, 0x62, 0, OPC_MODRM, OPT_REG32, OPT_EA)363 DEF_ASM_OP2(boundl, 0x62, 0, OPC_MODRM, OPT_REG32, OPT_EA)
@@ -383,6 +393,7 @@ ALT(DEF_ASM_OP2(cmova, 0x0f47, 0, OPC_MODRM | OPC_TEST, OPT_REG32 | OPT_EA, OPT_ · 29 unmodified lines
383 /* mmx */393 /* mmx */
384 DEF_ASM_OP0(emms, 0x0f77) /* must be last OP0 */394 DEF_ASM_OP0(emms, 0x0f77) /* must be last OP0 */
385 DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA | OPT_REG32, OPT_MMX )395 DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA | OPT_REG32, OPT_MMX )
396ALT(DEF_ASM_OP2(movd, 0x0f6e, 0, OPC_MODRM, OPT_EA | OPT_REG64, OPT_MMX ))
386ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_REG32 ))397ALT(DEF_ASM_OP2(movd, 0x0f7e, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_REG32 ))
387ALT(DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX ))398ALT(DEF_ASM_OP2(movq, 0x0f6f, 0, OPC_MODRM, OPT_EA | OPT_MMX, OPT_MMX ))
388ALT(DEF_ASM_OP2(movq, 0x0f7f, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_MMX ))399ALT(DEF_ASM_OP2(movq, 0x0f7f, 0, OPC_MODRM, OPT_MMX, OPT_EA | OPT_MMX ))

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