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Revert "riscv64-gen: Fix `load` and `store` type_size usage"

It was already contemplated by c81116e29a8e2467681da7e1437911657cccb831. This reverts commit c7263571d217e0863d3e62629207659b6aaf2b8b.

Ekaitz Zarraga committed 2 years ago

Commit 6426cc31 parent c7263571 file · +3 −45Browse files

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riscv64-gen.c+3−45
@@ -222,48 +222,6 @@ static void load_large_constant(int rr, int fc, uint32_t pi) · 221 unmodified lines
222 EI(0x13, 1, rr, rr, 8); // slli RR, RR, 8222 EI(0x13, 1, rr, rr, 8); // slli RR, RR, 8
223}223}
224 224
225ST_FUNC int type_size_integral(CType *type, int *a){
226 int bt;
227 bt = type->t & VT_BTYPE;
228 switch (bt){
229 case VT_VOID:
230 case VT_BOOL:
231 case VT_BYTE:
232 *a = 1;
233 return 1;
234 case VT_SHORT:
235 *a = 2;
236 return 2;
237 case VT_LLONG:
238 case VT_DOUBLE:
239 *a = 8;
240 return 8;
241 case VT_PTR:
242 case VT_FUNC:
243 *a = PTR_SIZE;
244 return PTR_SIZE;
245 case VT_FLOAT:
246 case VT_INT:
247 *a = 4;
248 return 4;
249 case VT_LDOUBLE:
250 *a = LDOUBLE_ALIGN;
251 return LDOUBLE_SIZE;
252 case VT_QLONG:
253 case VT_QFLOAT:
254 *a = 8;
255 return 16;
256 case VT_ENUM:
257 *a = 4;
258 /* Enums might be incomplete, so don't just return '4' here. */
259 return type->ref->c;
260 default:
261 /* VT_STRUCT and VT_UNION */
262 tcc_error("load/store with a non integral");
263 return type_size(type, a);
264 }
265}
266
267ST_FUNC void load(int r, SValue *sv)225ST_FUNC void load(int r, SValue *sv)
268{226{
269 int fr = sv->r;227 int fr = sv->r;
@@ -274,7 +232,7 @@ ST_FUNC void load(int r, SValue *sv) · 4 unmodified lines
274 int align, size;232 int align, size;
275 if (fr & VT_LVAL) {233 if (fr & VT_LVAL) {
276 int func3, opcode = is_freg(r) ? 0x07 : 0x03, br;234 int func3, opcode = is_freg(r) ? 0x07 : 0x03, br;
277 size = type_size_integral(&sv->type, &align);235 size = type_size(&sv->type, &align);
278 assert (!is_freg(r) || bt == VT_FLOAT || bt == VT_DOUBLE);236 assert (!is_freg(r) || bt == VT_FLOAT || bt == VT_DOUBLE);
279 if (bt == VT_FUNC) /* XXX should be done in generic code */237 if (bt == VT_FUNC) /* XXX should be done in generic code */
280 size = PTR_SIZE;238 size = PTR_SIZE;
@@ -355,7 +313,7 @@ ST_FUNC void load(int r, SValue *sv) · 74 unmodified lines
355 EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V313 EI(0x13, 0, rr, ireg(v), 0); // addi RR, V, 0 == mv RR, V
356 else {314 else {
357 int func7 = is_ireg(r) ? 0x70 : 0x78;315 int func7 = is_ireg(r) ? 0x70 : 0x78;
358 size = type_size_integral(&sv->type, &align);316 size = type_size(&sv->type, &align);
359 if (size == 8)317 if (size == 8)
360 func7 |= 1;318 func7 |= 1;
361 assert(size == 4 || size == 8);319 assert(size == 4 || size == 8);
@@ -415,7 +373,7 @@ ST_FUNC void store(int r, SValue *sv) · 53 unmodified lines
415 int rr = is_ireg(r) ? ireg(r) : freg(r), ptrreg;373 int rr = is_ireg(r) ? ireg(r) : freg(r), ptrreg;
416 int fc = sv->c.i;374 int fc = sv->c.i;
417 int bt = sv->type.t & VT_BTYPE;375 int bt = sv->type.t & VT_BTYPE;
418 int align, size = type_size_integral(&sv->type, &align);376 int align, size = type_size(&sv->type, &align);
419 assert(!is_float(bt) || is_freg(r) || bt == VT_LDOUBLE);377 assert(!is_float(bt) || is_freg(r) || bt == VT_LDOUBLE);
420 /* long doubles are in two integer registers, but the load/store378 /* long doubles are in two integer registers, but the load/store
421 primitives only deal with one, so do as if it's one reg. */379 primitives only deal with one, so do as if it's one reg. */

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