On some architectures, ARM for instance, the data and instruction caches are not coherent with each other. This is a problem for the -run feature since instructions are written in memory, and are thus written in the data cache first and then later flushed to the main memory. If the instructions are executed before they are pushed out of the cache, then the processor will fetch the old content from the memory and not the newly generated code. The solution is to flush from the data cache all the data in the memory region containing the instructions and to invalidate the same region in the instruction cache.
Unified · Split
| @@ -689,3 +689,14 @@ void __va_end(struct __va_list_struct *ap) · 688 unmodified lines | |||
| 689 | } | 689 | } |
| 690 | 690 | ||
| 691 | #endif /* __x86_64__ */ | 691 | #endif /* __x86_64__ */ |
| 692 | |||
| 693 | /* Flushing for tccrun */ | ||
| 694 | #if defined(__x86_64__) || defined(__i386__) | ||
| 695 | |||
| 696 | void __clear_cache(char *beginning, char *end) | ||
| 697 | { | ||
| 698 | } | ||
| 699 | |||
| 700 | #else | ||
| 701 | #warning __clear_cache not defined for this architecture, avoid using tcc -run | ||
| 702 | #endif | ||
| @@ -225,6 +225,7 @@ static void set_pages_executable(void *ptr, unsigned long length) · 224 unmodified lines | |||
| 225 | end = (addr_t)ptr + length; | 225 | end = (addr_t)ptr + length; |
| 226 | end = (end + PAGESIZE - 1) & ~(PAGESIZE - 1); | 226 | end = (end + PAGESIZE - 1) & ~(PAGESIZE - 1); |
| 227 | mprotect((void *)start, end - start, PROT_READ | PROT_WRITE | PROT_EXEC); | 227 | mprotect((void *)start, end - start, PROT_READ | PROT_WRITE | PROT_EXEC); |
| 228 | __clear_cache(ptr, prog_main + length); | ||
| 228 | #endif | 229 | #endif |
| 229 | } | 230 | } |
| 230 | 231 | ||