Unified · Split
| @@ -3,15 +3,8 @@ · 2 unmodified lines | ||
| 3 | 3 | .global alloca |
| 4 | 4 | .type alloca, %function |
| 5 | 5 | alloca: |
| 6 | −#ifdef __TINYC__ | |
| 7 | − .int 0xe060d00d | |
| 8 | − .int 0xe3cdd007 | |
| 9 | − .int 0xe1a0000d | |
| 10 | − .int 0xe1a0f00e | |
| 11 | −#else | |
| 12 | 6 | rsb sp, r0, sp |
| 13 | 7 | bic sp, sp, #7 |
| 14 | 8 | mov r0, sp |
| 15 | 9 | mov pc, lr |
| 16 | −#endif | |
| 17 | 10 | .size alloca, .-alloca |
| @@ -13,13 +13,13 @@ unsigned _tccsyscall(unsigned syscall_nr, ...); · 12 unmodified lines | ||
| 13 | 13 | __asm__( |
| 14 | 14 | ".global _tccsyscall\n" |
| 15 | 15 | "_tccsyscall:\n" |
| 16 | − ".int 0xe92d4080\n" // push {r7, lr} | |
| 17 | − ".int 0xe1a07000\n" // mov r7, r0 | |
| 18 | − ".int 0xe1a00001\n" // mov r0, r1 | |
| 19 | − ".int 0xe1a01002\n" // mov r1, r2 | |
| 20 | − ".int 0xe1a02003\n" // mov r2, r3 | |
| 21 | − ".int 0xef000000\n" // svc 0x00000000 | |
| 22 | − ".int 0xe8bd8080\n" // pop {r7, pc} | |
| 16 | + "push {r7, lr}\n\t" | |
| 17 | + "mov r7, r0\n\t" | |
| 18 | + "mov r0, r1\n\t" | |
| 19 | + "mov r1, r2\n\t" | |
| 20 | + "mov r2, r3\n\t" | |
| 21 | + "svc #0\n\t" | |
| 22 | + "pop {r7, pc}" | |
| 23 | 23 | ); |
| 24 | 24 | |
| 25 | 25 | /* from unistd.h: */ |
| @@ -47,14 +47,5 @@ void __clear_cache(void *beginning, void *end) · 21 unmodified lines | ||
| 47 | 47 | { |
| 48 | 48 | /* __ARM_NR_cacheflush is kernel private and should not be used in user space. |
| 49 | 49 | * However, there is no ARM asm parser in tcc so we use it for now */ |
| 50 | −#if 1 | |
| 51 | 50 | syscall(__ARM_NR_cacheflush, beginning, end, 0); |
| 52 | −#else | |
| 53 | − __asm__ ("push {r7}\n\t" | |
| 54 | − "mov r7, #0xf0002\n\t" | |
| 55 | − "mov r2, #0\n\t" | |
| 56 | − "swi 0\n\t" | |
| 57 | − "pop {r7}\n\t" | |
| 58 | − "ret"); | |
| 59 | −#endif | |
| 60 | 51 | } |
| @@ -3,26 +3,13 @@ · 2 unmodified lines | ||
| 3 | 3 | .global fetch_and_add_arm |
| 4 | 4 | .type fetch_and_add_arm, %function |
| 5 | 5 | fetch_and_add_arm: |
| 6 | −#ifdef __TINYC__ | |
| 7 | − .int 0xee070fba | |
| 8 | − .int 0xe1903f9f | |
| 9 | − .int 0xe0833001 | |
| 10 | − .int 0xe1802f93 | |
| 11 | − .int 0xe3520000 | |
| 12 | − .int 0x1afffffa | |
| 13 | − .int 0xee070fba | |
| 14 | − .int 0xe12fff1e | |
| 15 | −#else | |
| 16 | − .arch armv6 | |
| 17 | − | |
| 18 | − mcr p15, 0, r0, c7, c10, 5 | |
| 6 | + mcr p15, #0, r0, c7, c10, #5 | |
| 19 | 7 | .L0: |
| 20 | 8 | ldrex r3, [r0] |
| 21 | 9 | add r3, r3, r1 |
| 22 | 10 | strex r2, r3, [r0] |
| 23 | 11 | cmp r2, #0 |
| 24 | 12 | bne .L0 |
| 25 | − mcr p15, 0, r0, c7, c10, 5 | |
| 13 | + mcr p15, #0, r0, c7, c10, #5 | |
| 26 | 14 | bx lr |
| 27 | −#endif | |
| 28 | 15 | .size fetch_and_add_arm, .-fetch_and_add_arm |