arm-asm: For data processing instructions, support shifts and rotations.

Danny Milosavljevic committed 5 years ago

Commit daaa88c1 parent abef8f62 files · +52 −8Browse files

Unified · Split

2 files

arm-asm.c +48 −8
arm-tok.h +4 −0

 {
     Operand ops[3];
     int nb_ops;
+    Operand shift = {};
+    int nb_shift = 0;
+    uint32_t operands = 0;
     /* 16 entries per instruction for the different condition codes */
     uint32_t opcode_idx = (ARM_INSTRUCTION_GROUP(token) - TOK_ASM_andeq) >> 4;
-    for (nb_ops = 0; nb_ops < sizeof(ops)/sizeof(ops[0]); ++nb_ops) {
+    for (nb_ops = 0; nb_ops < sizeof(ops)/sizeof(ops[0]); ) {
+        if (tok == TOK_ASM_asl || tok == TOK_ASM_lsl || tok == TOK_ASM_lsr || tok == TOK_ASM_asr || tok == TOK_ASM_ror || tok == TOK_ASM_rrx)
+            break;
         parse_operand(s1, &ops[nb_ops]);
-        if (tok != ',') {
+        ++nb_ops;
-            ++nb_ops;
+        if (tok != ',')
             break;
-        }
         next(); // skip ','
     }
+    if (tok == ',')
+        next();
+    switch (tok) {
+    case TOK_ASM_asl:
+    case TOK_ASM_lsl:
+    case TOK_ASM_asr:
+    case TOK_ASM_lsr:
+    case TOK_ASM_ror:
+        switch (tok) {
+        case TOK_ASM_asl:
+            /* fallthrough */
+        case TOK_ASM_lsl:
+            operands |= ENCODE_BARREL_SHIFTER_MODE_LSL;
+            break;
+        case TOK_ASM_asr:
+            operands |= ENCODE_BARREL_SHIFTER_MODE_ASR;
+            break;
+        case TOK_ASM_lsr:
+            operands |= ENCODE_BARREL_SHIFTER_MODE_LSR;
+            break;
+        case TOK_ASM_ror:
+            operands |= ENCODE_BARREL_SHIFTER_MODE_ROR;
+            break;
+        }
+        next();
+        parse_operand(s1, &shift);
+        nb_shift = 1;
+        break;
+    case TOK_ASM_rrx:
+        next();
+        operands |= ENCODE_BARREL_SHIFTER_MODE_ROR;
+        break;
+    }
     if (nb_ops < 2)
         expect("at least two operands");
     else if (nb_ops == 2) {
         return;
     } else {
         uint32_t opcode = 0;
-        uint32_t operands = 0;
         // data processing (general case):
         // operands:
             operands |= ENCODE_RN(ops[1].reg);
         switch (ops[2].type) {
         case OP_REG32:
-            // TODO: Parse and encode shift.
             operands |= ops[2].reg;
             break;
         case OP_IM8:
-            // TODO: Parse and encode rotation.
             operands |= ENCODE_IMMEDIATE_FLAG;
             operands |= ops[2].e.v;
             break;
         case OP_IM8N: // immediate negative value
-            // TODO: Parse and encode rotation.
             operands |= ENCODE_IMMEDIATE_FLAG;
             /* Instruction swapping:
                0001 = EOR - Rd:= Op1 EOR Op2     -> difficult
             expect("(second source operand) register or immediate value");
         }
+        if (nb_shift) {
+            if (operands & ENCODE_IMMEDIATE_FLAG)
+                tcc_error("immediate rotation not implemented");
+            else
+                operands |= asm_encode_shift(&shift);
+        }
         /* S=0 and S=1 entries alternate one after another, in that order */
         opcode |= (opcode_idx & 1) ? ENCODE_SET_CONDITION_CODES : 0;
         asm_emit_opcode(token, opcode | operands);

arm-tok.h+4−0

@@ -28,6 +28,10 @@ · 27 unmodified lines
28	DEF_ASM(lr) /* alias for r14 */	28	DEF_ASM(lr) /* alias for r14 */
29	DEF_ASM(pc) /* alias for r15 */	29	DEF_ASM(pc) /* alias for r15 */
30		30
		31	/* data processing directives */
		32
		33	DEF_ASM(asl)
		34
31	#define ARM_INSTRUCTION_GROUP(tok) ((((tok) - TOK_ASM_nopeq) & 0xFFFFFFF0) + TOK_ASM_nopeq)	35	#define ARM_INSTRUCTION_GROUP(tok) ((((tok) - TOK_ASM_nopeq) & 0xFFFFFFF0) + TOK_ASM_nopeq)
32		36
33	/* Note: condition code is 4 bits */	37	/* Note: condition code is 4 bits */

arm-asm: For data processing instructions, support shifts and rotations.

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