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riscv: jal: Add pseudo instruction support

Ekaitz Zarraga committed 2 years ago

Commit e2d8eb31 parent 409007c1 file · +23 −4Browse files

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riscv64-asm.c+23−4
@@ -267,6 +267,26 @@ static void parse_mem_access_operands(TCCState *s1, Operand* ops){ · 266 unmodified lines
267267 }
268268 }
269269
270+/* This is special: First operand is optional */
271+static void asm_jal_opcode(TCCState *s1, int token){
272+ static const Operand ra = {.type = OP_REG, .reg = 1};
273+ Operand ops[2];
274+ parse_operand(s1, &ops[0]);
275+ if ( tok == ',')
276+ next();
277+ else {
278+ /* no more operands, it's the pseudoinstruction:
279+ * jal rs
280+ * Expand to:
281+ * jal ra, rs
282+ */
283+ asm_emit_j(token, 0x6f, &ra, &ops[0]);
284+ return;
285+ }
286+ parse_operand(s1, &ops[1]);
287+ asm_emit_j(token, 0x6f, &ops[0], &ops[1]);
288+}
289+
270290 /* This is special: It can be a pseudointruction or a instruction */
271291 static void asm_jalr_opcode(TCCState *s1, int token){
272292 static const Operand zimm = {.type = OP_IM12S};
@@ -418,9 +438,6 @@ static void asm_binary_opcode(TCCState* s1, int token) · 145 unmodified lines
418438 case TOK_ASM_auipc:
419439 asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]);
420440 return;
421− case TOK_ASM_jal:
422− asm_emit_j(token, 0x6f, ops, ops + 1);
423− return;
424441
425442 /* C extension */
426443 case TOK_ASM_c_add:
@@ -1100,7 +1117,6 @@ ST_FUNC void asm_opcode(TCCState *s1, int token) · 673 unmodified lines
11001117
11011118 case TOK_ASM_lui:
11021119 case TOK_ASM_auipc:
1103− case TOK_ASM_jal:
11041120 asm_binary_opcode(s1, token);
11051121 return;
11061122
@@ -1121,6 +1137,9 @@ ST_FUNC void asm_opcode(TCCState *s1, int token) · 14 unmodified lines
11211137 case TOK_ASM_jalr:
11221138 asm_jalr_opcode(s1, token); /* it can be a pseudo instruction too*/
11231139 break;
1140+ case TOK_ASM_jal:
1141+ asm_jal_opcode(s1, token); /* it can be a pseudo instruction too*/
1142+ break;
11241143
11251144 case TOK_ASM_add:
11261145 case TOK_ASM_addi:

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