| @@ -1,13 +1,17 @@ |
| 1 | 1 | /*************************************************************/ |
| 2 | 2 | /* |
| 3 | | − * ARM64 dummy assembler for TCC |
| 3 | + * ARM64 (AArch64) assembler for TCC |
| 4 | 4 | * |
| 5 | + * Based on ARM64 Architecture Reference Manual |
| 6 | + * Supports AArch64 assembler parsing and extended inline asm |
| 7 | + * with operands, constraints, and clobbers. |
| 5 | 8 | */ |
| 6 | 9 | |
| 7 | 10 | #ifdef TARGET_DEFS_ONLY |
| 8 | 11 | |
| 9 | 12 | #define CONFIG_TCC_ASM |
| 10 | | −#define NB_ASM_REGS 16 |
| 13 | +/* 32 general purpose + 32 SIMD/FP registers */ |
| 14 | +#define NB_ASM_REGS 64 |
| 11 | 15 | |
| 12 | 16 | ST_FUNC void g(int c); |
| 13 | 17 | ST_FUNC void gen_le16(int c); |
| @@ -16,13 +20,98 @@ ST_FUNC void gen_le32(int c); · 2 unmodified lines |
| 16 | 20 | /*************************************************************/ |
| 17 | 21 | #else |
| 18 | 22 | /*************************************************************/ |
| 23 | + |
| 19 | 24 | #define USING_GLOBALS |
| 20 | 25 | #include "tcc.h" |
| 21 | 26 | |
| 22 | | −static void asm_error(void) |
| 23 | | −{ |
| 24 | | − tcc_error("ARM asm not implemented."); |
| 25 | | −} |
| 27 | +/* Register type flags */ |
| 28 | +#define REG_X 0x01 /* 64-bit general purpose */ |
| 29 | +#define REG_W 0x02 /* 32-bit general purpose */ |
| 30 | +#define REG_V 0x04 /* 128-bit SIMD */ |
| 31 | +#define REG_D 0x08 /* 64-bit FP */ |
| 32 | +#define REG_S 0x10 /* 32-bit FP */ |
| 33 | +#define REG_H 0x20 /* 16-bit FP */ |
| 34 | +#define REG_B 0x40 /* 8-bit SIMD */ |
| 35 | + |
| 36 | +/* Operand types */ |
| 37 | +enum { |
| 38 | + OPT_REG, |
| 39 | + OPT_IM, |
| 40 | + OPT_ADDR, |
| 41 | + OPT_COND, |
| 42 | +}; |
| 43 | + |
| 44 | +#define OP_REG (1 << OPT_REG) |
| 45 | +#define OP_IM (1 << OPT_IM) |
| 46 | +#define OP_ADDR (1 << OPT_ADDR) |
| 47 | +#define OP_COND (1 << OPT_COND) |
| 48 | + |
| 49 | +/* Register allocation masks */ |
| 50 | +#define REG_OUT_MASK 0x01 |
| 51 | +#define REG_IN_MASK 0x02 |
| 52 | + |
| 53 | +#define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask) |
| 54 | + |
| 55 | +/* ARM64 register constants */ |
| 56 | +#define TREG_X0 0 |
| 57 | +#define TREG_X1 1 |
| 58 | +#define TREG_X2 2 |
| 59 | +#define TREG_X3 3 |
| 60 | +#define TREG_X4 4 |
| 61 | +#define TREG_X5 5 |
| 62 | +#define TREG_X6 6 |
| 63 | +#define TREG_X7 7 |
| 64 | +#define TREG_X8 8 |
| 65 | +#define TREG_X9 9 |
| 66 | +#define TREG_X10 10 |
| 67 | +#define TREG_X11 11 |
| 68 | +#define TREG_X12 12 |
| 69 | +#define TREG_X13 13 |
| 70 | +#define TREG_X14 14 |
| 71 | +#define TREG_X15 15 |
| 72 | +#define TREG_X16 16 |
| 73 | +#define TREG_X17 17 |
| 74 | +#define TREG_X18 18 |
| 75 | +#define TREG_X19 19 |
| 76 | +#define TREG_X20 20 |
| 77 | +#define TREG_X21 21 |
| 78 | +#define TREG_X22 22 |
| 79 | +#define TREG_X23 23 |
| 80 | +#define TREG_X24 24 |
| 81 | +#define TREG_X25 25 |
| 82 | +#define TREG_X26 26 |
| 83 | +#define TREG_X27 27 |
| 84 | +#define TREG_X28 28 |
| 85 | +#define TREG_X29 29 |
| 86 | +#define TREG_X30 30 |
| 87 | +#define TREG_SP 31 |
| 88 | + |
| 89 | +#ifdef TCC_TARGET_PE |
| 90 | +#define ARM64_FREG_BASE 19 |
| 91 | +#else |
| 92 | +#define ARM64_FREG_BASE 20 |
| 93 | +#endif |
| 94 | +#define ARM64_FREG_LAST (ARM64_FREG_BASE + 7) |
| 95 | + |
| 96 | +typedef struct Operand { |
| 97 | + uint32_t type; |
| 98 | + int8_t reg; |
| 99 | + int8_t reg2; |
| 100 | + uint8_t reg_type; |
| 101 | + uint8_t shift; |
| 102 | + uint8_t addr_mode; |
| 103 | + int reg_tok; |
| 104 | + ExprValue e; |
| 105 | +} Operand; |
| 106 | + |
| 107 | +enum { |
| 108 | + ADDR_OFF, |
| 109 | + ADDR_PRE, |
| 110 | + ADDR_POST, |
| 111 | +}; |
| 112 | + |
| 113 | +/* Forward declaration */ |
| 114 | +static void parse_addr_operand(TCCState *s1, Operand *op); |
| 26 | 115 | |
| 27 | 116 | /* XXX: make it faster ? */ |
| 28 | 117 | ST_FUNC void g(int c) |
| @@ -37,16 +126,16 @@ ST_FUNC void g(int c) · 8 unmodified lines |
| 37 | 126 | ind = ind1; |
| 38 | 127 | } |
| 39 | 128 | |
| 40 | | −ST_FUNC void gen_le16 (int i) |
| 129 | +ST_FUNC void gen_le16(int c) |
| 41 | 130 | { |
| 42 | | − g(i); |
| 43 | | − g(i>>8); |
| 131 | + g(c); |
| 132 | + g(c >> 8); |
| 44 | 133 | } |
| 45 | 134 | |
| 46 | | −ST_FUNC void gen_le32 (int i) |
| 135 | +ST_FUNC void gen_le32(int c) |
| 47 | 136 | { |
| 48 | | − gen_le16(i); |
| 49 | | − gen_le16(i>>16); |
| 137 | + gen_le16(c); |
| 138 | + gen_le16(c >> 16); |
| 50 | 139 | } |
| 51 | 140 | |
| 52 | 141 | ST_FUNC void gen_expr32(ExprValue *pe) |
| @@ -54,22 +143,1889 @@ ST_FUNC void gen_expr32(ExprValue *pe) · 1 unmodified line |
| 54 | 143 | gen_le32(pe->v); |
| 55 | 144 | } |
| 56 | 145 | |
| 146 | +/* Emit 32-bit instruction */ |
| 147 | +static void emit_instr32(uint32_t val) |
| 148 | +{ |
| 149 | + if (nocode_wanted) |
| 150 | + return; |
| 151 | + if (ind + 4 > cur_text_section->data_allocated) |
| 152 | + section_realloc(cur_text_section, ind + 4); |
| 153 | + write32le(cur_text_section->data + ind, val); |
| 154 | + ind += 4; |
| 155 | +} |
| 156 | + |
| 157 | +/* Parse ARM64 register token for assembler syntax. */ |
| 158 | +static int arm64_parse_asm_reg(int t) |
| 159 | +{ |
| 160 | + /* X registers (64-bit) */ |
| 161 | + if (t >= TOK_ASM_x0 && t <= TOK_ASM_x30) |
| 162 | + return t - TOK_ASM_x0; |
| 163 | + /* W registers (32-bit) */ |
| 164 | + if (t >= TOK_ASM_w0 && t <= TOK_ASM_w30) |
| 165 | + return t - TOK_ASM_w0; |
| 166 | + /* V registers (128-bit SIMD) */ |
| 167 | + if (t >= TOK_ASM_v0 && t <= TOK_ASM_v31) |
| 168 | + return (t - TOK_ASM_v0) + 32; |
| 169 | + /* D registers (64-bit FP) */ |
| 170 | + if (t >= TOK_ASM_d0 && t <= TOK_ASM_d31) |
| 171 | + return (t - TOK_ASM_d0) + 32; |
| 172 | + /* S registers (32-bit FP) */ |
| 173 | + if (t >= TOK_ASM_s0 && t <= TOK_ASM_s31) |
| 174 | + return (t - TOK_ASM_s0) + 32; |
| 175 | + /* H registers (16-bit FP) */ |
| 176 | + if (t >= TOK_ASM_h0 && t <= TOK_ASM_h31) |
| 177 | + return (t - TOK_ASM_h0) + 32; |
| 178 | + /* B registers (8-bit SIMD) */ |
| 179 | + if (t >= TOK_ASM_b0 && t <= TOK_ASM_b31) |
| 180 | + return (t - TOK_ASM_b0) + 32; |
| 181 | + /* Special registers */ |
| 182 | + if (t == TOK_ASM_sp || t == TOK_ASM_xzr || t == TOK_ASM_wzr) |
| 183 | + return 31; /* SP/ZR encoded as 31 */ |
| 184 | + return -1; |
| 185 | +} |
| 186 | + |
| 187 | +/* Get register type from token */ |
| 188 | +static uint8_t get_reg_type(int t) |
| 189 | +{ |
| 190 | + if (t >= TOK_ASM_x0 && t <= TOK_ASM_x30) |
| 191 | + return REG_X; |
| 192 | + if (t >= TOK_ASM_w0 && t <= TOK_ASM_w30) |
| 193 | + return REG_W; |
| 194 | + if (t >= TOK_ASM_v0 && t <= TOK_ASM_v31) |
| 195 | + return REG_V; |
| 196 | + if (t >= TOK_ASM_d0 && t <= TOK_ASM_d31) |
| 197 | + return REG_D; |
| 198 | + if (t >= TOK_ASM_s0 && t <= TOK_ASM_s31) |
| 199 | + return REG_S; |
| 200 | + if (t >= TOK_ASM_h0 && t <= TOK_ASM_h31) |
| 201 | + return REG_H; |
| 202 | + if (t >= TOK_ASM_b0 && t <= TOK_ASM_b31) |
| 203 | + return REG_B; |
| 204 | + /* Special registers - sp is 64-bit, xzr is 64-bit, wzr is 32-bit */ |
| 205 | + if (t == TOK_ASM_sp || t == TOK_ASM_xzr) |
| 206 | + return REG_X; |
| 207 | + if (t == TOK_ASM_wzr) |
| 208 | + return REG_W; |
| 209 | + return REG_X; |
| 210 | +} |
| 211 | + |
| 212 | +/* Parse condition code */ |
| 213 | +static int parse_condition(int t) |
| 214 | +{ |
| 215 | + switch (t) { |
| 216 | + case TOK_ASM_eq: return 0; |
| 217 | + case TOK_ASM_ne: return 1; |
| 218 | + case TOK_ASM_cs: |
| 219 | + case TOK_ASM_hs: return 2; |
| 220 | + case TOK_ASM_cc: |
| 221 | + case TOK_ASM_lo: return 3; |
| 222 | + case TOK_ASM_mi: return 4; |
| 223 | + case TOK_ASM_pl: return 5; |
| 224 | + case TOK_ASM_vs: return 6; |
| 225 | + case TOK_ASM_vc: return 7; |
| 226 | + case TOK_ASM_hi: return 8; |
| 227 | + case TOK_ASM_ls: return 9; |
| 228 | + case TOK_ASM_ge: return 10; |
| 229 | + case TOK_ASM_lt: return 11; |
| 230 | + case TOK_ASM_gt: return 12; |
| 231 | + case TOK_ASM_le: return 13; |
| 232 | + case TOK_ASM_al: return 14; |
| 233 | + default: return -1; |
| 234 | + } |
| 235 | +} |
| 236 | + |
| 237 | +static int parse_barrier_option_name(int t) |
| 238 | +{ |
| 239 | + const char *name; |
| 240 | + |
| 241 | + if (t < TOK_IDENT) |
| 242 | + return -1; |
| 243 | + name = get_tok_str(t, NULL); |
| 244 | + if (!strcmp(name, "oshld")) return 0x1; |
| 245 | + if (!strcmp(name, "oshst")) return 0x2; |
| 246 | + if (!strcmp(name, "osh")) return 0x3; |
| 247 | + if (!strcmp(name, "nshld")) return 0x5; |
| 248 | + if (!strcmp(name, "nshst")) return 0x6; |
| 249 | + if (!strcmp(name, "nsh")) return 0x7; |
| 250 | + if (!strcmp(name, "ishld")) return 0x9; |
| 251 | + if (!strcmp(name, "ishst")) return 0xA; |
| 252 | + if (!strcmp(name, "ish")) return 0xB; |
| 253 | + if (!strcmp(name, "ld")) return 0xD; |
| 254 | + if (!strcmp(name, "st")) return 0xE; |
| 255 | + if (!strcmp(name, "sy")) return 0xF; |
| 256 | + return -1; |
| 257 | +} |
| 258 | + |
| 259 | +static int arm64_parse_regvar(int t) |
| 260 | +{ |
| 261 | + if (t >= TOK_ASM_x0 && t <= TOK_ASM_x30) |
| 262 | + return t - TOK_ASM_x0; |
| 263 | + if (t >= TOK_ASM_v0 && t <= TOK_ASM_v7) |
| 264 | + return ARM64_FREG_BASE + (t - TOK_ASM_v0); |
| 265 | + if (t >= TOK_ASM_d0 && t <= TOK_ASM_d7) |
| 266 | + return ARM64_FREG_BASE + (t - TOK_ASM_d0); |
| 267 | + if (t >= TOK_ASM_s0 && t <= TOK_ASM_s7) |
| 268 | + return ARM64_FREG_BASE + (t - TOK_ASM_s0); |
| 269 | + if (t >= TOK_ASM_h0 && t <= TOK_ASM_h7) |
| 270 | + return ARM64_FREG_BASE + (t - TOK_ASM_h0); |
| 271 | + if (t >= TOK_ASM_b0 && t <= TOK_ASM_b7) |
| 272 | + return ARM64_FREG_BASE + (t - TOK_ASM_b0); |
| 273 | + return -1; |
| 274 | +} |
| 275 | + |
| 276 | +/* Parse a single operand */ |
| 277 | +static void parse_operand(TCCState *s1, Operand *op) |
| 278 | +{ |
| 279 | + int reg; |
| 280 | + |
| 281 | + op->type = 0; |
| 282 | + op->reg = -1; |
| 283 | + op->reg2 = -1; |
| 284 | + op->reg_type = 0; |
| 285 | + op->shift = 0; |
| 286 | + op->addr_mode = ADDR_OFF; |
| 287 | + op->reg_tok = 0; |
| 288 | + |
| 289 | + /* Address operand in brackets [xn, ...] */ |
| 290 | + if (tok == '[') { |
| 291 | + parse_addr_operand(s1, op); |
| 292 | + return; |
| 293 | + } |
| 294 | + |
| 295 | + /* Register */ |
| 296 | + reg = arm64_parse_asm_reg(tok); |
| 297 | + if (reg >= 0) { |
| 298 | + op->type = OP_REG; |
| 299 | + op->reg = reg; |
| 300 | + op->reg_type = get_reg_type(tok); |
| 301 | + op->reg_tok = tok; |
| 302 | + next(); |
| 303 | + return; |
| 304 | + } |
| 305 | + |
| 306 | + /* Condition code */ |
| 307 | + reg = parse_condition(tok); |
| 308 | + if (reg >= 0) { |
| 309 | + op->type = OP_COND; |
| 310 | + op->reg = reg; |
| 311 | + next(); |
| 312 | + return; |
| 313 | + } |
| 314 | + |
| 315 | + /* Immediate or address expression */ |
| 316 | + if (tok == '#' || tok == ':' || tok == '@' || tok == '$') { |
| 317 | + next(); |
| 318 | + asm_expr(s1, &op->e); |
| 319 | + op->type = OP_IM; |
| 320 | + } else if (tok >= TOK_IDENT) { |
| 321 | + tcc_error("invalid operand '%s'", get_tok_str(tok, &tokc)); |
| 322 | + op->type = OP_IM; |
| 323 | + } else { |
| 324 | + asm_expr(s1, &op->e); |
| 325 | + op->type = OP_IM; |
| 326 | + } |
| 327 | +} |
| 328 | + |
| 329 | +/* Parse a symbolic/immediate expression operand used by branch instructions. */ |
| 330 | +static void parse_expr_operand(TCCState *s1, Operand *op) |
| 331 | +{ |
| 332 | + op->type = OP_IM; |
| 333 | + op->reg = -1; |
| 334 | + op->reg2 = -1; |
| 335 | + op->reg_type = 0; |
| 336 | + op->shift = 0; |
| 337 | + op->addr_mode = ADDR_OFF; |
| 338 | + op->reg_tok = 0; |
| 339 | + |
| 340 | + if (tok == '#' || tok == ':' || tok == '@' || tok == '$') |
| 341 | + next(); |
| 342 | + asm_expr(s1, &op->e); |
| 343 | +} |
| 344 | + |
| 345 | +/* Parse address operand in brackets [xn, ...] */ |
| 346 | +static void parse_addr_operand(TCCState *s1, Operand *op) |
| 347 | +{ |
| 348 | + int reg; |
| 349 | + |
| 350 | + op->type = OP_ADDR; |
| 351 | + op->reg = -1; |
| 352 | + op->reg2 = -1; |
| 353 | + op->e.v = 0; |
| 354 | + op->e.sym = NULL; |
| 355 | + op->addr_mode = ADDR_OFF; |
| 356 | + op->reg_tok = 0; |
| 357 | + |
| 358 | + skip('['); |
| 359 | + reg = arm64_parse_asm_reg(tok); |
| 360 | + if (reg < 0 || reg >= 32) { |
| 361 | + tcc_error("invalid register in address operand"); |
| 362 | + return; |
| 363 | + } |
| 364 | + op->reg = reg; |
| 365 | + op->reg_tok = tok; |
| 366 | + next(); |
| 367 | + /* Check for offset */ |
| 368 | + if (tok == ',') { |
| 369 | + next(); |
| 370 | + if (tok == '#' || tok == '@' || tok == '$') |
| 371 | + next(); |
| 372 | + asm_expr(s1, &op->e); |
| 373 | + } |
| 374 | + skip(']'); |
| 375 | + if (tok == '!') { |
| 376 | + op->addr_mode = ADDR_PRE; |
| 377 | + next(); |
| 378 | + } else if (tok == ',') { |
| 379 | + op->addr_mode = ADDR_POST; |
| 380 | + next(); |
| 381 | + if (tok == '#' || tok == '@' || tok == '$') |
| 382 | + next(); |
| 383 | + asm_expr(s1, &op->e); |
| 384 | + } |
| 385 | +} |
| 386 | + |
| 387 | +/* Generate MOVZ/MOVN/MOVK with base opcode */ |
| 388 | +static void gen_mov_with_base(int rd, uint16_t imm, int shift, |
| 389 | + int is_64bit, uint32_t base_opcode) |
| 390 | +{ |
| 391 | + uint32_t instr = base_opcode; |
| 392 | + if (is_64bit) instr |= ARM64_SF(1); |
| 393 | + /* shift is halfword index (0-3), encode as LSL #0/16/32/48 */ |
| 394 | + instr |= ARM64_IMM_HW(imm, shift); |
| 395 | + instr |= ARM64_RD(rd); |
| 396 | + emit_instr32(instr); |
| 397 | +} |
| 398 | + |
| 399 | +static void gen_movz(int rd, uint16_t imm, int shift, int is_64bit) |
| 400 | +{ |
| 401 | + gen_mov_with_base(rd, imm, shift, is_64bit, ARM64_MOVZ); |
| 402 | +} |
| 403 | + |
| 404 | +/* Generate MOVN instruction */ |
| 405 | +static void gen_movn(int rd, uint16_t imm, int shift, int is_64bit) |
| 406 | +{ |
| 407 | + gen_mov_with_base(rd, imm, shift, is_64bit, ARM64_MOVN); |
| 408 | +} |
| 409 | + |
| 410 | +/* Generate MOVK instruction */ |
| 411 | +static void gen_movk(int rd, uint16_t imm, int shift, int is_64bit) |
| 412 | +{ |
| 413 | + gen_mov_with_base(rd, imm, shift, is_64bit, ARM64_MOVK); |
| 414 | +} |
| 415 | + |
| 416 | +/* Generate ADD (immediate) */ |
| 417 | +static void gen_add_imm(int rd, int rn, uint32_t imm, int is_64bit, int setflags) |
| 418 | +{ |
| 419 | + uint32_t instr = ARM64_ADD_IMM; |
| 420 | + uint32_t imm12; |
| 421 | + |
| 422 | + if (is_64bit) instr |= ARM64_SF(1); |
| 423 | + if (setflags) instr |= ARM64_S(1); |
| 424 | + |
| 425 | + if (imm <= 0xFFF) { |
| 426 | + imm12 = imm; |
| 427 | + } else if (!(imm & 0xFFF) && (imm >> 12) <= 0xFFF) { |
| 428 | + instr |= ARM64_SH(1); |
| 429 | + imm12 = imm >> 12; |
| 430 | + } else { |
| 431 | + tcc_error("add immediate out of range"); |
| 432 | + return; |
| 433 | + } |
| 434 | + |
| 435 | + instr |= ARM64_IMM12(imm12); |
| 436 | + instr |= ARM64_RN(rn); |
| 437 | + instr |= ARM64_RD(rd); |
| 438 | + emit_instr32(instr); |
| 439 | +} |
| 440 | + |
| 441 | +/* Generate SUB (immediate) */ |
| 442 | +static void gen_sub_imm(int rd, int rn, uint32_t imm, int is_64bit, int setflags) |
| 443 | +{ |
| 444 | + uint32_t instr = ARM64_SUB_IMM; |
| 445 | + uint32_t imm12; |
| 446 | + |
| 447 | + if (is_64bit) instr |= ARM64_SF(1); |
| 448 | + if (setflags) instr |= ARM64_S(1); |
| 449 | + |
| 450 | + if (imm <= 0xFFF) { |
| 451 | + imm12 = imm; |
| 452 | + } else if (!(imm & 0xFFF) && (imm >> 12) <= 0xFFF) { |
| 453 | + instr |= ARM64_SH(1); |
| 454 | + imm12 = imm >> 12; |
| 455 | + } else { |
| 456 | + tcc_error("sub immediate out of range"); |
| 457 | + return; |
| 458 | + } |
| 459 | + |
| 460 | + instr |= ARM64_IMM12(imm12); |
| 461 | + instr |= ARM64_RN(rn); |
| 462 | + instr |= ARM64_RD(rd); |
| 463 | + emit_instr32(instr); |
| 464 | +} |
| 465 | + |
| 466 | +/* Generate data processing register instruction */ |
| 467 | +static void gen_dp_reg(uint32_t opcode, int rd, int rn, int rm, int is_64bit) |
| 468 | +{ |
| 469 | + uint32_t instr = opcode; |
| 470 | + if (is_64bit) instr |= ARM64_SF(1); |
| 471 | + instr |= ARM64_RM(rm); |
| 472 | + instr |= ARM64_RN(rn); |
| 473 | + instr |= ARM64_RD(rd); |
| 474 | + emit_instr32(instr); |
| 475 | +} |
| 476 | + |
| 477 | +/* Generate LDR/STR (unsigned immediate) */ |
| 478 | +static void gen_ldst_imm(uint32_t base_opcode, int rt, int rn, |
| 479 | + int32_t offset, int size_log2) |
| 480 | +{ |
| 481 | + uint32_t instr = base_opcode; |
| 482 | + uint32_t unscaled_opcode = 0; |
| 483 | + uint32_t imm12; |
| 484 | + |
| 485 | + if (offset >= 0 && !(offset & ((1 << size_log2) - 1))) { |
| 486 | + imm12 = offset >> size_log2; |
| 487 | + if (imm12 <= 0xFFF) { |
| 488 | + instr |= ARM64_IMM12(imm12); |
| 489 | + instr |= ARM64_RN(rn); |
| 490 | + instr |= ARM64_RT(rt); |
| 491 | + emit_instr32(instr); |
| 492 | + return; |
| 493 | + } |
| 494 | + } |
| 495 | + |
| 496 | + switch (base_opcode) { |
| 497 | + case ARM64_LDR_X: unscaled_opcode = ARM64_LDUR_X; break; |
| 498 | + case ARM64_LDR_W: unscaled_opcode = ARM64_LDUR_W; break; |
| 499 | + case ARM64_LDR_B: unscaled_opcode = ARM64_LDUR_B; break; |
| 500 | + case ARM64_LDR_H: unscaled_opcode = ARM64_LDUR_H; break; |
| 501 | + case ARM64_LDR_D: unscaled_opcode = ARM64_LDUR_D_SIMD; break; |
| 502 | + case ARM64_STR_X: unscaled_opcode = ARM64_STUR_X; break; |
| 503 | + case ARM64_STR_W: unscaled_opcode = ARM64_STUR_W; break; |
| 504 | + case ARM64_STR_B: unscaled_opcode = ARM64_STUR_B; break; |
| 505 | + case ARM64_STR_H: unscaled_opcode = ARM64_STUR_H; break; |
| 506 | + case ARM64_STR_D: unscaled_opcode = ARM64_STUR_D_SIMD; break; |
| 507 | + } |
| 508 | + |
| 509 | + if (unscaled_opcode && offset >= -256 && offset <= 255) { |
| 510 | + instr = unscaled_opcode; |
| 511 | + instr |= ((uint32_t)offset & 0x1FFU) << 12; |
| 512 | + instr |= ARM64_RN(rn); |
| 513 | + instr |= ARM64_RT(rt); |
| 514 | + emit_instr32(instr); |
| 515 | + return; |
| 516 | + } |
| 517 | + |
| 518 | + if (offset & ((1 << size_log2) - 1)) |
| 519 | + tcc_error("invalid load/store offset"); |
| 520 | + tcc_error("load/store offset out of range"); |
| 521 | +} |
| 522 | + |
| 523 | +/* Generate STP/LDP (signed immediate) */ |
| 524 | +static void gen_ldst_pair(uint32_t base_opcode, int rt, int rt2, int rn, |
| 525 | + int32_t offset, int size_log2) |
| 526 | +{ |
| 527 | + int32_t imm7; |
| 528 | + uint32_t instr = base_opcode; |
| 529 | + |
| 530 | + if (offset & ((1 << size_log2) - 1)) |
| 531 | + tcc_error("invalid pair load/store offset"); |
| 532 | + imm7 = offset >> size_log2; |
| 533 | + if (imm7 < -64 || imm7 > 63) |
| 534 | + tcc_error("pair load/store offset out of range"); |
| 535 | + |
| 536 | + instr |= ARM64_IMM7(imm7); |
| 537 | + instr |= ARM64_RT2(rt2); |
| 538 | + instr |= ARM64_RN(rn); |
| 539 | + instr |= ARM64_RT(rt); |
| 540 | + emit_instr32(instr); |
| 541 | +} |
| 542 | + |
| 543 | +/* Generate B (branch) */ |
| 544 | +/* Generate B/BL with base opcode */ |
| 545 | +static void gen_b_or_bl(int32_t offset, uint32_t base_opcode) |
| 546 | +{ |
| 547 | + uint32_t instr = base_opcode; |
| 548 | + instr |= ARM64_OFFSET26(offset); |
| 549 | + emit_instr32(instr); |
| 550 | +} |
| 551 | + |
| 552 | +static void gen_b(int32_t offset) |
| 553 | +{ |
| 554 | + gen_b_or_bl(offset, ARM64_B); |
| 555 | +} |
| 556 | + |
| 557 | +/* Generate BL (branch with link) */ |
| 558 | +static void gen_bl(int32_t offset) |
| 559 | +{ |
| 560 | + gen_b_or_bl(offset, ARM64_BL); |
| 561 | +} |
| 562 | + |
| 563 | +/* Generate BR (branch to register) */ |
| 564 | +static void gen_br(int rn) |
| 565 | +{ |
| 566 | + uint32_t instr = ARM64_BR; |
| 567 | + instr |= ARM64_RN(rn); |
| 568 | + emit_instr32(instr); |
| 569 | +} |
| 570 | + |
| 571 | +/* Generate BLR (branch with link to register) */ |
| 572 | +static void gen_blr(int rn) |
| 573 | +{ |
| 574 | + uint32_t instr = ARM64_BLR; |
| 575 | + instr |= ARM64_RN(rn); |
| 576 | + emit_instr32(instr); |
| 577 | +} |
| 578 | + |
| 579 | +/* Generate RET */ |
| 580 | +static void gen_ret(int rn) |
| 581 | +{ |
| 582 | + uint32_t instr = ARM64_RET; |
| 583 | + instr |= ARM64_RN(rn); |
| 584 | + emit_instr32(instr); |
| 585 | +} |
| 586 | + |
| 587 | +/* Generate conditional branch */ |
| 588 | +static void gen_b_cond(int cond, int32_t offset) |
| 589 | +{ |
| 590 | + uint32_t instr = ARM64_B_COND; |
| 591 | + instr |= ARM64_OFFSET19(offset); |
| 592 | + instr |= ARM64_COND(cond); |
| 593 | + emit_instr32(instr); |
| 594 | +} |
| 595 | + |
| 596 | +/* Generate CBZ */ |
| 597 | +/* Generate CBZ/CBNZ with base opcode */ |
| 598 | +static void gen_cbz_or_cbnz(int rt, int32_t offset, int is_64bit, uint32_t base_opcode) |
| 599 | +{ |
| 600 | + uint32_t instr = base_opcode; |
| 601 | + if (is_64bit) instr |= ARM64_SF(1); |
| 602 | + instr |= ARM64_OFFSET19(offset); |
| 603 | + instr |= ARM64_RT(rt); |
| 604 | + emit_instr32(instr); |
| 605 | +} |
| 606 | + |
| 607 | +static void gen_cbz(int rt, int32_t offset, int is_64bit) |
| 608 | +{ |
| 609 | + gen_cbz_or_cbnz(rt, offset, is_64bit, ARM64_CBZ); |
| 610 | +} |
| 611 | + |
| 612 | +/* Generate CBNZ */ |
| 613 | +static void gen_cbnz(int rt, int32_t offset, int is_64bit) |
| 614 | +{ |
| 615 | + gen_cbz_or_cbnz(rt, offset, is_64bit, ARM64_CBNZ); |
| 616 | +} |
| 617 | + |
| 618 | +/* Generate MOV (register) - ORR with zero register */ |
| 619 | +static void gen_mov_reg(int rd, int rm, int is_64bit) |
| 620 | +{ |
| 621 | + uint32_t instr = ARM64_MOV_REG; |
| 622 | + if (is_64bit) instr |= ARM64_SF(1); |
| 623 | + instr |= ARM64_RM(rm); |
| 624 | + instr |= ARM64_RD(rd); |
| 625 | + emit_instr32(instr); |
| 626 | +} |
| 627 | + |
| 628 | +static int arm64_asm_encode_bimm64(uint64_t x) |
| 629 | +{ |
| 630 | + int neg, rep, pos, len; |
| 631 | + |
| 632 | + neg = x & 1; |
| 633 | + if (neg) |
| 634 | + x = ~x; |
| 635 | + if (!x) |
| 636 | + return -1; |
| 637 | + |
| 638 | + if (x >> 2 == (x & ((((uint64_t)1) << (64 - 2)) - 1))) |
| 639 | + rep = 2, x &= (((uint64_t)1) << 2) - 1; |
| 640 | + else if (x >> 4 == (x & ((((uint64_t)1) << (64 - 4)) - 1))) |
| 641 | + rep = 4, x &= (((uint64_t)1) << 4) - 1; |
| 642 | + else if (x >> 8 == (x & ((((uint64_t)1) << (64 - 8)) - 1))) |
| 643 | + rep = 8, x &= (((uint64_t)1) << 8) - 1; |
| 644 | + else if (x >> 16 == (x & ((((uint64_t)1) << (64 - 16)) - 1))) |
| 645 | + rep = 16, x &= (((uint64_t)1) << 16) - 1; |
| 646 | + else if (x >> 32 == (x & ((((uint64_t)1) << (64 - 32)) - 1))) |
| 647 | + rep = 32, x &= (((uint64_t)1) << 32) - 1; |
| 648 | + else |
| 649 | + rep = 64; |
| 650 | + |
| 651 | + pos = 0; |
| 652 | + if (!(x & ((((uint64_t)1) << 32) - 1))) |
| 653 | + x >>= 32, pos += 32; |
| 654 | + if (!(x & ((((uint64_t)1) << 16) - 1))) |
| 655 | + x >>= 16, pos += 16; |
| 656 | + if (!(x & ((((uint64_t)1) << 8) - 1))) |
| 657 | + x >>= 8, pos += 8; |
| 658 | + if (!(x & ((((uint64_t)1) << 4) - 1))) |
| 659 | + x >>= 4, pos += 4; |
| 660 | + if (!(x & ((((uint64_t)1) << 2) - 1))) |
| 661 | + x >>= 2, pos += 2; |
| 662 | + if (!(x & ((((uint64_t)1) << 1) - 1))) |
| 663 | + x >>= 1, pos += 1; |
| 664 | + |
| 665 | + len = 0; |
| 666 | + if (!(~x & ((((uint64_t)1) << 32) - 1))) |
| 667 | + x >>= 32, len += 32; |
| 668 | + if (!(~x & ((((uint64_t)1) << 16) - 1))) |
| 669 | + x >>= 16, len += 16; |
| 670 | + if (!(~x & ((((uint64_t)1) << 8) - 1))) |
| 671 | + x >>= 8, len += 8; |
| 672 | + if (!(~x & ((((uint64_t)1) << 4) - 1))) |
| 673 | + x >>= 4, len += 4; |
| 674 | + if (!(~x & ((((uint64_t)1) << 2) - 1))) |
| 675 | + x >>= 2, len += 2; |
| 676 | + if (!(~x & ((((uint64_t)1) << 1) - 1))) |
| 677 | + x >>= 1, len += 1; |
| 678 | + |
| 679 | + if (x) |
| 680 | + return -1; |
| 681 | + if (neg) { |
| 682 | + pos = (pos + len) & (rep - 1); |
| 683 | + len = rep - len; |
| 684 | + } |
| 685 | + return ((0x1000 & rep << 6) | (((rep - 1) ^ 31) << 1 & 63) | |
| 686 | + ((rep - pos) & (rep - 1)) << 6 | (len - 1)); |
| 687 | +} |
| 688 | + |
| 689 | +static void gen_logical_imm(uint32_t opcode, int rd, int rn, |
| 690 | + uint64_t imm, int is_64bit) |
| 691 | +{ |
| 692 | + uint32_t instr; |
| 693 | + uint64_t val; |
| 694 | + int enc; |
| 695 | + |
| 696 | + if (is_64bit) |
| 697 | + val = imm; |
| 698 | + else { |
| 699 | + val = (uint32_t)imm; |
| 700 | + val |= val << 32; |
| 701 | + } |
| 702 | + |
| 703 | + enc = arm64_asm_encode_bimm64(val); |
| 704 | + if (enc < 0) { |
| 705 | + tcc_error("logical immediate out of range"); |
| 706 | + return; |
| 707 | + } |
| 708 | + |
| 709 | + instr = opcode; |
| 710 | + if (is_64bit) |
| 711 | + instr |= ARM64_SF(1); |
| 712 | + instr |= ARM64_N(enc >> 12); |
| 713 | + instr |= ARM64_IMM_R(enc >> 6); |
| 714 | + instr |= ARM64_IMM_S(enc); |
| 715 | + instr |= ARM64_RN(rn); |
| 716 | + instr |= ARM64_RD(rd); |
| 717 | + emit_instr32(instr); |
| 718 | +} |
| 719 | + |
| 720 | +/* return the constraint priority (we allocate first the lowest |
| 721 | + numbered constraints) */ |
| 722 | +static inline int constraint_priority(const char *str) |
| 723 | +{ |
| 724 | + int priority, c, pr; |
| 725 | + |
| 726 | + priority = 0; |
| 727 | + for (;;) { |
| 728 | + c = *str++; |
| 729 | + if (c == '\0') |
| 730 | + break; |
| 731 | + switch (c) { |
| 732 | + case '=': |
| 733 | + case '+': |
| 734 | + case '&': |
| 735 | + continue; |
| 736 | + case 'r': |
| 737 | + pr = 1; |
| 738 | + break; |
| 739 | + case 'w': |
| 740 | + case 'f': |
| 741 | + case 'x': |
| 742 | + case 'y': |
| 743 | + pr = 3; |
| 744 | + break; |
| 745 | + case 'm': |
| 746 | + case 'Q': |
| 747 | + pr = 4; |
| 748 | + break; |
| 749 | + case 'i': |
| 750 | + case 'S': |
| 751 | + pr = 5; |
| 752 | + break; |
| 753 | + case 'U': |
| 754 | + if (str[0] == 'm' && str[1] == 'p') { |
| 755 | + str += 2; |
| 756 | + pr = 4; |
| 757 | + break; |
| 758 | + } |
| 759 | + tcc_warning("unknown constraint '%c'", c); |
| 760 | + pr = 0; |
| 761 | + break; |
| 762 | + case 'I': |
| 763 | + case 'J': |
| 764 | + case 'K': |
| 765 | + case 'L': |
| 766 | + case 'M': |
| 767 | + case 'N': |
| 768 | + case 'Z': |
| 769 | + pr = 6; |
| 770 | + break; |
| 771 | + case 'n': |
| 772 | + pr = 7; |
| 773 | + break; |
| 774 | + case 'g': |
| 775 | + pr = 8; |
| 776 | + break; |
| 777 | + default: |
| 778 | + tcc_warning("unknown constraint '%c'", c); |
| 779 | + pr = 0; |
| 780 | + break; |
| 781 | + } |
| 782 | + if (pr > priority) |
| 783 | + priority = pr; |
| 784 | + } |
| 785 | + return priority; |
| 786 | +} |
| 787 | + |
| 788 | +static const char *skip_constraint_modifiers(const char *p) |
| 789 | +{ |
| 790 | + while (*p == '=' || *p == '&' || *p == '+' || *p == '%') |
| 791 | + p++; |
| 792 | + return p; |
| 793 | +} |
| 794 | + |
| 795 | +static int is_valid_add_imm(int64_t val) |
| 796 | +{ |
| 797 | + return val >= 0 && val <= 4095; |
| 798 | +} |
| 799 | + |
| 800 | +static int is_valid_logical_imm(int64_t val, int bits) |
| 801 | +{ |
| 802 | + uint64_t uval; |
| 803 | + |
| 804 | + uval = (uint64_t)val; |
| 805 | + if (bits == 32) { |
| 806 | + uval = (uint32_t)uval; |
| 807 | + uval |= uval << 32; |
| 808 | + } |
| 809 | + return arm64_asm_encode_bimm64(uval) >= 0; |
| 810 | +} |
| 811 | + |
| 812 | +static int is_valid_movw_imm(int64_t val) |
| 813 | +{ |
| 814 | + uint64_t uval = (uint64_t)val; |
| 815 | + |
| 816 | + if (uval <= 0xFFFF) |
| 817 | + return 1; |
| 818 | + if (uval >= 0xFFFF0000 && (uval & 0xFFFF) == 0) |
| 819 | + return 1; |
| 820 | + if (uval >= 0xFFFF00000000ULL && (uval & 0xFFFFFFFFULL) == 0) |
| 821 | + return 1; |
| 822 | + if ((uval & 0xFFFFFFFF00000000ULL) == 0) |
| 823 | + return 1; |
| 824 | + |
| 825 | + return 0; |
| 826 | +} |
| 827 | + |
| 828 | +static int is_valid_movw_shift(int shift, int is_64bit) |
| 829 | +{ |
| 830 | + if (shift < 0 || (shift & 15)) |
| 831 | + return 0; |
| 832 | + if (shift > (is_64bit ? 48 : 16)) |
| 833 | + return 0; |
| 834 | + return 1; |
| 835 | +} |
| 836 | + |
| 837 | +static int arm64_memory_is_base_only(const SValue *sv) |
| 838 | +{ |
| 839 | + int r; |
| 840 | + |
| 841 | + r = sv->r; |
| 842 | + if ((r & VT_VALMASK) == VT_CONST) |
| 843 | + return 0; |
| 844 | + if ((r & VT_VALMASK) == VT_LOCAL) |
| 845 | + return 0; |
| 846 | + if ((r & VT_VALMASK) == VT_LLOCAL) |
| 847 | + return 1; |
| 848 | + if (r & VT_LVAL) |
| 849 | + return (r & VT_VALMASK) < VT_CONST; |
| 850 | + return 0; |
| 851 | +} |
| 852 | + |
| 853 | +static int arm64_memory_is_pair_suitable(const SValue *sv) |
| 854 | +{ |
| 855 | + int64_t offset; |
| 856 | + |
| 857 | + if (arm64_memory_is_base_only(sv)) |
| 858 | + return 1; |
| 859 | + if ((sv->r & VT_VALMASK) != VT_LOCAL) |
| 860 | + return 0; |
| 861 | + |
| 862 | + offset = (int64_t)sv->c.i; |
| 863 | + return (offset & 7) == 0 && offset >= -512 && offset <= 504; |
| 864 | +} |
| 865 | + |
| 866 | +static int arm64_int_reg_is_allocatable(int reg) |
| 867 | +{ |
| 868 | +#ifdef TCC_TARGET_PE |
| 869 | + return reg >= TREG_X0 && reg <= TREG_X17; |
| 870 | +#else |
| 871 | + return reg >= TREG_X0 && reg <= TREG_X30; |
| 872 | +#endif |
| 873 | +} |
| 874 | + |
| 875 | +static int arm64_memory_needs_address_reg(const SValue *sv) |
| 876 | +{ |
| 877 | + int r; |
| 878 | + |
| 879 | + r = sv->r & ~(VT_BOUNDED | VT_NONCONST); |
| 880 | + if (!(r & VT_LVAL)) |
| 881 | + return 0; |
| 882 | + switch (r & VT_VALMASK) { |
| 883 | + case VT_LOCAL: |
| 884 | + case VT_LLOCAL: |
| 885 | + case VT_CONST: |
| 886 | + return 1; |
| 887 | + } |
| 888 | + return 0; |
| 889 | +} |
| 890 | + |
| 891 | +static int arm64_prepare_memory_operand(ASMOperand *op, uint8_t *regs_allocated) |
| 892 | +{ |
| 893 | + int reg; |
| 894 | + |
| 895 | + if (!arm64_memory_needs_address_reg(op->vt)) |
| 896 | + return 1; |
| 897 | + |
| 898 | + for (reg = 0; reg < 31; reg++) { |
| 899 | + if (arm64_int_reg_is_allocatable(reg) |
| 900 | + && !(regs_allocated[reg] & REG_IN_MASK)) { |
| 901 | + regs_allocated[reg] |= REG_IN_MASK; |
| 902 | + op->reg = reg; |
| 903 | + op->is_memory = 1; |
| 904 | + return 1; |
| 905 | + } |
| 906 | + } |
| 907 | + return 0; |
| 908 | +} |
| 909 | + |
| 910 | +static void arm64_load_memory_operand_base(int reg, SValue *sv) |
| 911 | +{ |
| 912 | + SValue base; |
| 913 | + int rval; |
| 914 | + |
| 915 | + base = *sv; |
| 916 | + base.type.t = VT_PTR; |
| 917 | + rval = base.r & VT_VALMASK; |
| 918 | + if (rval == VT_LLOCAL) { |
| 919 | + base.r = (base.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL; |
| 920 | + } else if (rval == VT_CONST || rval == VT_LOCAL) { |
| 921 | + base.r &= ~VT_LVAL; |
| 922 | + } else { |
| 923 | + tcc_internal_error("unsupported ARM64 memory operand base"); |
| 924 | + } |
| 925 | + load(reg, &base); |
| 926 | +} |
| 927 | + |
| 928 | +static int operand_is_sp(const Operand *op) |
| 929 | +{ |
| 930 | + return op->reg_tok == TOK_ASM_sp; |
| 931 | +} |
| 932 | + |
| 933 | +static int parse_sysreg_name(int t) |
| 934 | +{ |
| 935 | + const char *name; |
| 936 | + |
| 937 | + if (t < TOK_IDENT) |
| 938 | + return -1; |
| 939 | + name = get_tok_str(t, NULL); |
| 940 | + if (!strcmp(name, "FPCR") || !strcmp(name, "fpcr")) |
| 941 | + return 0; |
| 942 | + if (!strcmp(name, "FPSR") || !strcmp(name, "fpsr")) |
| 943 | + return 1; |
| 944 | + return -1; |
| 945 | +} |
| 946 | + |
| 947 | +static void gen_mrs(int rt, int sysreg) |
| 948 | +{ |
| 949 | + uint32_t instr; |
| 950 | + |
| 951 | + switch (sysreg) { |
| 952 | + case 0: /* FPCR */ |
| 953 | + instr = ARM64_MRS_FPCR; |
| 954 | + break; |
| 955 | + case 1: /* FPSR */ |
| 956 | + instr = ARM64_MRS_FPSR; |
| 957 | + break; |
| 958 | + default: |
| 959 | + tcc_error("unsupported system register"); |
| 960 | + return; |
| 961 | + } |
| 962 | + emit_instr32(instr | ARM64_RD(rt)); |
| 963 | +} |
| 964 | + |
| 965 | +static void gen_msr(int rt, int sysreg) |
| 966 | +{ |
| 967 | + uint32_t instr; |
| 968 | + |
| 969 | + switch (sysreg) { |
| 970 | + case 0: /* FPCR */ |
| 971 | + instr = ARM64_MSR_FPCR; |
| 972 | + break; |
| 973 | + case 1: /* FPSR */ |
| 974 | + instr = ARM64_MSR_FPSR; |
| 975 | + break; |
| 976 | + default: |
| 977 | + tcc_error("unsupported system register"); |
| 978 | + return; |
| 979 | + } |
| 980 | + emit_instr32(instr | ARM64_RD(rt)); |
| 981 | +} |
| 982 | + |
| 983 | +/* Generate NOP */ |
| 984 | +static void gen_nop(void) |
| 985 | +{ |
| 986 | + emit_instr32(ARM64_NOP); |
| 987 | +} |
| 988 | + |
| 989 | +/* Generate shift operations (LSL, LSR, ASR, ROR) */ |
| 990 | +static void gen_shift(int rd, int rn, int rm_or_imm, int shift_type, int is_imm, int is_64bit) |
| 991 | +{ |
| 992 | + uint32_t instr; |
| 993 | + int width = is_64bit ? 64 : 32; |
| 994 | + |
| 995 | + if (is_imm) { |
| 996 | + /* Shift by immediate */ |
| 997 | + switch (shift_type) { |
| 998 | + case 0: /* LSL - UBFM alias */ |
| 999 | + if (rm_or_imm < 0 || rm_or_imm >= width) { |
| 1000 | + tcc_error("shift immediate out of range"); |
| 1001 | + return; |
| 1002 | + } |
| 1003 | + instr = is_64bit ? ARM64_LSL_IMM : ARM64_LSR_IMM_32; |
| 1004 | + instr |= ARM64_IMM_R((width - rm_or_imm) & (width - 1)); |
| 1005 | + instr |= ARM64_IMM_S(width - rm_or_imm - 1); |
| 1006 | + break; |
| 1007 | + case 1: /* LSR - UBFM alias: immr = shift, imms = width - 1 */ |
| 1008 | + if (rm_or_imm < 0 || rm_or_imm >= width) { |
| 1009 | + tcc_error("shift immediate out of range"); |
| 1010 | + return; |
| 1011 | + } |
| 1012 | + instr = is_64bit ? ARM64_LSL_IMM : ARM64_LSR_IMM_32; |
| 1013 | + instr |= ARM64_IMM_R(rm_or_imm); |
| 1014 | + instr |= ARM64_IMM_S(width - 1); |
| 1015 | + break; |
| 1016 | + case 2: /* ASR - SBFM alias: immr = shift, imms = width - 1 */ |
| 1017 | + if (rm_or_imm < 0 || rm_or_imm >= width) { |
| 1018 | + tcc_error("shift immediate out of range"); |
| 1019 | + return; |
| 1020 | + } |
| 1021 | + instr = is_64bit ? ARM64_ASR_IMM : (ARM64_ASR_IMM & ~(1U << 31)); |
| 1022 | + instr |= ARM64_IMM_R(rm_or_imm); |
| 1023 | + instr |= ARM64_IMM_S(width - 1); |
| 1024 | + break; |
| 1025 | + case 3: /* ROR - EXTR alias: Rm = source, Rn = source, imms = shift */ |
| 1026 | + if (rm_or_imm < 0 || rm_or_imm >= width) { |
| 1027 | + tcc_error("shift immediate out of range"); |
| 1028 | + return; |
| 1029 | + } |
| 1030 | + instr = is_64bit ? ARM64_EXTR64 : ARM64_EXTR; |
| 1031 | + instr |= ARM64_RM(rn); |
| 1032 | + instr |= ARM64_IMM_S(rm_or_imm); |
| 1033 | + instr |= ARM64_RN(rn); |
| 1034 | + instr |= ARM64_RD(rd); |
| 1035 | + emit_instr32(instr); |
| 1036 | + return; |
| 1037 | + default: |
| 1038 | + tcc_error("unknown shift type"); |
| 1039 | + return; |
| 1040 | + } |
| 1041 | + instr |= ARM64_RN(rn); |
| 1042 | + instr |= ARM64_RD(rd); |
| 1043 | + } else { |
| 1044 | + /* Shift by register */ |
| 1045 | + switch (shift_type) { |
| 1046 | + case 0: /* LSL */ |
| 1047 | + instr = ARM64_LSL_REG; |
| 1048 | + break; |
| 1049 | + case 1: /* LSR */ |
| 1050 | + instr = ARM64_LSR_REG; |
| 1051 | + break; |
| 1052 | + case 2: /* ASR */ |
| 1053 | + instr = ARM64_ASR_REG; |
| 1054 | + break; |
| 1055 | + case 3: /* ROR */ |
| 1056 | + instr = ARM64_ROR_REG; |
| 1057 | + break; |
| 1058 | + default: |
| 1059 | + tcc_error("unknown shift type"); |
| 1060 | + return; |
| 1061 | + } |
| 1062 | + if (is_64bit) |
| 1063 | + instr |= ARM64_SF(1); |
| 1064 | + instr |= ARM64_RM(rm_or_imm); |
| 1065 | + instr |= ARM64_RN(rn); |
| 1066 | + instr |= ARM64_RD(rd); |
| 1067 | + } |
| 1068 | + emit_instr32(instr); |
| 1069 | +} |
| 1070 | + |
| 1071 | +/* Handle shift instructions */ |
| 1072 | +static void asm_shift(TCCState *s1, int token) |
| 1073 | +{ |
| 1074 | + Operand op1, op2, op3; |
| 1075 | + int rd, rn, shift_amount; |
| 1076 | + int shift_type; |
| 1077 | + int is_64bit = 1; |
| 1078 | + |
| 1079 | + switch (token) { |
| 1080 | + case TOK_ASM_lsl: |
| 1081 | + shift_type = 0; |
| 1082 | + break; |
| 1083 | + case TOK_ASM_lsr: |
| 1084 | + shift_type = 1; |
| 1085 | + break; |
| 1086 | + case TOK_ASM_asr: |
| 1087 | + shift_type = 2; |
| 1088 | + break; |
| 1089 | + case TOK_ASM_ror: |
| 1090 | + shift_type = 3; |
| 1091 | + break; |
| 1092 | + default: |
| 1093 | + tcc_error("unknown shift instruction"); |
| 1094 | + return; |
| 1095 | + } |
| 1096 | + |
| 1097 | + parse_operand(s1, &op1); |
| 1098 | + if (tok == ',') next(); |
| 1099 | + parse_operand(s1, &op2); |
| 1100 | + |
| 1101 | + if (!(op1.type & OP_REG)) { |
| 1102 | + tcc_error("expected register in first operand"); |
| 1103 | + return; |
| 1104 | + } |
| 1105 | + if (!(op2.type & OP_REG)) { |
| 1106 | + tcc_error("expected register in second operand"); |
| 1107 | + return; |
| 1108 | + } |
| 1109 | + |
| 1110 | + rd = op1.reg; |
| 1111 | + rn = op2.reg; |
| 1112 | + |
| 1113 | + if (tok == ',') { |
| 1114 | + next(); |
| 1115 | + parse_operand(s1, &op3); |
| 1116 | + is_64bit = (op1.reg_type & REG_X); |
| 1117 | + if (is_64bit != !!(op2.reg_type & REG_X)) { |
| 1118 | + tcc_error("mismatched register widths"); |
| 1119 | + return; |
| 1120 | + } |
| 1121 | + if (op3.type & OP_REG) { |
| 1122 | + if (is_64bit != !!(op3.reg_type & REG_X)) { |
| 1123 | + tcc_error("mismatched register widths"); |
| 1124 | + return; |
| 1125 | + } |
| 1126 | + gen_shift(rd, rn, op3.reg, shift_type, 0, is_64bit); |
| 1127 | + } else if (op3.type & OP_IM) { |
| 1128 | + shift_amount = op3.e.v; |
| 1129 | + gen_shift(rd, rn, shift_amount, shift_type, 1, is_64bit); |
| 1130 | + } else { |
| 1131 | + tcc_error("shift requires immediate or register operand"); |
| 1132 | + } |
| 1133 | + } else { |
| 1134 | + tcc_error("shift requires immediate or register operand"); |
| 1135 | + return; |
| 1136 | + } |
| 1137 | +} |
| 1138 | + |
| 1139 | +/* Generate barrier instructions (ISB, DSB, DMB) */ |
| 1140 | +static void gen_barrier(int barrier_type, int option) |
| 1141 | +{ |
| 1142 | + uint32_t instr; |
| 1143 | + |
| 1144 | + switch (barrier_type) { |
| 1145 | + case 0: /* ISB - Instruction Synchronization Barrier */ |
| 1146 | + instr = ARM64_ISB; |
| 1147 | + break; |
| 1148 | + case 1: /* DSB - Data Synchronization Barrier */ |
| 1149 | + instr = ARM64_DSB; |
| 1150 | + break; |
| 1151 | + case 2: /* DMB - Data Memory Barrier */ |
| 1152 | + instr = ARM64_DMB; |
| 1153 | + break; |
| 1154 | + default: |
| 1155 | + tcc_error("unknown barrier type"); |
| 1156 | + return; |
| 1157 | + } |
| 1158 | + instr |= ARM64_ISB_OPTION(option); |
| 1159 | + emit_instr32(instr); |
| 1160 | +} |
| 1161 | + |
| 1162 | +/* Handle barrier instructions */ |
| 1163 | +static void asm_barrier(TCCState *s1, int token) |
| 1164 | +{ |
| 1165 | + int barrier_type, option; |
| 1166 | + Operand op; |
| 1167 | + |
| 1168 | + switch (token) { |
| 1169 | + case TOK_ASM_isb: |
| 1170 | + barrier_type = 0; |
| 1171 | + break; |
| 1172 | + case TOK_ASM_dsb: |
| 1173 | + barrier_type = 1; |
| 1174 | + break; |
| 1175 | + case TOK_ASM_dmb: |
| 1176 | + barrier_type = 2; |
| 1177 | + break; |
| 1178 | + default: |
| 1179 | + tcc_error("unknown barrier instruction"); |
| 1180 | + return; |
| 1181 | + } |
| 1182 | + |
| 1183 | + /* Default option = sy/full system. */ |
| 1184 | + option = 0xF; |
| 1185 | + |
| 1186 | + /* Check for an optional named or numeric barrier scope. */ |
| 1187 | + if (tok != TOK_LINEFEED) { |
| 1188 | + option = parse_barrier_option_name(tok); |
| 1189 | + if (option >= 0) { |
| 1190 | + next(); |
| 1191 | + } else { |
| 1192 | + parse_operand(s1, &op); |
| 1193 | + if (!(op.type & OP_IM) || op.e.sym) { |
| 1194 | + tcc_error("barrier option must be an immediate or scope name"); |
| 1195 | + return; |
| 1196 | + } |
| 1197 | + if (op.e.v > 0xF) { |
| 1198 | + tcc_error("barrier option out of range"); |
| 1199 | + return; |
| 1200 | + } |
| 1201 | + option = op.e.v; |
| 1202 | + } |
| 1203 | + } |
| 1204 | + |
| 1205 | + gen_barrier(barrier_type, option); |
| 1206 | +} |
| 1207 | + |
| 1208 | +/* Generate immediate move sequence */ |
| 1209 | +static void gen_mov_imm(int rd, uint64_t imm, int is_64bit) |
| 1210 | +{ |
| 1211 | + uint16_t hw; |
| 1212 | + int i, first = 1; |
| 1213 | + |
| 1214 | + for (i = 0; i < (is_64bit ? 4 : 2); i++) { |
| 1215 | + hw = (imm >> (i * 16)) & 0xFFFF; |
| 1216 | + if (hw != 0 || i == 0) { |
| 1217 | + if (first) { |
| 1218 | + /* Pass halfword index (0-3), not bit count */ |
| 1219 | + gen_movz(rd, hw, i, is_64bit); |
| 1220 | + first = 0; |
| 1221 | + } else { |
| 1222 | + gen_movk(rd, hw, i, is_64bit); |
| 1223 | + } |
| 1224 | + } else if (!first) { |
| 1225 | + gen_movk(rd, hw, i, is_64bit); |
| 1226 | + } |
| 1227 | + } |
| 1228 | +} |
| 1229 | + |
| 1230 | +/* Handle mov instruction */ |
| 1231 | +static void asm_mov(TCCState *s1) |
| 1232 | +{ |
| 1233 | + Operand op1, op2; |
| 1234 | + int rd, rn; |
| 1235 | + int is_64bit; |
| 1236 | + |
| 1237 | + parse_operand(s1, &op1); |
| 1238 | + if (tok == ',') next(); |
| 1239 | + parse_operand(s1, &op2); |
| 1240 | + rd = op1.reg; |
| 1241 | + is_64bit = (op1.reg_type & REG_X); |
| 1242 | + |
| 1243 | + if (op2.type & OP_IM) { |
| 1244 | + /* Handle immediate: mov x0, #123 */ |
| 1245 | + if (operand_is_sp(&op1)) { |
| 1246 | + tcc_error("cannot move an immediate into sp"); |
| 1247 | + return; |
| 1248 | + } |
| 1249 | + gen_mov_imm(rd, op2.e.v, is_64bit); |
| 1250 | + } else if (op2.type & OP_REG) { |
| 1251 | + /* Handle register: mov x0, x1 */ |
| 1252 | + rn = op2.reg; |
| 1253 | + if (operand_is_sp(&op1) || operand_is_sp(&op2)) |
| 1254 | + gen_add_imm(rd, rn, 0, 1, 0); |
| 1255 | + else |
| 1256 | + gen_mov_reg(rd, rn, is_64bit); |
| 1257 | + } else { |
| 1258 | + tcc_error("invalid operand for mov"); |
| 1259 | + } |
| 1260 | +} |
| 1261 | + |
| 1262 | +/* Handle data processing instructions */ |
| 1263 | +static void asm_data_proc(TCCState *s1, int token) |
| 1264 | +{ |
| 1265 | + Operand op1, op2, op3; |
| 1266 | + int rd, rn, rm; |
| 1267 | + int is_64bit = 1; |
| 1268 | + uint32_t opcode; |
| 1269 | + |
| 1270 | + switch (token) { |
| 1271 | + case TOK_ASM_add: |
| 1272 | + case TOK_ASM_adds: |
| 1273 | + opcode = token == TOK_ASM_add ? ARM64_ADD_REG : ARM64_ADDS_REG; |
| 1274 | + break; |
| 1275 | + case TOK_ASM_sub: |
| 1276 | + case TOK_ASM_subs: |
| 1277 | + opcode = token == TOK_ASM_sub ? ARM64_SUB_REG : ARM64_SUBS_REG; |
| 1278 | + break; |
| 1279 | + case TOK_ASM_and: |
| 1280 | + case TOK_ASM_ands: |
| 1281 | + opcode = token == TOK_ASM_and ? ARM64_AND_REG : ARM64_ANDS_REG; |
| 1282 | + break; |
| 1283 | + case TOK_ASM_orr: |
| 1284 | + opcode = ARM64_ORR_REG; |
| 1285 | + break; |
| 1286 | + case TOK_ASM_eor: |
| 1287 | + opcode = ARM64_EOR_REG; |
| 1288 | + break; |
| 1289 | + case TOK_ASM_mul: |
| 1290 | + opcode = ARM64_MUL_REG; |
| 1291 | + break; |
| 1292 | + default: |
| 1293 | + tcc_error("unsupported data processing instruction"); |
| 1294 | + return; |
| 1295 | + } |
| 1296 | + |
| 1297 | + parse_operand(s1, &op1); |
| 1298 | + if (tok == ',') next(); |
| 1299 | + parse_operand(s1, &op2); |
| 1300 | + |
| 1301 | + if (!(op1.type & OP_REG)) { |
| 1302 | + tcc_error("expected register in first operand"); |
| 1303 | + return; |
| 1304 | + } |
| 1305 | + if (!(op2.type & OP_REG)) { |
| 1306 | + tcc_error("expected register in second operand"); |
| 1307 | + return; |
| 1308 | + } |
| 1309 | + |
| 1310 | + rd = op1.reg; |
| 1311 | + rn = op2.reg; |
| 1312 | + |
| 1313 | + if (tok == ',') { |
| 1314 | + next(); |
| 1315 | + parse_operand(s1, &op3); |
| 1316 | + is_64bit = (op1.reg_type & REG_X); |
| 1317 | + if (is_64bit != !!(op2.reg_type & REG_X)) { |
| 1318 | + tcc_error("mismatched register widths"); |
| 1319 | + return; |
| 1320 | + } |
| 1321 | + if (op3.type & OP_IM) { |
| 1322 | + if (token == TOK_ASM_add || token == TOK_ASM_adds) |
| 1323 | + gen_add_imm(rd, rn, op3.e.v, is_64bit, |
| 1324 | + token == TOK_ASM_adds); |
| 1325 | + else if (token == TOK_ASM_sub || token == TOK_ASM_subs) |
| 1326 | + gen_sub_imm(rd, rn, op3.e.v, is_64bit, |
| 1327 | + token == TOK_ASM_subs); |
| 1328 | + else if (token == TOK_ASM_and) |
| 1329 | + gen_logical_imm(ARM64_AND_IMM, rd, rn, op3.e.v, is_64bit); |
| 1330 | + else if (token == TOK_ASM_ands) |
| 1331 | + gen_logical_imm(ARM64_ANDS_IMM, rd, rn, op3.e.v, is_64bit); |
| 1332 | + else if (token == TOK_ASM_orr) |
| 1333 | + gen_logical_imm(ARM64_ORR_IMM_BASE, rd, rn, op3.e.v, is_64bit); |
| 1334 | + else if (token == TOK_ASM_eor) |
| 1335 | + gen_logical_imm(ARM64_EOR_IMM, rd, rn, op3.e.v, is_64bit); |
| 1336 | + else |
| 1337 | + tcc_error("immediate operand not valid for this instruction"); |
| 1338 | + } else { |
| 1339 | + if (!(op3.type & OP_REG)) { |
| 1340 | + tcc_error("expected register in third operand"); |
| 1341 | + return; |
| 1342 | + } |
| 1343 | + rm = op3.reg; |
| 1344 | + if (is_64bit != !!(op2.reg_type & REG_X) || is_64bit != !!(op3.reg_type & REG_X)) { |
| 1345 | + tcc_error("mismatched register widths"); |
| 1346 | + return; |
| 1347 | + } |
| 1348 | + gen_dp_reg(opcode, rd, rn, rm, is_64bit); |
| 1349 | + } |
| 1350 | + } else if (op2.type & OP_IM) { |
| 1351 | + tcc_error("missing source register for immediate form"); |
| 1352 | + } else { |
| 1353 | + tcc_error("missing third operand"); |
| 1354 | + } |
| 1355 | +} |
| 1356 | + |
| 1357 | +/* Handle load/store instructions */ |
| 1358 | +static void asm_ldst(TCCState *s1, int token) |
| 1359 | +{ |
| 1360 | + Operand op1, op2; |
| 1361 | + int rt, rn; |
| 1362 | + int32_t offset = 0; |
| 1363 | + int size_log2 = 3; |
| 1364 | + uint32_t base_opcode; |
| 1365 | + |
| 1366 | + parse_operand(s1, &op1); |
| 1367 | + if (tok == ',') next(); |
| 1368 | + parse_operand(s1, &op2); |
| 1369 | + |
| 1370 | + if (!(op1.type & OP_REG)) { |
| 1371 | + tcc_error("expected register in first operand"); |
| 1372 | + return; |
| 1373 | + } |
| 1374 | + if (op2.type != OP_ADDR) { |
| 1375 | + tcc_error("expected address operand in second operand"); |
| 1376 | + return; |
| 1377 | + } |
| 1378 | + |
| 1379 | + rt = op1.reg; |
| 1380 | + rn = op2.reg; |
| 1381 | + offset = op2.e.v; |
| 1382 | + |
| 1383 | + switch (token) { |
| 1384 | + case TOK_ASM_ldr: |
| 1385 | + if (op1.reg_type & REG_X) { |
| 1386 | + base_opcode = ARM64_LDR_X; |
| 1387 | + size_log2 = 3; |
| 1388 | + } else if (op1.reg_type & REG_W) { |
| 1389 | + base_opcode = ARM64_LDR_W; |
| 1390 | + size_log2 = 2; |
| 1391 | + } else if (op1.reg_type & REG_D) { |
| 1392 | + base_opcode = ARM64_LDR_D; |
| 1393 | + size_log2 = 3; |
| 1394 | + } else { |
| 1395 | + tcc_error("ldr requires a w, x, or d register"); |
| 1396 | + return; |
| 1397 | + } |
| 1398 | + break; |
| 1399 | + case TOK_ASM_ldrb: |
| 1400 | + base_opcode = ARM64_LDR_B; |
| 1401 | + size_log2 = 0; |
| 1402 | + break; |
| 1403 | + case TOK_ASM_ldrh: |
| 1404 | + base_opcode = ARM64_LDR_H; |
| 1405 | + size_log2 = 1; |
| 1406 | + break; |
| 1407 | + case TOK_ASM_str: |
| 1408 | + if (op1.reg_type & REG_X) { |
| 1409 | + base_opcode = ARM64_STR_X; |
| 1410 | + size_log2 = 3; |
| 1411 | + } else if (op1.reg_type & REG_W) { |
| 1412 | + base_opcode = ARM64_STR_W; |
| 1413 | + size_log2 = 2; |
| 1414 | + } else if (op1.reg_type & REG_D) { |
| 1415 | + base_opcode = ARM64_STR_D; |
| 1416 | + size_log2 = 3; |
| 1417 | + } else { |
| 1418 | + tcc_error("str requires a w, x, or d register"); |
| 1419 | + return; |
| 1420 | + } |
| 1421 | + break; |
| 1422 | + case TOK_ASM_strb: |
| 1423 | + base_opcode = ARM64_STR_B; |
| 1424 | + size_log2 = 0; |
| 1425 | + break; |
| 1426 | + case TOK_ASM_strh: |
| 1427 | + base_opcode = ARM64_STR_H; |
| 1428 | + size_log2 = 1; |
| 1429 | + break; |
| 1430 | + default: |
| 1431 | + tcc_error("unsupported load/store instruction"); |
| 1432 | + return; |
| 1433 | + } |
| 1434 | + |
| 1435 | + if (op2.addr_mode != ADDR_OFF) |
| 1436 | + tcc_error("only offset addressing is implemented for ldr/str"); |
| 1437 | + gen_ldst_imm(base_opcode, rt, rn, offset, size_log2); |
| 1438 | +} |
| 1439 | + |
| 1440 | +static void asm_ldst_pair(TCCState *s1, int token) |
| 1441 | +{ |
| 1442 | + Operand op1, op2, op3; |
| 1443 | + uint32_t base_opcode; |
| 1444 | + int size_log2 = 3; |
| 1445 | + |
| 1446 | + parse_operand(s1, &op1); |
| 1447 | + if (tok == ',') |
| 1448 | + next(); |
| 1449 | + parse_operand(s1, &op2); |
| 1450 | + if (tok == ',') |
| 1451 | + next(); |
| 1452 | + parse_operand(s1, &op3); |
| 1453 | + |
| 1454 | + if (!(op1.type & OP_REG)) { |
| 1455 | + tcc_error("expected register in first operand"); |
| 1456 | + return; |
| 1457 | + } |
| 1458 | + if (!(op2.type & OP_REG)) { |
| 1459 | + tcc_error("expected register in second operand"); |
| 1460 | + return; |
| 1461 | + } |
| 1462 | + if (!(op3.type & OP_ADDR)) |
| 1463 | + tcc_error("pair load/store requires an address operand"); |
| 1464 | + |
| 1465 | + if ((op1.reg_type & REG_X) && (op2.reg_type & REG_X)) { |
| 1466 | + if (token == TOK_ASM_stp) { |
| 1467 | + base_opcode = op3.addr_mode == ADDR_PRE ? ARM64_STP_X_PRE : |
| 1468 | + op3.addr_mode == ADDR_POST ? ARM64_STP_X_POST : |
| 1469 | + ARM64_STP_X; |
| 1470 | + } else { |
| 1471 | + base_opcode = op3.addr_mode == ADDR_PRE ? ARM64_LDP_X_PRE : |
| 1472 | + op3.addr_mode == ADDR_POST ? ARM64_LDP_X_POST : |
| 1473 | + ARM64_LDP_X; |
| 1474 | + } |
| 1475 | + } else if ((op1.reg_type & REG_D) && (op2.reg_type & REG_D)) { |
| 1476 | + if (token == TOK_ASM_stp) { |
| 1477 | + base_opcode = op3.addr_mode == ADDR_PRE ? ARM64_STP_D_PRE : |
| 1478 | + op3.addr_mode == ADDR_POST ? ARM64_STP_D_POST : |
| 1479 | + ARM64_STP_D; |
| 1480 | + } else { |
| 1481 | + base_opcode = op3.addr_mode == ADDR_PRE ? ARM64_LDP_D_PRE : |
| 1482 | + op3.addr_mode == ADDR_POST ? ARM64_LDP_D_POST : |
| 1483 | + ARM64_LDP_D; |
| 1484 | + } |
| 1485 | + } else { |
| 1486 | + tcc_error("stp/ldp requires matching x or d registers"); |
| 1487 | + return; |
| 1488 | + } |
| 1489 | + |
| 1490 | + gen_ldst_pair(base_opcode, op1.reg, op2.reg, op3.reg, op3.e.v, size_log2); |
| 1491 | +} |
| 1492 | + |
| 1493 | +static void asm_sysreg(TCCState *s1, int token) |
| 1494 | +{ |
| 1495 | + Operand op; |
| 1496 | + int sysreg; |
| 1497 | + |
| 1498 | + if (token == TOK_ASM_mrs) { |
| 1499 | + parse_operand(s1, &op); |
| 1500 | + if (tok == ',') |
| 1501 | + next(); |
| 1502 | + sysreg = parse_sysreg_name(tok); |
| 1503 | + if (sysreg < 0) |
| 1504 | + tcc_error("unsupported system register"); |
| 1505 | + next(); |
| 1506 | + gen_mrs(op.reg, sysreg); |
| 1507 | + return; |
| 1508 | + } |
| 1509 | + |
| 1510 | + sysreg = parse_sysreg_name(tok); |
| 1511 | + if (sysreg < 0) |
| 1512 | + tcc_error("unsupported system register"); |
| 1513 | + next(); |
| 1514 | + if (tok == ',') |
| 1515 | + next(); |
| 1516 | + parse_operand(s1, &op); |
| 1517 | + gen_msr(op.reg, sysreg); |
| 1518 | +} |
| 1519 | + |
| 1520 | +/* Get condition code from branch instruction token */ |
| 1521 | +static int get_branch_condition(int branch_token) |
| 1522 | +{ |
| 1523 | + int cond_token; |
| 1524 | + |
| 1525 | + /* Map branch token to condition token (strip 'b' prefix) */ |
| 1526 | + switch (branch_token) { |
| 1527 | + case TOK_ASM_beq: cond_token = TOK_ASM_eq; break; |
| 1528 | + case TOK_ASM_bne: cond_token = TOK_ASM_ne; break; |
| 1529 | + case TOK_ASM_bcs: |
| 1530 | + case TOK_ASM_bhs: cond_token = TOK_ASM_cs; break; |
| 1531 | + case TOK_ASM_bcc: |
| 1532 | + case TOK_ASM_blo: cond_token = TOK_ASM_cc; break; |
| 1533 | + case TOK_ASM_bmi: cond_token = TOK_ASM_mi; break; |
| 1534 | + case TOK_ASM_bpl: cond_token = TOK_ASM_pl; break; |
| 1535 | + case TOK_ASM_bvs: cond_token = TOK_ASM_vs; break; |
| 1536 | + case TOK_ASM_bvc: cond_token = TOK_ASM_vc; break; |
| 1537 | + case TOK_ASM_bhi: cond_token = TOK_ASM_hi; break; |
| 1538 | + case TOK_ASM_bls: cond_token = TOK_ASM_ls; break; |
| 1539 | + case TOK_ASM_bge: cond_token = TOK_ASM_ge; break; |
| 1540 | + case TOK_ASM_blt: cond_token = TOK_ASM_lt; break; |
| 1541 | + case TOK_ASM_bgt: cond_token = TOK_ASM_gt; break; |
| 1542 | + case TOK_ASM_ble: cond_token = TOK_ASM_le; break; |
| 1543 | + default: return -1; |
| 1544 | + } |
| 1545 | + |
| 1546 | + return parse_condition(cond_token); |
| 1547 | +} |
| 1548 | + |
| 1549 | +/* Handle branch instructions */ |
| 1550 | +static void asm_branch(TCCState *s1, int token) |
| 1551 | +{ |
| 1552 | + Operand op; |
| 1553 | + int cond; |
| 1554 | + Sym *sym; |
| 1555 | + int32_t offset; |
| 1556 | + |
| 1557 | + /* ret can be used without operand */ |
| 1558 | + if (token == TOK_ASM_ret && (tok == TOK_LINEFEED || tok == ';' || tok == TOK_EOF)) { |
| 1559 | + gen_ret(30); /* x30 is the link register */ |
| 1560 | + return; |
| 1561 | + } |
| 1562 | + |
| 1563 | + if (token == TOK_ASM_br || token == TOK_ASM_blr || token == TOK_ASM_ret) |
| 1564 | + parse_operand(s1, &op); |
| 1565 | + else |
| 1566 | + parse_expr_operand(s1, &op); |
| 1567 | + |
| 1568 | + if (op.type & OP_IM) { |
| 1569 | + sym = op.e.sym; |
| 1570 | + if (sym) { |
| 1571 | + /* Symbolic address - emit relocation */ |
| 1572 | + offset = 0; |
| 1573 | + |
| 1574 | + cond = get_branch_condition(token); |
| 1575 | + if (cond >= 0) { |
| 1576 | + /* Conditional branch - use CONDBR19 relocation */ |
| 1577 | + gen_b_cond(cond, 0); |
| 1578 | + greloca(cur_text_section, sym, ind - 4, R_AARCH64_CONDBR19, 0); |
| 1579 | + } else { |
| 1580 | + switch (token) { |
| 1581 | + case TOK_ASM_b: |
| 1582 | + gen_b(0); |
| 1583 | + greloca(cur_text_section, sym, ind - 4, R_AARCH64_JUMP26, 0); |
| 1584 | + break; |
| 1585 | + case TOK_ASM_bl: |
| 1586 | + gen_bl(0); |
| 1587 | + greloca(cur_text_section, sym, ind - 4, R_AARCH64_CALL26, 0); |
| 1588 | + break; |
| 1589 | + default: |
| 1590 | + tcc_error("unsupported branch"); |
| 1591 | + } |
| 1592 | + } |
| 1593 | + } else { |
| 1594 | + offset = (int32_t)op.e.v - ind; |
| 1595 | + |
| 1596 | + cond = get_branch_condition(token); |
| 1597 | + if (cond >= 0) { |
| 1598 | + gen_b_cond(cond, offset); |
| 1599 | + } else { |
| 1600 | + switch (token) { |
| 1601 | + case TOK_ASM_b: |
| 1602 | + gen_b(offset); |
| 1603 | + break; |
| 1604 | + case TOK_ASM_bl: |
| 1605 | + gen_bl(offset); |
| 1606 | + break; |
| 1607 | + default: |
| 1608 | + tcc_error("unsupported branch"); |
| 1609 | + } |
| 1610 | + } |
| 1611 | + } |
| 1612 | + } else if (op.type & OP_REG) { |
| 1613 | + switch (token) { |
| 1614 | + case TOK_ASM_br: |
| 1615 | + gen_br(op.reg); |
| 1616 | + break; |
| 1617 | + case TOK_ASM_blr: |
| 1618 | + gen_blr(op.reg); |
| 1619 | + break; |
| 1620 | + case TOK_ASM_ret: |
| 1621 | + gen_ret(op.reg); |
| 1622 | + break; |
| 1623 | + default: |
| 1624 | + tcc_error("register branch not valid"); |
| 1625 | + } |
| 1626 | + } |
| 1627 | +} |
| 1628 | + |
| 1629 | +/* Handle CBZ/CBNZ */ |
| 1630 | +static void asm_cb(TCCState *s1, int token) |
| 1631 | +{ |
| 1632 | + Operand op1, op2; |
| 1633 | + int rt, is_64bit; |
| 1634 | + int32_t offset; |
| 1635 | + Sym *sym; |
| 1636 | + |
| 1637 | + parse_operand(s1, &op1); |
| 1638 | + if (tok == ',') next(); |
| 1639 | + parse_expr_operand(s1, &op2); |
| 1640 | + |
| 1641 | + rt = op1.reg; |
| 1642 | + is_64bit = (op1.reg_type & REG_X); |
| 1643 | + sym = op2.e.sym; |
| 1644 | + |
| 1645 | + if (sym) { |
| 1646 | + /* Symbolic address - emit relocation */ |
| 1647 | + offset = 0; |
| 1648 | + if (token == TOK_ASM_cbz) { |
| 1649 | + gen_cbz(rt, offset, is_64bit); |
| 1650 | + greloca(cur_text_section, sym, ind - 4, R_AARCH64_CONDBR19, 0); |
| 1651 | + } else { |
| 1652 | + gen_cbnz(rt, offset, is_64bit); |
| 1653 | + greloca(cur_text_section, sym, ind - 4, R_AARCH64_CONDBR19, 0); |
| 1654 | + } |
| 1655 | + } else { |
| 1656 | + offset = (int32_t)op2.e.v - ind; |
| 1657 | + if (token == TOK_ASM_cbz) |
| 1658 | + gen_cbz(rt, offset, is_64bit); |
| 1659 | + else |
| 1660 | + gen_cbnz(rt, offset, is_64bit); |
| 1661 | + } |
| 1662 | +} |
| 1663 | + |
| 1664 | +/* Handle MOVZ/MOVN/MOVK */ |
| 1665 | +static void asm_move_wide(TCCState *s1, int token) |
| 1666 | +{ |
| 1667 | + Operand op1, op2; |
| 1668 | + int rd, is_64bit = 1; |
| 1669 | + uint16_t imm; |
| 1670 | + int shift = 0; |
| 1671 | + |
| 1672 | + parse_operand(s1, &op1); |
| 1673 | + if (tok == ',') next(); |
| 1674 | + parse_operand(s1, &op2); |
| 1675 | + |
| 1676 | + if (!(op1.type & OP_REG)) { |
| 1677 | + tcc_error("expected register in first operand"); |
| 1678 | + return; |
| 1679 | + } |
| 1680 | + if (!(op2.type & OP_IM) || op2.e.sym) { |
| 1681 | + tcc_error("expected immediate in second operand"); |
| 1682 | + return; |
| 1683 | + } |
| 1684 | + |
| 1685 | + rd = op1.reg; |
| 1686 | + is_64bit = (op1.reg_type & REG_X); |
| 1687 | + if ((uint64_t)op2.e.v > 0xFFFF) { |
| 1688 | + tcc_error("move wide immediate out of range"); |
| 1689 | + return; |
| 1690 | + } |
| 1691 | + imm = op2.e.v; |
| 1692 | + |
| 1693 | + if (tok == ',') { |
| 1694 | + next(); |
| 1695 | + if (tok != TOK_ASM_lsl) { |
| 1696 | + tcc_error("move wide shift must use lsl"); |
| 1697 | + return; |
| 1698 | + } |
| 1699 | + next(); |
| 1700 | + if (tok == '#') next(); |
| 1701 | + asm_expr(s1, &op2.e); |
| 1702 | + if (op2.e.sym || !is_valid_movw_shift((int)op2.e.v, is_64bit)) { |
| 1703 | + tcc_error("move wide shift out of range"); |
| 1704 | + return; |
| 1705 | + } |
| 1706 | + shift = (int)op2.e.v / 16; |
| 1707 | + } |
| 1708 | + |
| 1709 | + switch (token) { |
| 1710 | + case TOK_ASM_movz: |
| 1711 | + gen_movz(rd, imm, shift, is_64bit); |
| 1712 | + break; |
| 1713 | + case TOK_ASM_movn: |
| 1714 | + gen_movn(rd, imm, shift, is_64bit); |
| 1715 | + break; |
| 1716 | + case TOK_ASM_movk: |
| 1717 | + gen_movk(rd, imm, shift, is_64bit); |
| 1718 | + break; |
| 1719 | + default: |
| 1720 | + tcc_error("unknown move wide instruction"); |
| 1721 | + } |
| 1722 | +} |
| 1723 | + |
| 1724 | +/* Main assembler opcode dispatcher */ |
| 57 | 1725 | ST_FUNC void asm_opcode(TCCState *s1, int opcode) |
| 58 | 1726 | { |
| 59 | | − asm_error(); |
| 1727 | + switch (opcode) { |
| 1728 | + case TOK_ASM_add: |
| 1729 | + case TOK_ASM_adds: |
| 1730 | + case TOK_ASM_sub: |
| 1731 | + case TOK_ASM_subs: |
| 1732 | + case TOK_ASM_and: |
| 1733 | + case TOK_ASM_ands: |
| 1734 | + case TOK_ASM_orr: |
| 1735 | + case TOK_ASM_eor: |
| 1736 | + case TOK_ASM_mul: |
| 1737 | + asm_data_proc(s1, opcode); |
| 1738 | + break; |
| 1739 | + |
| 1740 | + case TOK_ASM_mov: |
| 1741 | + /* mov is handled separately - it's ORR with zero register */ |
| 1742 | + asm_mov(s1); |
| 1743 | + break; |
| 1744 | + |
| 1745 | + case TOK_ASM_lsl: |
| 1746 | + case TOK_ASM_lsr: |
| 1747 | + case TOK_ASM_asr: |
| 1748 | + case TOK_ASM_ror: |
| 1749 | + asm_shift(s1, opcode); |
| 1750 | + break; |
| 1751 | + |
| 1752 | + case TOK_ASM_ldr: |
| 1753 | + case TOK_ASM_ldrb: |
| 1754 | + case TOK_ASM_ldrh: |
| 1755 | + case TOK_ASM_str: |
| 1756 | + case TOK_ASM_strb: |
| 1757 | + case TOK_ASM_strh: |
| 1758 | + asm_ldst(s1, opcode); |
| 1759 | + break; |
| 1760 | + |
| 1761 | + case TOK_ASM_ldp: |
| 1762 | + case TOK_ASM_stp: |
| 1763 | + asm_ldst_pair(s1, opcode); |
| 1764 | + break; |
| 1765 | + |
| 1766 | + case TOK_ASM_b: |
| 1767 | + case TOK_ASM_bl: |
| 1768 | + case TOK_ASM_br: |
| 1769 | + case TOK_ASM_blr: |
| 1770 | + case TOK_ASM_ret: |
| 1771 | + case TOK_ASM_beq: |
| 1772 | + case TOK_ASM_bne: |
| 1773 | + case TOK_ASM_bcs: |
| 1774 | + case TOK_ASM_bhs: |
| 1775 | + case TOK_ASM_bcc: |
| 1776 | + case TOK_ASM_blo: |
| 1777 | + case TOK_ASM_bmi: |
| 1778 | + case TOK_ASM_bpl: |
| 1779 | + case TOK_ASM_bvs: |
| 1780 | + case TOK_ASM_bvc: |
| 1781 | + case TOK_ASM_bhi: |
| 1782 | + case TOK_ASM_bls: |
| 1783 | + case TOK_ASM_bge: |
| 1784 | + case TOK_ASM_blt: |
| 1785 | + case TOK_ASM_bgt: |
| 1786 | + case TOK_ASM_ble: |
| 1787 | + asm_branch(s1, opcode); |
| 1788 | + break; |
| 1789 | + |
| 1790 | + case TOK_ASM_cbz: |
| 1791 | + case TOK_ASM_cbnz: |
| 1792 | + asm_cb(s1, opcode); |
| 1793 | + break; |
| 1794 | + |
| 1795 | + case TOK_ASM_movz: |
| 1796 | + case TOK_ASM_movn: |
| 1797 | + case TOK_ASM_movk: |
| 1798 | + asm_move_wide(s1, opcode); |
| 1799 | + break; |
| 1800 | + |
| 1801 | + case TOK_ASM_mrs: |
| 1802 | + case TOK_ASM_msr: |
| 1803 | + asm_sysreg(s1, opcode); |
| 1804 | + break; |
| 1805 | + |
| 1806 | + case TOK_ASM_isb: |
| 1807 | + case TOK_ASM_dsb: |
| 1808 | + case TOK_ASM_dmb: |
| 1809 | + asm_barrier(s1, opcode); |
| 1810 | + break; |
| 1811 | + |
| 1812 | + case TOK_ASM_nop: |
| 1813 | + gen_nop(); |
| 1814 | + break; |
| 1815 | + |
| 1816 | + default: |
| 1817 | + tcc_error("ARM64 instruction '%s' not implemented", |
| 1818 | + get_tok_str(opcode, NULL)); |
| 1819 | + break; |
| 1820 | + } |
| 60 | 1821 | } |
| 61 | 1822 | |
| 1823 | +/* Substitute assembler operand */ |
| 62 | 1824 | ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier) |
| 63 | 1825 | { |
| 64 | | − asm_error(); |
| 1826 | + int r, reg, size, fp_reg, align; |
| 1827 | + int64_t val; |
| 1828 | + uint64_t uval; |
| 1829 | + |
| 1830 | + r = sv->r; |
| 1831 | + if ((r & VT_VALMASK) == VT_CONST) { |
| 1832 | + if ((modifier == 'w' || modifier == 'x') && !(r & VT_LVAL) |
| 1833 | + && !(r & VT_SYM) && sv->c.i == 0) { |
| 1834 | + cstr_cat(add_str, modifier == 'w' ? "wzr" : "xzr", -1); |
| 1835 | + return; |
| 1836 | + } |
| 1837 | + if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n' && |
| 1838 | + modifier != 'P') |
| 1839 | + cstr_ccat(add_str, '#'); |
| 1840 | + if (r & VT_SYM) { |
| 1841 | + const char *name = get_tok_str(sv->sym->v, NULL); |
| 1842 | + if (sv->sym->v >= SYM_FIRST_ANOM) |
| 1843 | + get_asm_sym(tok_alloc(name, strlen(name))->tok, sv->sym); |
| 1844 | + if (tcc_state->leading_underscore) |
| 1845 | + cstr_ccat(add_str, '_'); |
| 1846 | + cstr_cat(add_str, name, -1); |
| 1847 | + if ((uint32_t) sv->c.i == 0) |
| 1848 | + goto no_offset; |
| 1849 | + cstr_ccat(add_str, '+'); |
| 1850 | + } |
| 1851 | + uval = sv->c.i; |
| 1852 | + if (modifier == 'n') { |
| 1853 | + val = -(int64_t)uval; |
| 1854 | + cstr_printf(add_str, "%lld", (long long)val); |
| 1855 | + } else if (uval > 0x7fffffffffffffffULL) { |
| 1856 | + cstr_printf(add_str, "0x%llx", (unsigned long long)uval); |
| 1857 | + } else { |
| 1858 | + val = (int64_t)uval; |
| 1859 | + cstr_printf(add_str, "%lld", (long long)val); |
| 1860 | + } |
| 1861 | + no_offset:; |
| 1862 | + } else if ((r & VT_VALMASK) == VT_LOCAL) { |
| 1863 | + cstr_printf(add_str, "[x29,#%d]", (int) sv->c.i); |
| 1864 | + } else if (r & VT_LVAL) { |
| 1865 | + reg = r & VT_VALMASK; |
| 1866 | + if (reg >= VT_CONST) |
| 1867 | + tcc_internal_error(""); |
| 1868 | + cstr_printf(add_str, "[x%d]", reg); |
| 1869 | + } else { |
| 1870 | + /* register case */ |
| 1871 | + reg = r & VT_VALMASK; |
| 1872 | + if (reg >= VT_CONST) |
| 1873 | + tcc_internal_error(""); |
| 1874 | + |
| 1875 | + if (ARM64_FREG_BASE <= reg && reg <= ARM64_FREG_LAST) { |
| 1876 | + fp_reg = reg - ARM64_FREG_BASE; |
| 1877 | + size = type_size(&sv->type, &align); |
| 1878 | + |
| 1879 | + if (modifier == 0) |
| 1880 | + modifier = size <= 4 ? 's' |
| 1881 | + : size == 8 ? 'd' |
| 1882 | + : 'q'; |
| 1883 | + |
| 1884 | + switch (modifier) { |
| 1885 | + case 'b': |
| 1886 | + case 'h': |
| 1887 | + case 's': |
| 1888 | + case 'd': |
| 1889 | + case 'q': |
| 1890 | + case 'Z': |
| 1891 | + cstr_printf(add_str, "%c%d", modifier == 'Z' ? 'z' : modifier, |
| 1892 | + fp_reg); |
| 1893 | + return; |
| 1894 | + default: |
| 1895 | + tcc_error("invalid operand modifier for SIMD/FP register"); |
| 1896 | + return; |
| 1897 | + } |
| 1898 | + } |
| 1899 | + |
| 1900 | + /* choose register operand size */ |
| 1901 | + if ((sv->type.t & VT_BTYPE) == VT_BYTE || |
| 1902 | + (sv->type.t & VT_BTYPE) == VT_BOOL) |
| 1903 | + size = 1; |
| 1904 | + else if ((sv->type.t & VT_BTYPE) == VT_SHORT) |
| 1905 | + size = 2; |
| 1906 | + else if ((sv->type.t & VT_BTYPE) == VT_LLONG || |
| 1907 | + (sv->type.t & VT_BTYPE) == VT_PTR) |
| 1908 | + size = 8; |
| 1909 | + else |
| 1910 | + size = 4; |
| 1911 | + |
| 1912 | + if (modifier == 'x') { |
| 1913 | + size = 8; |
| 1914 | + } else if (modifier == 'w' || modifier == 'k') { |
| 1915 | + size = 4; |
| 1916 | + } else if (modifier == 'b') { |
| 1917 | + size = 1; |
| 1918 | + } else if (modifier == 'h') { |
| 1919 | + size = 2; |
| 1920 | + } else if (modifier == 'q') { |
| 1921 | + size = 8; |
| 1922 | + } |
| 1923 | + |
| 1924 | + if (size <= 4) { |
| 1925 | + cstr_printf(add_str, "w%d", reg); |
| 1926 | + } else { |
| 1927 | + cstr_printf(add_str, "x%d", reg); |
| 1928 | + } |
| 1929 | + } |
| 65 | 1930 | } |
| 66 | 1931 | |
| 67 | | −/* generate prolog and epilog code for asm statement */ |
| 68 | 1932 | ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, |
| 69 | | − int nb_outputs, int is_output, |
| 70 | | − uint8_t *clobber_regs, |
| 71 | | − int out_reg) |
| 1933 | + int nb_outputs, int is_output, |
| 1934 | + uint8_t *clobber_regs, |
| 1935 | + int out_reg) |
| 72 | 1936 | { |
| 1937 | + uint8_t regs_allocated[NB_ASM_REGS]; |
| 1938 | + ASMOperand *op; |
| 1939 | + int i, reg, saved_count, stack_size, stack_off; |
| 1940 | + int saved_regs[12]; |
| 1941 | + static const uint8_t reg_saved[] = { |
| 1942 | + 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, |
| 1943 | + 29, 30 |
| 1944 | + }; |
| 1945 | + |
| 1946 | + memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated)); |
| 1947 | + for (i = 0; i < nb_operands; i++) { |
| 1948 | + op = &operands[i]; |
| 1949 | + if (op->reg >= 0) |
| 1950 | + regs_allocated[op->reg] = 1; |
| 1951 | + } |
| 1952 | + |
| 1953 | + saved_count = 0; |
| 1954 | + for (i = 0; i < sizeof(reg_saved) / sizeof(reg_saved[0]); i++) { |
| 1955 | + reg = reg_saved[i]; |
| 1956 | + if (regs_allocated[reg]) |
| 1957 | + saved_regs[saved_count++] = reg; |
| 1958 | + } |
| 1959 | + stack_size = ((saved_count + 1) / 2) * 16; |
| 1960 | + |
| 1961 | + if (!is_output) { |
| 1962 | + if (saved_count > 0) { |
| 1963 | + gen_sub_imm(31, 31, stack_size, 1, 0); |
| 1964 | + |
| 1965 | + for (i = stack_off = 0; i < saved_count; ) { |
| 1966 | + if (i + 1 < saved_count) { |
| 1967 | + gen_ldst_pair(ARM64_STP_X, saved_regs[i], saved_regs[i + 1], |
| 1968 | + TREG_SP, stack_off, 3); |
| 1969 | + stack_off += 16; |
| 1970 | + i += 2; |
| 1971 | + } else { |
| 1972 | + gen_ldst_imm(ARM64_STR_X, saved_regs[i], TREG_SP, |
| 1973 | + stack_off, 3); |
| 1974 | + i++; |
| 1975 | + } |
| 1976 | + } |
| 1977 | + } |
| 1978 | + |
| 1979 | + for (i = 0; i < nb_operands; i++) { |
| 1980 | + op = &operands[i]; |
| 1981 | + if (op->reg >= 0) { |
| 1982 | + if (op->is_memory) { |
| 1983 | + arm64_load_memory_operand_base(op->reg, op->vt); |
| 1984 | + } else if (i >= nb_outputs || op->is_rw) { |
| 1985 | + load(op->reg, op->vt); |
| 1986 | + } |
| 1987 | + } |
| 1988 | + } |
| 1989 | + } else { |
| 1990 | + for (i = 0; i < nb_outputs; i++) { |
| 1991 | + op = &operands[i]; |
| 1992 | + if (op->reg >= 0) { |
| 1993 | + if (op->is_memory) |
| 1994 | + continue; |
| 1995 | + if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) { |
| 1996 | + if (!op->is_memory) { |
| 1997 | + SValue sv; |
| 1998 | + sv = *op->vt; |
| 1999 | + sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL; |
| 2000 | + sv.type.t = VT_PTR; |
| 2001 | + load(out_reg, &sv); |
| 2002 | + |
| 2003 | + sv = *op->vt; |
| 2004 | + sv.r = (sv.r & ~VT_VALMASK) | out_reg; |
| 2005 | + store(op->reg, &sv); |
| 2006 | + } |
| 2007 | + } else { |
| 2008 | + store(op->reg, op->vt); |
| 2009 | + } |
| 2010 | + } |
| 2011 | + } |
| 2012 | + |
| 2013 | + if (saved_count > 0) { |
| 2014 | + for (i = stack_off = 0; i < saved_count; ) { |
| 2015 | + if (i + 1 < saved_count) { |
| 2016 | + gen_ldst_pair(ARM64_LDP_X, saved_regs[i], saved_regs[i + 1], |
| 2017 | + TREG_SP, stack_off, 3); |
| 2018 | + stack_off += 16; |
| 2019 | + i += 2; |
| 2020 | + } else { |
| 2021 | + gen_ldst_imm(ARM64_LDR_X, saved_regs[i], TREG_SP, |
| 2022 | + stack_off, 3); |
| 2023 | + i++; |
| 2024 | + } |
| 2025 | + } |
| 2026 | + gen_add_imm(31, 31, stack_size, 1, 0); |
| 2027 | + } |
| 2028 | + } |
| 73 | 2029 | } |
| 74 | 2030 | |
| 75 | 2031 | ST_FUNC void asm_compute_constraints(ASMOperand *operands, |
| @@ -77,17 +2033,247 @@ ST_FUNC void asm_compute_constraints(ASMOperand *operands, · 1 unmodified line |
| 77 | 2033 | const uint8_t *clobber_regs, |
| 78 | 2034 | int *pout_reg) |
| 79 | 2035 | { |
| 2036 | + ASMOperand *op; |
| 2037 | + int sorted_op[MAX_ASM_OPERANDS]; |
| 2038 | + int i, j, k, p1, p2, tmp, reg, c, reg_mask; |
| 2039 | + const char *str; |
| 2040 | + uint8_t regs_allocated[NB_ASM_REGS]; |
| 2041 | + |
| 2042 | + for (i = 0; i < nb_operands; i++) { |
| 2043 | + op = &operands[i]; |
| 2044 | + op->input_index = -1; |
| 2045 | + op->ref_index = -1; |
| 2046 | + op->reg = -1; |
| 2047 | + op->is_memory = 0; |
| 2048 | + op->is_rw = 0; |
| 2049 | + op->is_llong = 0; |
| 2050 | + } |
| 2051 | + |
| 2052 | + for (i = 0; i < nb_operands; i++) { |
| 2053 | + op = &operands[i]; |
| 2054 | + str = op->constraint; |
| 2055 | + str = skip_constraint_modifiers(str); |
| 2056 | + if (isnum(*str) || *str == '[') { |
| 2057 | + k = find_constraint(operands, nb_operands, str, NULL); |
| 2058 | + if ((unsigned)k >= i || i < nb_outputs) |
| 2059 | + tcc_error("invalid reference in constraint %d ('%s')", i, str); |
| 2060 | + op->ref_index = k; |
| 2061 | + if (operands[k].input_index >= 0) |
| 2062 | + tcc_error("cannot reference twice the same operand"); |
| 2063 | + operands[k].input_index = i; |
| 2064 | + op->priority = 5; |
| 2065 | + } else if ((op->vt->r & VT_VALMASK) == VT_LOCAL |
| 2066 | + && op->vt->sym |
| 2067 | + && (reg = op->vt->sym->r & VT_VALMASK) < VT_CONST) { |
| 2068 | + op->priority = 1; |
| 2069 | + op->reg = reg; |
| 2070 | + } else { |
| 2071 | + op->priority = constraint_priority(str); |
| 2072 | + } |
| 2073 | + } |
| 2074 | + |
| 2075 | + for (i = 0; i < nb_operands; i++) |
| 2076 | + sorted_op[i] = i; |
| 2077 | + for (i = 0; i < nb_operands - 1; i++) { |
| 2078 | + for (j = i + 1; j < nb_operands; j++) { |
| 2079 | + p1 = operands[sorted_op[i]].priority; |
| 2080 | + p2 = operands[sorted_op[j]].priority; |
| 2081 | + if (p2 < p1) { |
| 2082 | + tmp = sorted_op[i]; |
| 2083 | + sorted_op[i] = sorted_op[j]; |
| 2084 | + sorted_op[j] = tmp; |
| 2085 | + } |
| 2086 | + } |
| 2087 | + } |
| 2088 | + |
| 2089 | + for (i = 0; i < NB_ASM_REGS; i++) { |
| 2090 | + if (clobber_regs[i]) |
| 2091 | + regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK; |
| 2092 | + else |
| 2093 | + regs_allocated[i] = 0; |
| 2094 | + } |
| 2095 | + |
| 2096 | + for (i = 0; i < nb_operands; i++) { |
| 2097 | + j = sorted_op[i]; |
| 2098 | + op = &operands[j]; |
| 2099 | + str = op->constraint; |
| 2100 | + if (op->ref_index >= 0) |
| 2101 | + continue; |
| 2102 | + if (op->input_index >= 0) { |
| 2103 | + reg_mask = REG_IN_MASK | REG_OUT_MASK; |
| 2104 | + } else if (j < nb_outputs) { |
| 2105 | + reg_mask = REG_OUT_MASK; |
| 2106 | + } else { |
| 2107 | + reg_mask = REG_IN_MASK; |
| 2108 | + } |
| 2109 | + if (op->reg >= 0) { |
| 2110 | + if (is_reg_allocated(op->reg)) |
| 2111 | + tcc_error("asm regvar requests register that's taken already"); |
| 2112 | + reg = op->reg; |
| 2113 | + goto reg_found; |
| 2114 | + } |
| 2115 | + try_next: |
| 2116 | + c = *str++; |
| 2117 | + switch (c) { |
| 2118 | + case '=': |
| 2119 | + goto try_next; |
| 2120 | + case '+': |
| 2121 | + op->is_rw = 1; |
| 2122 | + case '&': |
| 2123 | + if (j >= nb_outputs) |
| 2124 | + tcc_error("'%c' modifier can only be applied to outputs", c); |
| 2125 | + reg_mask = REG_IN_MASK | REG_OUT_MASK; |
| 2126 | + goto try_next; |
| 2127 | + case 'r': |
| 2128 | + for (reg = 0; reg < 31; reg++) { |
| 2129 | + if (arm64_int_reg_is_allocatable(reg) |
| 2130 | + && !is_reg_allocated(reg)) |
| 2131 | + goto reg_found; |
| 2132 | + } |
| 2133 | + goto try_next; |
| 2134 | + case 'w': |
| 2135 | + case 'f': |
| 2136 | + for (reg = ARM64_FREG_BASE; reg <= ARM64_FREG_LAST; reg++) { |
| 2137 | + if (!is_reg_allocated(reg)) |
| 2138 | + goto reg_found; |
| 2139 | + } |
| 2140 | + goto try_next; |
| 2141 | + case 'x': |
| 2142 | + case 'y': |
| 2143 | + for (reg = ARM64_FREG_BASE; reg <= ARM64_FREG_LAST; reg++) { |
| 2144 | + if (!is_reg_allocated(reg)) |
| 2145 | + goto reg_found; |
| 2146 | + } |
| 2147 | + goto try_next; |
| 2148 | + case 'm': |
| 2149 | + case 'g': |
| 2150 | + if (j < nb_outputs || c == 'm') { |
| 2151 | + if (!arm64_prepare_memory_operand(op, regs_allocated)) |
| 2152 | + goto try_next; |
| 2153 | + } |
| 2154 | + break; |
| 2155 | + case 'Q': |
| 2156 | + if (!arm64_memory_is_base_only(op->vt)) |
| 2157 | + goto try_next; |
| 2158 | + if (!arm64_prepare_memory_operand(op, regs_allocated)) |
| 2159 | + goto try_next; |
| 2160 | + break; |
| 2161 | + case 'S': |
| 2162 | + if ((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) != (VT_CONST | VT_SYM)) |
| 2163 | + goto try_next; |
| 2164 | + break; |
| 2165 | + case 'U': |
| 2166 | + if (str[0] != 'm' || str[1] != 'p') |
| 2167 | + goto try_next; |
| 2168 | + str += 2; |
| 2169 | + if (!arm64_memory_is_pair_suitable(op->vt)) |
| 2170 | + goto try_next; |
| 2171 | + if (!arm64_prepare_memory_operand(op, regs_allocated)) |
| 2172 | + goto try_next; |
| 2173 | + break; |
| 2174 | + case 'i': |
| 2175 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST)) |
| 2176 | + goto try_next; |
| 2177 | + break; |
| 2178 | + case 'I': |
| 2179 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2180 | + goto try_next; |
| 2181 | + if (!is_valid_add_imm(op->vt->c.i)) |
| 2182 | + goto try_next; |
| 2183 | + break; |
| 2184 | + case 'J': |
| 2185 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2186 | + goto try_next; |
| 2187 | + if (!is_valid_add_imm(-op->vt->c.i)) |
| 2188 | + goto try_next; |
| 2189 | + break; |
| 2190 | + case 'K': |
| 2191 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2192 | + goto try_next; |
| 2193 | + if (!is_valid_logical_imm(op->vt->c.i, 32)) |
| 2194 | + goto try_next; |
| 2195 | + break; |
| 2196 | + case 'L': |
| 2197 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2198 | + goto try_next; |
| 2199 | + if (!is_valid_logical_imm(op->vt->c.i, 64)) |
| 2200 | + goto try_next; |
| 2201 | + break; |
| 2202 | + case 'M': |
| 2203 | + case 'N': |
| 2204 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2205 | + goto try_next; |
| 2206 | + if (!is_valid_movw_imm(op->vt->c.i)) |
| 2207 | + goto try_next; |
| 2208 | + break; |
| 2209 | + case 'Z': |
| 2210 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST)) |
| 2211 | + goto try_next; |
| 2212 | + if (op->vt->c.i != 0) |
| 2213 | + goto try_next; |
| 2214 | + break; |
| 2215 | + case 'n': |
| 2216 | + if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST)) |
| 2217 | + goto try_next; |
| 2218 | + break; |
| 2219 | + default: |
| 2220 | + tcc_error("asm constraint %d ('%s') could not be satisfied", |
| 2221 | + j, op->constraint); |
| 2222 | + break; |
| 2223 | + } |
| 2224 | + if (op->input_index >= 0) { |
| 2225 | + operands[op->input_index].reg = op->reg; |
| 2226 | + operands[op->input_index].is_llong = op->is_llong; |
| 2227 | + } |
| 2228 | + continue; |
| 2229 | + reg_found: |
| 2230 | + op->is_llong = 0; |
| 2231 | + op->reg = reg; |
| 2232 | + regs_allocated[reg] |= reg_mask; |
| 2233 | + if (op->input_index >= 0) { |
| 2234 | + operands[op->input_index].reg = op->reg; |
| 2235 | + operands[op->input_index].is_llong = op->is_llong; |
| 2236 | + } |
| 2237 | + } |
| 2238 | + |
| 2239 | + *pout_reg = -1; |
| 2240 | + for (i = 0; i < nb_operands; i++) { |
| 2241 | + op = &operands[i]; |
| 2242 | + if (op->reg >= 0 && |
| 2243 | + (op->vt->r & VT_VALMASK) == VT_LLOCAL && |
| 2244 | + !op->is_memory) { |
| 2245 | + for (reg = 0; reg < 31; reg++) { |
| 2246 | + if (!(regs_allocated[reg] & REG_OUT_MASK)) |
| 2247 | + goto reg_found2; |
| 2248 | + } |
| 2249 | + tcc_error("could not find free output register for reloading"); |
| 2250 | + reg_found2: |
| 2251 | + *pout_reg = reg; |
| 2252 | + break; |
| 2253 | + } |
| 2254 | + } |
| 80 | 2255 | } |
| 81 | 2256 | |
| 2257 | +/* Handle clobber list */ |
| 82 | 2258 | ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str) |
| 83 | 2259 | { |
| 84 | | − asm_error(); |
| 2260 | + int reg; |
| 2261 | + |
| 2262 | + if (!strcmp(str, "memory") || |
| 2263 | + !strcmp(str, "cc") || |
| 2264 | + !strcmp(str, "flags")) |
| 2265 | + return; |
| 2266 | + |
| 2267 | + reg = arm64_parse_regvar(tok_alloc_const(str)); |
| 2268 | + if (reg == -1) |
| 2269 | + tcc_error("invalid clobber register '%s'", str); |
| 2270 | + clobber_regs[reg] = 1; |
| 85 | 2271 | } |
| 86 | 2272 | |
| 87 | | −ST_FUNC int asm_parse_regvar (int t) |
| 2273 | +/* Parse register variable - this is the ST_FUNC that tcc.h expects */ |
| 2274 | +ST_FUNC int asm_parse_regvar(int t) |
| 88 | 2275 | { |
| 89 | | − asm_error(); |
| 90 | | − return -1; |
| 2276 | + return arm64_parse_regvar(t); |
| 91 | 2277 | } |
| 92 | 2278 | |
| 93 | 2279 | /*************************************************************/ |