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riscv64: fcvt.d.s doesn't need a rounding mode

it doesn't round so the RM field can be zero. According to some sourcs it should be set to zero by software in these cases, and the binutils disassembler doesn't like us setting it to 7. This shouldn't matter in practice, but who knows.

Michael Matz committed 6 years ago

Commit fb1fb821 parent 2f943901 file · +2 −2Browse files

Unified · Split

riscv64-gen.c+2−2
@@ -1176,9 +1176,9 @@ ST_FUNC void gen_cvt_ftof(int dt) · 1175 unmodified lines
11761176 rs = gv(RC_FLOAT);
11771177 rd = get_reg(RC_FLOAT);
11781178 if (dt == VT_DOUBLE)
1179− EI(0x53, 7, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (dyn rm)
1179+ EI(0x53, 0, freg(rd), freg(rs), 0x21 << 5); // fcvt.d.s RD, RS (no rm)
11801180 else
1181− EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS
1181+ EI(0x53, 7, freg(rd), freg(rs), (0x20 << 5) | 1); // fcvt.s.d RD, RS (dyn rm)
11821182 vtop->r = rd;
11831183 }
11841184 }

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