// SPDX-License-Identifier: GPL-2.0-or-later/* * Intel CPU Microcode Update Driver for Linux * * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> * 2006 Shaohua Li <shaohua.li@intel.com> * * Intel CPU microcode early update for Linux * * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> * H Peter Anvin" <hpa@zytor.com> */#define pr_fmt(fmt) "microcode: " fmt#include <linux/earlycpio.h>#include <linux/firmware.h>#include <linux/pci_ids.h>#include <linux/uaccess.h>#include <linux/initrd.h>#include <linux/kernel.h>#include <linux/delay.h>#include <linux/slab.h>#include <linux/cpu.h>#include <linux/uio.h>#include <linux/io.h>#include <linux/mm.h> #include <asm/cpu_device_id.h>#include <asm/cpuid/api.h>#include <asm/processor.h>#include <asm/tlbflush.h>#include <asm/setup.h>#include <asm/msr.h> #include "internal.h" static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; #define UCODE_BSP_LOADED ((struct microcode_intel *)0x1UL) /* Defines for the microcode staging mailbox interface */#define MBOX_REG_NUM 4#define MBOX_REG_SIZE sizeof(u32) #define MBOX_CONTROL_OFFSET 0x0#define MBOX_STATUS_OFFSET 0x4#define MBOX_WRDATA_OFFSET 0x8#define MBOX_RDDATA_OFFSET 0xc #define MASK_MBOX_CTRL_ABORT BIT(0)#define MASK_MBOX_CTRL_GO BIT(31) #define MASK_MBOX_STATUS_ERROR BIT(2)#define MASK_MBOX_STATUS_READY BIT(31) #define MASK_MBOX_RESP_SUCCESS BIT(0)#define MASK_MBOX_RESP_PROGRESS BIT(1)#define MASK_MBOX_RESP_ERROR BIT(2) #define MBOX_CMD_LOAD 0x3#define MBOX_OBJ_STAGING 0xb#define MBOX_HEADER(size) ((PCI_VENDOR_ID_INTEL) | \ (MBOX_OBJ_STAGING << 16) | \ ((u64)((size) / sizeof(u32)) << 32)) /* The size of each mailbox header */#define MBOX_HEADER_SIZE sizeof(u64)/* The size of staging hardware response */#define MBOX_RESPONSE_SIZE sizeof(u64) #define MBOX_XACTION_TIMEOUT_MS (10 * MSEC_PER_SEC) /* Current microcode patch used in early patching on the APs. */static struct microcode_intel *ucode_patch_va __read_mostly;static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */static unsigned int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */struct extended_signature { unsigned int sig; unsigned int pf; unsigned int cksum;}; struct extended_sigtable { unsigned int count; unsigned int cksum; unsigned int reserved[3]; struct extended_signature sigs[];}; /** * struct staging_state - Track the current staging process state * * @mmio_base: MMIO base address for staging * @ucode_len: Total size of the microcode image * @chunk_size: Size of each data piece * @bytes_sent: Total bytes transmitted so far * @offset: Current offset in the microcode image */struct staging_state { void __iomem *mmio_base; unsigned int ucode_len; unsigned int chunk_size; unsigned int bytes_sent; unsigned int offset;}; #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) static inline unsigned int get_totalsize(struct microcode_header_intel *hdr){ return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE;} static inline unsigned int exttable_size(struct extended_sigtable *et){ return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE;} /* * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 * structures are populated. */static u32 intel_cpuid_vfm(void){ u32 eax = cpuid_eax(1); u32 fam = x86_family(eax); u32 model = x86_model(eax); return IFM(fam, model);} u32 intel_get_platform_id(void){ unsigned int val[2]; if (x86_hypervisor_present) return 0; /* * This can be called early. Use CPUID directly instead of * relying on cpuinfo_x86 which may not be fully initialized. * The PII does not have MSR_IA32_PLATFORM_ID. Everything * before _it_ has no microcode (for Linux at least). */ if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) return 0; /* get processor flags from MSR 0x17 */ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); return (val[1] >> 18) & 7;} void intel_collect_cpu_info(struct cpu_signature *sig){ sig->sig = cpuid_eax(1); sig->rev = intel_get_microcode_revision(); sig->pf = 1 << intel_get_platform_id();}EXPORT_SYMBOL_GPL(intel_collect_cpu_info); static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2, unsigned int pf2){ if (s1->sig != sig2) return false; /* * Consider an empty mask to match everything. This * should only occur for one CPU model, the PII. */ if (!pf2) return true; /* Is the CPU's platform ID in the signature mask? */ return s1->pf & pf2;} bool intel_find_matching_signature(void *mc, struct cpu_signature *sig){ struct microcode_header_intel *mc_hdr = mc; struct extended_signature *ext_sig; struct extended_sigtable *ext_hdr; int i; if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf)) return true; /* Look for ext. headers: */ if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) return false; ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf)) return true; ext_sig++; } return 0;}EXPORT_SYMBOL_GPL(intel_find_matching_signature); /** * intel_microcode_sanity_check() - Sanity check microcode file. * @mc: Pointer to the microcode file contents. * @print_err: Display failure reason if true, silent if false. * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. * Validate if the microcode header type matches with the type * specified here. * * Validate certain header fields and verify if computed checksum matches * with the one specified in the header. * * Return: 0 if the file passes all the checks, -EINVAL if any of the checks * fail. */int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type){ unsigned long total_size, data_size, ext_table_size; struct microcode_header_intel *mc_header = mc; struct extended_sigtable *ext_header = NULL; u32 sum, orig_sum, ext_sigcount = 0, i; struct extended_signature *ext_sig; total_size = get_totalsize(mc_header); data_size = intel_microcode_get_datasize(mc_header); if (data_size + MC_HEADER_SIZE > total_size) { if (print_err) pr_err("Error: bad microcode data file size.\n"); return -EINVAL; } if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { if (print_err) pr_err("Error: invalid/unknown microcode update format. Header type %d\n", mc_header->hdrver); return -EINVAL; } ext_table_size = total_size - (MC_HEADER_SIZE + data_size); if (ext_table_size) { u32 ext_table_sum = 0; u32 *ext_tablep; if (ext_table_size < EXT_HEADER_SIZE || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { if (print_err) pr_err("Error: truncated extended signature table.\n"); return -EINVAL; } ext_header = mc + MC_HEADER_SIZE + data_size; if (ext_table_size != exttable_size(ext_header)) { if (print_err) pr_err("Error: extended signature table size mismatch.\n"); return -EFAULT; } ext_sigcount = ext_header->count; /* * Check extended table checksum: the sum of all dwords that * comprise a valid table must be 0. */ ext_tablep = (u32 *)ext_header; i = ext_table_size / sizeof(u32); while (i--) ext_table_sum += ext_tablep[i]; if (ext_table_sum) { if (print_err) pr_warn("Bad extended signature table checksum, aborting.\n"); return -EINVAL; } } /* * Calculate the checksum of update data and header. The checksum of * valid update data and header including the extended signature table * must be 0. */ orig_sum = 0; i = (MC_HEADER_SIZE + data_size) / sizeof(u32); while (i--) orig_sum += ((u32 *)mc)[i]; if (orig_sum) { if (print_err) pr_err("Bad microcode data checksum, aborting.\n"); return -EINVAL; } if (!ext_table_size) return 0; /* * Check extended signature checksum: 0 => valid. */ for (i = 0; i < ext_sigcount; i++) { ext_sig = (void *)ext_header + EXT_HEADER_SIZE + EXT_SIGNATURE_SIZE * i; sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - (ext_sig->sig + ext_sig->pf + ext_sig->cksum); if (sum) { if (print_err) pr_err("Bad extended signature checksum, aborting.\n"); return -EINVAL; } } return 0;}EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); static void update_ucode_pointer(struct microcode_intel *mc){ kvfree(ucode_patch_va); /* * Save the virtual address for early loading and for eventual free * on late loading. */ ucode_patch_va = mc;} static void save_microcode_patch(struct microcode_intel *patch){ unsigned int size = get_totalsize(&patch->hdr); struct microcode_intel *mc; mc = kvmemdup(patch, size, GFP_KERNEL); if (mc) update_ucode_pointer(mc); else pr_err("Unable to allocate microcode memory size: %u\n", size);} /* Scan blob for microcode matching the boot CPUs family, model, stepping */static __init struct microcode_intel *scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save){ struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; if (!intel_find_matching_signature(data, &uci->cpu_sig)) continue; /* * For saving the early microcode, find the matching revision which * was loaded on the BSP. * * On the BSP during early boot, find a newer revision than * actually loaded in the CPU. */ if (save) { if (cur_rev != mc_header->rev) continue; } else if (cur_rev >= mc_header->rev) { continue; } patch = data; cur_rev = mc_header->rev; } return size ? NULL : patch;} static inline u32 read_mbox_dword(void __iomem *mmio_base){ u32 dword = readl(mmio_base + MBOX_RDDATA_OFFSET); /* Acknowledge read completion to the staging hardware */ writel(0, mmio_base + MBOX_RDDATA_OFFSET); return dword;} static inline void write_mbox_dword(void __iomem *mmio_base, u32 dword){ writel(dword, mmio_base + MBOX_WRDATA_OFFSET);} static inline u64 read_mbox_header(void __iomem *mmio_base){ u32 high, low; low = read_mbox_dword(mmio_base); high = read_mbox_dword(mmio_base); return ((u64)high << 32) | low;} static inline void write_mbox_header(void __iomem *mmio_base, u64 value){ write_mbox_dword(mmio_base, value); write_mbox_dword(mmio_base, value >> 32);} static void write_mbox_data(void __iomem *mmio_base, u32 *chunk, unsigned int chunk_bytes){ int i; /* * The MMIO space is mapped as Uncached (UC). Each write arrives * at the device as an individual transaction in program order. * The device can then reassemble the sequence accordingly. */ for (i = 0; i < chunk_bytes / sizeof(u32); i++) write_mbox_dword(mmio_base, chunk[i]);} /* * Prepare for a new microcode transfer: reset hardware and record the * image size. */static void init_stage(struct staging_state *ss){ ss->ucode_len = get_totalsize(&ucode_patch_late->hdr); /* * Abort any ongoing process, effectively resetting the device. * Unlike regular mailbox data processing requests, this * operation does not require a status check. */ writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET);} /* * Update the chunk size and decide whether another chunk can be sent. * This accounts for remaining data and retry limits. */static bool can_send_next_chunk(struct staging_state *ss, int *err){ /* A page size or remaining bytes if this is the final chunk */ ss->chunk_size = min(PAGE_SIZE, ss->ucode_len - ss->offset); /* * Each microcode image is divided into chunks, each at most * one page size. A 10-chunk image would typically require 10 * transactions. * * However, the hardware managing the mailbox has limited * resources and may not cache the entire image, potentially * requesting the same chunk multiple times. * * To tolerate this behavior, allow up to twice the expected * number of transactions (i.e., a 10-chunk image can take up to * 20 attempts). * * If the number of attempts exceeds this limit, treat it as * exceeding the maximum allowed transfer size. */ if (ss->bytes_sent + ss->chunk_size > ss->ucode_len * 2) { *err = -EMSGSIZE; return false; } *err = 0; return true;} /* * The hardware indicates completion by returning a sentinel end offset. */static inline bool is_end_offset(u32 offset){ return offset == UINT_MAX;} /* * Determine whether staging is complete: either the hardware signaled * the end offset, or no more transactions are permitted (retry limit * reached). */static inline bool staging_is_complete(struct staging_state *ss, int *err){ return is_end_offset(ss->offset) || !can_send_next_chunk(ss, err);} Lines 1–500 of 1052. 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// SPDX-License-Identifier: GPL-2.0-or-later /* * Intel CPU Microcode Update Driver for Linux * * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> * 2006 Shaohua Li <shaohua.li@intel.com> * * Intel CPU microcode early update for Linux * * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> * H Peter Anvin" <hpa@zytor.com> */ #define pr_fmt(fmt) "microcode: " fmt #include <linux/earlycpio.h> #include <linux/firmware.h> #include <linux/pci_ids.h> #include <linux/uaccess.h> #include <linux/initrd.h> #include <linux/kernel.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/cpu.h> #include <linux/uio.h> #include <linux/io.h> #include <linux/mm.h> #include <asm/cpu_device_id.h> #include <asm/cpuid/api.h> #include <asm/processor.h> #include <asm/tlbflush.h> #include <asm/setup.h> #include <asm/msr.h> #include "internal.h" static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; #define UCODE_BSP_LOADED ((struct microcode_intel *)0x1UL) /* Defines for the microcode staging mailbox interface */ #define MBOX_REG_NUM 4 #define MBOX_REG_SIZE sizeof(u32) #define MBOX_CONTROL_OFFSET 0x0 #define MBOX_STATUS_OFFSET 0x4 #define MBOX_WRDATA_OFFSET 0x8 #define MBOX_RDDATA_OFFSET 0xc #define MASK_MBOX_CTRL_ABORT BIT(0) #define MASK_MBOX_CTRL_GO BIT(31) #define MASK_MBOX_STATUS_ERROR BIT(2) #define MASK_MBOX_STATUS_READY BIT(31) #define MASK_MBOX_RESP_SUCCESS BIT(0) #define MASK_MBOX_RESP_PROGRESS BIT(1) #define MASK_MBOX_RESP_ERROR BIT(2) #define MBOX_CMD_LOAD 0x3 #define MBOX_OBJ_STAGING 0xb #define MBOX_HEADER(size) ((PCI_VENDOR_ID_INTEL) | \ (MBOX_OBJ_STAGING << 16) | \ ((u64)((size) / sizeof(u32)) << 32)) /* The size of each mailbox header */ #define MBOX_HEADER_SIZE sizeof(u64) /* The size of staging hardware response */ #define MBOX_RESPONSE_SIZE sizeof(u64) #define MBOX_XACTION_TIMEOUT_MS (10 * MSEC_PER_SEC) /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { unsigned int sig; unsigned int pf; unsigned int cksum; }; struct extended_sigtable { unsigned int count; unsigned int cksum; unsigned int reserved[3]; struct extended_signature sigs[]; }; /** * struct staging_state - Track the current staging process state * * @mmio_base: MMIO base address for staging * @ucode_len: Total size of the microcode image * @chunk_size: Size of each data piece * @bytes_sent: Total bytes transmitted so far * @offset: Current offset in the microcode image */ struct staging_state { void __iomem *mmio_base; unsigned int ucode_len; unsigned int chunk_size; unsigned int bytes_sent; unsigned int offset; }; #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) #define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) #define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) static inline unsigned int get_totalsize(struct microcode_header_intel *hdr) { return hdr->datasize ? hdr->totalsize : DEFAULT_UCODE_TOTALSIZE; } static inline unsigned int exttable_size(struct extended_sigtable *et) { return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } /* * Use CPUID to generate a "vfm" value. Useful before cpuinfo_x86 * structures are populated. */ static u32 intel_cpuid_vfm(void) { u32 eax = cpuid_eax(1); u32 fam = x86_family(eax); u32 model = x86_model(eax); return IFM(fam, model); } u32 intel_get_platform_id(void) { unsigned int val[2]; if (x86_hypervisor_present) return 0; /* * This can be called early. Use CPUID directly instead of * relying on cpuinfo_x86 which may not be fully initialized. * The PII does not have MSR_IA32_PLATFORM_ID. Everything * before _it_ has no microcode (for Linux at least). */ if (intel_cpuid_vfm() <= INTEL_PENTIUM_II_KLAMATH) return 0; /* get processor flags from MSR 0x17 */ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); return (val[1] >> 18) & 7; } void intel_collect_cpu_info(struct cpu_signature *sig) { sig->sig = cpuid_eax(1); sig->rev = intel_get_microcode_revision(); sig->pf = 1 << intel_get_platform_id(); } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2, unsigned int pf2) { if (s1->sig != sig2) return false; /* * Consider an empty mask to match everything. This * should only occur for one CPU model, the PII. */ if (!pf2) return true; /* Is the CPU's platform ID in the signature mask? */ return s1->pf & pf2; } bool intel_find_matching_signature(void *mc, struct cpu_signature *sig) { struct microcode_header_intel *mc_hdr = mc; struct extended_signature *ext_sig; struct extended_sigtable *ext_hdr; int i; if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf)) return true; /* Look for ext. headers: */ if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) return false; ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf)) return true; ext_sig++; } return 0; } EXPORT_SYMBOL_GPL(intel_find_matching_signature); /** * intel_microcode_sanity_check() - Sanity check microcode file. * @mc: Pointer to the microcode file contents. * @print_err: Display failure reason if true, silent if false. * @hdr_type: Type of file, i.e. normal microcode file or In Field Scan file. * Validate if the microcode header type matches with the type * specified here. * * Validate certain header fields and verify if computed checksum matches * with the one specified in the header. * * Return: 0 if the file passes all the checks, -EINVAL if any of the checks * fail. */ int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) { unsigned long total_size, data_size, ext_table_size; struct microcode_header_intel *mc_header = mc; struct extended_sigtable *ext_header = NULL; u32 sum, orig_sum, ext_sigcount = 0, i; struct extended_signature *ext_sig; total_size = get_totalsize(mc_header); data_size = intel_microcode_get_datasize(mc_header); if (data_size + MC_HEADER_SIZE > total_size) { if (print_err) pr_err("Error: bad microcode data file size.\n"); return -EINVAL; } if (mc_header->ldrver != 1 || mc_header->hdrver != hdr_type) { if (print_err) pr_err("Error: invalid/unknown microcode update format. Header type %d\n", mc_header->hdrver); return -EINVAL; } ext_table_size = total_size - (MC_HEADER_SIZE + data_size); if (ext_table_size) { u32 ext_table_sum = 0; u32 *ext_tablep; if (ext_table_size < EXT_HEADER_SIZE || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { if (print_err) pr_err("Error: truncated extended signature table.\n"); return -EINVAL; } ext_header = mc + MC_HEADER_SIZE + data_size; if (ext_table_size != exttable_size(ext_header)) { if (print_err) pr_err("Error: extended signature table size mismatch.\n"); return -EFAULT; } ext_sigcount = ext_header->count; /* * Check extended table checksum: the sum of all dwords that * comprise a valid table must be 0. */ ext_tablep = (u32 *)ext_header; i = ext_table_size / sizeof(u32); while (i--) ext_table_sum += ext_tablep[i]; if (ext_table_sum) { if (print_err) pr_warn("Bad extended signature table checksum, aborting.\n"); return -EINVAL; } } /* * Calculate the checksum of update data and header. The checksum of * valid update data and header including the extended signature table * must be 0. */ orig_sum = 0; i = (MC_HEADER_SIZE + data_size) / sizeof(u32); while (i--) orig_sum += ((u32 *)mc)[i]; if (orig_sum) { if (print_err) pr_err("Bad microcode data checksum, aborting.\n"); return -EINVAL; } if (!ext_table_size) return 0; /* * Check extended signature checksum: 0 => valid. */ for (i = 0; i < ext_sigcount; i++) { ext_sig = (void *)ext_header + EXT_HEADER_SIZE + EXT_SIGNATURE_SIZE * i; sum = (mc_header->sig + mc_header->pf + mc_header->cksum) - (ext_sig->sig + ext_sig->pf + ext_sig->cksum); if (sum) { if (print_err) pr_err("Bad extended signature checksum, aborting.\n"); return -EINVAL; } } return 0; } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); static void update_ucode_pointer(struct microcode_intel *mc) { kvfree(ucode_patch_va); /* * Save the virtual address for early loading and for eventual free * on late loading. */ ucode_patch_va = mc; } static void save_microcode_patch(struct microcode_intel *patch) { unsigned int size = get_totalsize(&patch->hdr); struct microcode_intel *mc; mc = kvmemdup(patch, size, GFP_KERNEL); if (mc) update_ucode_pointer(mc); else pr_err("Unable to allocate microcode memory size: %u\n", size); } /* Scan blob for microcode matching the boot CPUs family, model, stepping */ static __init struct microcode_intel *scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; if (!intel_find_matching_signature(data, &uci->cpu_sig)) continue; /* * For saving the early microcode, find the matching revision which * was loaded on the BSP. * * On the BSP during early boot, find a newer revision than * actually loaded in the CPU. */ if (save) { if (cur_rev != mc_header->rev) continue; } else if (cur_rev >= mc_header->rev) { continue; } patch = data; cur_rev = mc_header->rev; } return size ? NULL : patch; } static inline u32 read_mbox_dword(void __iomem *mmio_base) { u32 dword = readl(mmio_base + MBOX_RDDATA_OFFSET); /* Acknowledge read completion to the staging hardware */ writel(0, mmio_base + MBOX_RDDATA_OFFSET); return dword; } static inline void write_mbox_dword(void __iomem *mmio_base, u32 dword) { writel(dword, mmio_base + MBOX_WRDATA_OFFSET); } static inline u64 read_mbox_header(void __iomem *mmio_base) { u32 high, low; low = read_mbox_dword(mmio_base); high = read_mbox_dword(mmio_base); return ((u64)high << 32) | low; } static inline void write_mbox_header(void __iomem *mmio_base, u64 value) { write_mbox_dword(mmio_base, value); write_mbox_dword(mmio_base, value >> 32); } static void write_mbox_data(void __iomem *mmio_base, u32 *chunk, unsigned int chunk_bytes) { int i; /* * The MMIO space is mapped as Uncached (UC). Each write arrives * at the device as an individual transaction in program order. * The device can then reassemble the sequence accordingly. */ for (i = 0; i < chunk_bytes / sizeof(u32); i++) write_mbox_dword(mmio_base, chunk[i]); } /* * Prepare for a new microcode transfer: reset hardware and record the * image size. */ static void init_stage(struct staging_state *ss) { ss->ucode_len = get_totalsize(&ucode_patch_late->hdr); /* * Abort any ongoing process, effectively resetting the device. * Unlike regular mailbox data processing requests, this * operation does not require a status check. */ writel(MASK_MBOX_CTRL_ABORT, ss->mmio_base + MBOX_CONTROL_OFFSET); } /* * Update the chunk size and decide whether another chunk can be sent. * This accounts for remaining data and retry limits. */ static bool can_send_next_chunk(struct staging_state *ss, int *err) { /* A page size or remaining bytes if this is the final chunk */ ss->chunk_size = min(PAGE_SIZE, ss->ucode_len - ss->offset); /* * Each microcode image is divided into chunks, each at most * one page size. A 10-chunk image would typically require 10 * transactions. * * However, the hardware managing the mailbox has limited * resources and may not cache the entire image, potentially * requesting the same chunk multiple times. * * To tolerate this behavior, allow up to twice the expected * number of transactions (i.e., a 10-chunk image can take up to * 20 attempts). * * If the number of attempts exceeds this limit, treat it as * exceeding the maximum allowed transfer size. */ if (ss->bytes_sent + ss->chunk_size > ss->ucode_len * 2) { *err = -EMSGSIZE; return false; } *err = 0; return true; } /* * The hardware indicates completion by returning a sentinel end offset. */ static inline bool is_end_offset(u32 offset) { return offset == UINT_MAX; } /* * Determine whether staging is complete: either the hardware signaled * the end offset, or no more transactions are permitted (retry limit * reached). */ static inline bool staging_is_complete(struct staging_state *ss, int *err) { return is_end_offset(ss->offset) || !can_send_next_chunk(ss, err); }