/* * Copyright 2010 Tilera Corporation. All Rights Reserved. * *   This program is free software; you can redistribute it and/or *   modify it under the terms of the GNU General Public License *   as published by the Free Software Foundation, version 2. * *   This program is distributed in the hope that it will be useful, but *   WITHOUT ANY WARRANTY; without even the implied warranty of *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or *   NON INFRINGEMENT.  See the GNU General Public License for *   more details. * * Linux interrupt vectors. */ #include <linux/linkage.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/unistd.h>#include <asm/ptrace.h>#include <asm/thread_info.h>#include <asm/irqflags.h>#include <asm/atomic_32.h>#include <asm/asm-offsets.h>#include <hv/hypervisor.h>#include <arch/abi.h>#include <arch/interrupts.h>#include <arch/spr_def.h> #ifdef CONFIG_PREEMPT# error "No support for kernel preemption currently"#endif #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR) #if !CHIP_HAS_WH64()	/* By making this an empty macro, we can use wh64 in the code. */	.macro  wh64 reg	.endm#endif 	.macro  push_reg reg, ptr=sp, delta=-4	{	 sw     \ptr, \reg	 addli  \ptr, \ptr, \delta	}	.endm 	.macro  pop_reg reg, ptr=sp, delta=4	{	 lw     \reg, \ptr	 addli  \ptr, \ptr, \delta	}	.endm 	.macro  pop_reg_zero reg, zreg, ptr=sp, delta=4	{	 move   \zreg, zero	 lw     \reg, \ptr	 addi   \ptr, \ptr, \delta	}	.endm 	.macro  push_extra_callee_saves reg	PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))	push_reg r51, \reg	push_reg r50, \reg	push_reg r49, \reg	push_reg r48, \reg	push_reg r47, \reg	push_reg r46, \reg	push_reg r45, \reg	push_reg r44, \reg	push_reg r43, \reg	push_reg r42, \reg	push_reg r41, \reg	push_reg r40, \reg	push_reg r39, \reg	push_reg r38, \reg	push_reg r37, \reg	push_reg r36, \reg	push_reg r35, \reg	push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)	.endm 	.macro  panic str	.pushsection .rodata, "a"1:	.asciz  "\str"	.popsection	{	 moveli r0, lo16(1b)	}	{	 auli   r0, r0, ha16(1b)	 jal    panic	}	.endm #ifdef __COLLECT_LINKER_FEEDBACK__	.pushsection .text.intvec_feedback,"ax"intvec_feedback:	.popsection#endif 	/*	 * Default interrupt handler.	 *	 * vecnum is where we'll put this code.	 * c_routine is the C routine we'll call.	 *	 * The C routine is passed two arguments:	 * - A pointer to the pt_regs state.	 * - The interrupt vector number.	 *	 * The "processing" argument specifies the code for processing	 * the interrupt. Defaults to "handle_interrupt".	 */	.macro  int_hand vecnum, vecname, c_routine, processing=handle_interrupt	.org    (\vecnum << 8)intvec_\vecname:	.ifc    \vecnum, INT_SWINT_1	blz     TREG_SYSCALL_NR_NAME, sys_cmpxchg	.endif 	/* Temporarily save a register so we have somewhere to work. */ 	mtspr   SPR_SYSTEM_SAVE_K_1, r0	mfspr   r0, SPR_EX_CONTEXT_K_1 	/* The cmpxchg code clears sp to force us to reset it here on fault. */	{	 bz     sp, 2f	 andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */	} 	.ifc    \vecnum, INT_DOUBLE_FAULT	/*	 * For double-faults from user-space, fall through to the normal	 * register save and stack setup path.  Otherwise, it's the	 * hypervisor giving us one last chance to dump diagnostics, and we	 * branch to the kernel_double_fault routine to do so.	 */	bz      r0, 1f	j       _kernel_double_fault1:	.else	/*	 * If we're coming from user-space, then set sp to the top of	 * the kernel stack.  Otherwise, assume sp is already valid.	 */	{	 bnz    r0, 0f	 move   r0, sp	}	.endif 	.ifc    \c_routine, do_page_fault	/*	 * The page_fault handler may be downcalled directly by the	 * hypervisor even when Linux is running and has ICS set.	 *	 * In this case the contents of EX_CONTEXT_K_1 reflect the	 * previous fault and can't be relied on to choose whether or	 * not to reinitialize the stack pointer.  So we add a test	 * to see whether SYSTEM_SAVE_K_2 has the high bit set,	 * and if so we don't reinitialize sp, since we must be coming	 * from Linux.  (In fact the precise case is !(val & ~1),	 * but any Linux PC has to have the high bit set.)	 *	 * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for	 * any path that turns into a downcall to one of our TLB handlers.	 */	mfspr   r0, SPR_SYSTEM_SAVE_K_2	{	 blz    r0, 0f    /* high bit in S_S_1_2 is for a PC to use */	 move   r0, sp	}	.endif 2:	/*	 * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and	 * the current stack top in the higher bits.  So we recover	 * our stack top by just masking off the low bits, then	 * point sp at the top aligned address on the actual stack page.	 */	mfspr   r0, SPR_SYSTEM_SAVE_K_0	mm      r0, r0, zero, LOG2_THREAD_SIZE, 31 0:	/*	 * Align the stack mod 64 so we can properly predict what	 * cache lines we need to write-hint to reduce memory fetch	 * latency as we enter the kernel.  The layout of memory is	 * as follows, with cache line 0 at the lowest VA, and cache	 * line 4 just below the r0 value this "andi" computes.	 * Note that we never write to cache line 4, and we skip	 * cache line 1 for syscalls.	 *	 *    cache line 4: ptregs padding (two words)	 *    cache line 3: r46...lr, pc, ex1, faultnum, orig_r0, flags, pad	 *    cache line 2: r30...r45	 *    cache line 1: r14...r29	 *    cache line 0: 2 x frame, r0..r13	 */	andi    r0, r0, -64 	/*	 * Push the first four registers on the stack, so that we can set	 * them to vector-unique values before we jump to the common code.	 *	 * Registers are pushed on the stack as a struct pt_regs,	 * with the sp initially just above the struct, and when we're	 * done, sp points to the base of the struct, minus	 * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.	 *	 * This routine saves just the first four registers, plus the	 * stack context so we can do proper backtracing right away,	 * and defers to handle_interrupt to save the rest.	 * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.	 */	addli   r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)	wh64    r0    /* cache line 3 */	{	 sw     r0, lr	 addli  r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR	}	{	 sw     r0, sp	 addli  sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP	}	{	 sw     sp, r52	 addli  sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)	}	wh64    sp    /* cache line 0 */	{	 sw     sp, r1	 addli  sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)	}	{	 sw     sp, r2	 addli  sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)	}	{	 sw     sp, r3	 addli  sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)	}	mfspr   r0, SPR_EX_CONTEXT_K_0	.ifc \processing,handle_syscall	/*	 * Bump the saved PC by one bundle so that when we return, we won't	 * execute the same swint instruction again.  We need to do this while	 * we're in the critical section.	 */	addi    r0, r0, 8	.endif	{	 sw     sp, r0	 addli  sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC	}	mfspr   r0, SPR_EX_CONTEXT_K_1	{	 sw     sp, r0	 addi   sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1	/*	 * Use r0 for syscalls so it's a temporary; use r1 for interrupts	 * so that it gets passed through unchanged to the handler routine.	 * Note that the .if conditional confusingly spans bundles.	 */	 .ifc \processing,handle_syscall	 movei  r0, \vecnum	}	{	 sw     sp, r0	 .else	 movei  r1, \vecnum	}	{	 sw     sp, r1	 .endif	 addli  sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM	}	mfspr   r0, SPR_SYSTEM_SAVE_K_1    /* Original r0 */	{	 sw     sp, r0	 addi   sp, sp, -PTREGS_OFFSET_REG(0) - 4	}	{	 sw     sp, zero        /* write zero into "Next SP" frame pointer */	 addi   sp, sp, -4      /* leave SP pointing at bottom of frame */	}	.ifc \processing,handle_syscall	j       handle_syscall	.else	/*	 * Capture per-interrupt SPR context to registers.	 * We overload the meaning of r3 on this path such that if its bit 31	 * is set, we have to mask all interrupts including NMIs before	 * clearing the interrupt critical section bit.	 * See discussion below at "finish_interrupt_save".	 */	.ifc \c_routine, do_page_fault	mfspr   r2, SPR_SYSTEM_SAVE_K_3   /* address of page fault */	mfspr   r3, SPR_SYSTEM_SAVE_K_2   /* info about page fault */	.else	.ifc \vecnum, INT_DOUBLE_FAULT	{	 mfspr  r2, SPR_SYSTEM_SAVE_K_2   /* double fault info from HV */	 movei  r3, 0	}	.else	.ifc \c_routine, do_trap	{	 mfspr  r2, GPV_REASON	 movei  r3, 0	}	.else	.ifc \c_routine, op_handle_perf_interrupt	{	 mfspr  r2, PERF_COUNT_STS	 movei  r3, -1   /* not used, but set for consistency */	}	.else#if CHIP_HAS_AUX_PERF_COUNTERS()	.ifc \c_routine, op_handle_aux_perf_interrupt	{	 mfspr  r2, AUX_PERF_COUNT_STS	 movei  r3, -1   /* not used, but set for consistency */	}	.else#endif	movei   r3, 0#if CHIP_HAS_AUX_PERF_COUNTERS()	.endif#endif	.endif	.endif	.endif	.endif	/* Put function pointer in r0 */	moveli  r0, lo16(\c_routine)	{	 auli   r0, r0, ha16(\c_routine)	 j       \processing	}	.endif	ENDPROC(intvec_\vecname) #ifdef __COLLECT_LINKER_FEEDBACK__	.pushsection .text.intvec_feedback,"ax"	.org    (\vecnum << 5)	FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)	jrp     lr	.popsection#endif 	.endm  	/*	 * Save the rest of the registers that we didn't save in the actual	 * vector itself.  We can't use r0-r10 inclusive here.	 */	.macro  finish_interrupt_save, function 	/* If it's a syscall, save a proper orig_r0, otherwise just zero. */	PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)	{	 .ifc \function,handle_syscall	 sw     r52, r0	 .else	 sw     r52, zero	 .endif	 PTREGS_PTR(r52, PTREGS_OFFSET_TP)	} 	/*	 * For ordinary syscalls, we save neither caller- nor callee-	 * save registers, since the syscall invoker doesn't expect the	 * caller-saves to be saved, and the called kernel functions will	 * take care of saving the callee-saves for us.	 *	 * For interrupts we save just the caller-save registers.  Saving	 * them is required (since the "caller" can't save them).  Again,	 * the called kernel functions will restore the callee-save	 * registers for us appropriately.	 *	 * On return, we normally restore nothing special for syscalls,	 * and just the caller-save registers for interrupts.	 *	 * However, there are some important caveats to all this:	 *	 * - We always save a few callee-save registers to give us	 *   some scratchpad registers to carry across function calls.	 *	 * - fork/vfork/etc require us to save all the callee-save	 *   registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.	 *	 * - We always save r0..r5 and r10 for syscalls, since we need	 *   to reload them a bit later for the actual kernel call, and	 *   since we might need them for -ERESTARTNOINTR, etc.	 *	 * - Before invoking a signal handler, we save the unsaved	 *   callee-save registers so they are visible to the	 *   signal handler or any ptracer.	 *	 * - If the unsaved callee-save registers are modified, we set	 *   a bit in pt_regs so we know to reload them from pt_regs	 *   and not just rely on the kernel function unwinding.	 *   (Done for ptrace register writes and SA_SIGINFO handler.)	 */	{	 sw     r52, tp	 PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))	}	wh64    r52    /* cache line 2 */	push_reg r33, r52	push_reg r32, r52	push_reg r31, r52	.ifc \function,handle_syscall	push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)	push_reg TREG_SYSCALL_NR_NAME, r52, \	  PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL	.else 	push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)	wh64    r52    /* cache line 1 */	push_reg r29, r52	push_reg r28, r52	push_reg r27, r52	push_reg r26, r52	push_reg r25, r52	push_reg r24, r52	push_reg r23, r52	push_reg r22, r52	push_reg r21, r52	push_reg r20, r52	push_reg r19, r52	push_reg r18, r52	push_reg r17, r52	push_reg r16, r52	push_reg r15, r52	push_reg r14, r52	push_reg r13, r52	push_reg r12, r52	push_reg r11, r52	push_reg r10, r52	push_reg r9, r52	push_reg r8, r52	push_reg r7, r52	push_reg r6, r52 	.endif 	push_reg r5, r52	sw      r52, r4 	/* Load tp with our per-cpu offset. */#ifdef CONFIG_SMP	{	 mfspr  r20, SPR_SYSTEM_SAVE_K_0	 moveli r21, lo16(__per_cpu_offset)	}	{	 auli   r21, r21, ha16(__per_cpu_offset)	 mm     r20, r20, zero, 0, LOG2_THREAD_SIZE-1	}	s2a     r20, r20, r21	lw      tp, r20#else	move    tp, zero#endif 	/*	 * If we will be returning to the kernel, we will need to	 * reset the interrupt masks to the state they had before.	 * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.	 * We load flags in r32 here so we can jump to .Lrestore_regs	 * directly after do_page_fault_ics() if necessary.	 */	mfspr   r32, SPR_EX_CONTEXT_K_1	{	 andi   r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */	 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)	}	bzt     r32, 1f       /* zero if from user space */	IRQS_DISABLED(r32)    /* zero if irqs enabled */#if PT_FLAGS_DISABLE_IRQ != 1# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix#endif1:	.ifnc \function,handle_syscall	/* Record the fact that we saved the caller-save registers above. */	ori     r32, r32, PT_FLAGS_CALLER_SAVES	.endif

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