/* * Support for IDE interfaces on PowerMacs. * * These IDE interfaces are memory-mapped and have a DBDMA channel * for doing DMA. * *  Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt *  Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz * *  This program is free software; you can redistribute it and/or *  modify it under the terms of the GNU General Public License *  as published by the Free Software Foundation; either version *  2 of the License, or (at your option) any later version. * * Some code taken from drivers/ide/ide-dma.c: * *  Copyright (c) 1995-1998  Mark Lord * * TODO: - Use pre-calculated (kauai) timing tables all the time and * get rid of the "rounded" tables used previously, so we have the * same table format for all controllers and can then just have one * big table *  */#include <linux/types.h>#include <linux/kernel.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/ide.h>#include <linux/notifier.h>#include <linux/module.h>#include <linux/reboot.h>#include <linux/pci.h>#include <linux/adb.h>#include <linux/pmu.h>#include <linux/scatterlist.h>#include <linux/slab.h> #include <asm/prom.h>#include <asm/io.h>#include <asm/dbdma.h>#include <asm/ide.h>#include <asm/pci-bridge.h>#include <asm/machdep.h>#include <asm/pmac_feature.h>#include <asm/sections.h>#include <asm/irq.h>#include <asm/mediabay.h> #define DRV_NAME "ide-pmac" #undef IDE_PMAC_DEBUG #define DMA_WAIT_TIMEOUT	50 typedef struct pmac_ide_hwif {	unsigned long			regbase;	int				irq;	int				kind;	int				aapl_bus_id;	unsigned			broken_dma : 1;	unsigned			broken_dma_warn : 1;	struct device_node*		node;	struct macio_dev		*mdev;	u32				timings[4];	volatile u32 __iomem *		*kauai_fcr;	ide_hwif_t			*hwif; 	/* Those fields are duplicating what is in hwif. We currently	 * can't use the hwif ones because of some assumptions that are	 * beeing done by the generic code about the kind of dma controller	 * and format of the dma table. This will have to be fixed though.	 */	volatile struct dbdma_regs __iomem *	dma_regs;	struct dbdma_cmd*		dma_table_cpu;} pmac_ide_hwif_t; enum {	controller_ohare,	/* OHare based */	controller_heathrow,	/* Heathrow/Paddington */	controller_kl_ata3,	/* KeyLargo ATA-3 */	controller_kl_ata4,	/* KeyLargo ATA-4 */	controller_un_ata6,	/* UniNorth2 ATA-6 */	controller_k2_ata6,	/* K2 ATA-6 */	controller_sh_ata6,	/* Shasta ATA-6 */}; static const char* model_name[] = {	"OHare ATA",		/* OHare based */	"Heathrow ATA",		/* Heathrow/Paddington */	"KeyLargo ATA-3",	/* KeyLargo ATA-3 (MDMA only) */	"KeyLargo ATA-4",	/* KeyLargo ATA-4 (UDMA/66) */	"UniNorth ATA-6",	/* UniNorth2 ATA-6 (UDMA/100) */	"K2 ATA-6",		/* K2 ATA-6 (UDMA/100) */	"Shasta ATA-6",		/* Shasta ATA-6 (UDMA/133) */}; /* * Extra registers, both 32-bit little-endian */#define IDE_TIMING_CONFIG	0x200#define IDE_INTERRUPT		0x300 /* Kauai (U2) ATA has different register setup */#define IDE_KAUAI_PIO_CONFIG	0x200#define IDE_KAUAI_ULTRA_CONFIG	0x210#define IDE_KAUAI_POLL_CONFIG	0x220 /* * Timing configuration register definitions */ /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */#define SYSCLK_TICKS(t)		(((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)#define SYSCLK_TICKS_66(t)	(((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)#define IDE_SYSCLK_NS		30	/* 33Mhz cell */#define IDE_SYSCLK_66_NS	15	/* 66Mhz cell */ /* 133Mhz cell, found in shasta. * See comments about 100 Mhz Uninorth 2... * Note that PIO_MASK and MDMA_MASK seem to overlap */#define TR_133_PIOREG_PIO_MASK		0xff000fff#define TR_133_PIOREG_MDMA_MASK		0x00fff800#define TR_133_UDMAREG_UDMA_MASK	0x0003ffff#define TR_133_UDMAREG_UDMA_EN		0x00000001 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about * this one yet, it appears as a pci device (106b/0033) on uninorth * internal PCI bus and it's clock is controlled like gem or fw. It * appears to be an evolution of keylargo ATA4 with a timing register * extended to 2 32bits registers and a similar DBDMA channel. Other * registers seem to exist but I can't tell much about them. *  * So far, I'm using pre-calculated tables for this extracted from * the values used by the MacOS X driver. *  * The "PIO" register controls PIO and MDMA timings, the "ULTRA" * register controls the UDMA timings. At least, it seems bit 0 * of this one enables UDMA vs. MDMA, and bits 4..7 are the * cycle time in units of 10ns. Bits 8..15 are used by I don't * know their meaning yet */#define TR_100_PIOREG_PIO_MASK		0xff000fff#define TR_100_PIOREG_MDMA_MASK		0x00fff000#define TR_100_UDMAREG_UDMA_MASK	0x0000ffff#define TR_100_UDMAREG_UDMA_EN		0x00000001  /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on * 40 connector cable and to 4 on 80 connector one. * Clock unit is 15ns (66Mhz) *  * 3 Values can be programmed: *  - Write data setup, which appears to match the cycle time. They *    also call it DIOW setup. *  - Ready to pause time (from spec) *  - Address setup. That one is weird. I don't see where exactly *    it fits in UDMA cycles, I got it's name from an obscure piece *    of commented out code in Darwin. They leave it to 0, we do as *    well, despite a comment that would lead to think it has a *    min value of 45ns. * Apple also add 60ns to the write data setup (or cycle time ?) on * reads. */#define TR_66_UDMA_MASK			0xfff00000#define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */#define TR_66_UDMA_ADDRSETUP_MASK	0xe0000000 /* Address setup */#define TR_66_UDMA_ADDRSETUP_SHIFT	29#define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */#define TR_66_UDMA_RDY2PAUS_SHIFT	25#define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */#define TR_66_UDMA_WRDATASETUP_SHIFT	21#define TR_66_MDMA_MASK			0x000ffc00#define TR_66_MDMA_RECOVERY_MASK	0x000f8000#define TR_66_MDMA_RECOVERY_SHIFT	15#define TR_66_MDMA_ACCESS_MASK		0x00007c00#define TR_66_MDMA_ACCESS_SHIFT		10#define TR_66_PIO_MASK			0x000003ff#define TR_66_PIO_RECOVERY_MASK		0x000003e0#define TR_66_PIO_RECOVERY_SHIFT	5#define TR_66_PIO_ACCESS_MASK		0x0000001f#define TR_66_PIO_ACCESS_SHIFT		0 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo * Can do pio & mdma modes, clock unit is 30ns (33Mhz) *  * The access time and recovery time can be programmed. Some older * Darwin code base limit OHare to 150ns cycle time. I decided to do * the same here fore safety against broken old hardware ;) * The HalfTick bit, when set, adds half a clock (15ns) to the access * time and removes one from recovery. It's not supported on KeyLargo * implementation afaik. The E bit appears to be set for PIO mode 0 and * is used to reach long timings used in this mode. */#define TR_33_MDMA_MASK			0x003ff800#define TR_33_MDMA_RECOVERY_MASK	0x001f0000#define TR_33_MDMA_RECOVERY_SHIFT	16#define TR_33_MDMA_ACCESS_MASK		0x0000f800#define TR_33_MDMA_ACCESS_SHIFT		11#define TR_33_MDMA_HALFTICK		0x00200000#define TR_33_PIO_MASK			0x000007ff#define TR_33_PIO_E			0x00000400#define TR_33_PIO_RECOVERY_MASK		0x000003e0#define TR_33_PIO_RECOVERY_SHIFT	5#define TR_33_PIO_ACCESS_MASK		0x0000001f#define TR_33_PIO_ACCESS_SHIFT		0 /* * Interrupt register definitions */#define IDE_INTR_DMA			0x80000000#define IDE_INTR_DEVICE			0x40000000 /* * FCR Register on Kauai. Not sure what bit 0x4 is  ... */#define KAUAI_FCR_UATA_MAGIC		0x00000004#define KAUAI_FCR_UATA_RESET_N		0x00000002#define KAUAI_FCR_UATA_ENABLE		0x00000001 /* Rounded Multiword DMA timings *  * I gave up finding a generic formula for all controller * types and instead, built tables based on timing values * used by Apple in Darwin's implementation. */struct mdma_timings_t {	int	accessTime;	int	recoveryTime;	int	cycleTime;}; struct mdma_timings_t mdma_timings_33[] ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  75,  75, 150 },    {  75,  45, 120 },    {   0,   0,   0 }}; struct mdma_timings_t mdma_timings_33k[] ={    { 240, 240, 480 },    { 180, 180, 360 },    { 150, 150, 300 },    { 120, 120, 240 },    {  90, 120, 210 },    {  90,  90, 180 },    {  90,  60, 150 },    {  90,  30, 120 },    {   0,   0,   0 }}; struct mdma_timings_t mdma_timings_66[] ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  90,  75, 165 },    {  75,  45, 120 },    {   0,   0,   0 }}; /* KeyLargo ATA-4 Ultra DMA timings (rounded) */struct {	int	addrSetup; /* ??? */	int	rdy2pause;	int	wrDataSetup;} kl66_udma_timings[] ={    {   0, 180,  120 },	/* Mode 0 */    {   0, 150,  90 },	/*      1 */    {   0, 120,  60 },	/*      2 */    {   0, 90,   45 },	/*      3 */    {   0, 90,   30 }	/*      4 */}; /* UniNorth 2 ATA/100 timings */struct kauai_timing {	int	cycle_time;	u32	timing_reg;}; static struct kauai_timing	kauai_pio_timings[] ={	{ 930	, 0x08000fff },	{ 600	, 0x08000a92 },	{ 383	, 0x0800060f },	{ 360	, 0x08000492 },	{ 330	, 0x0800048f },	{ 300	, 0x080003cf },	{ 270	, 0x080003cc },	{ 240	, 0x0800038b },	{ 239	, 0x0800030c },	{ 180	, 0x05000249 },	{ 120	, 0x04000148 },	{ 0	, 0 },}; static struct kauai_timing	kauai_mdma_timings[] ={	{ 1260	, 0x00fff000 },	{ 480	, 0x00618000 },	{ 360	, 0x00492000 },	{ 270	, 0x0038e000 },	{ 240	, 0x0030c000 },	{ 210	, 0x002cb000 },	{ 180	, 0x00249000 },	{ 150	, 0x00209000 },	{ 120	, 0x00148000 },	{ 0	, 0 },}; static struct kauai_timing	kauai_udma_timings[] ={	{ 120	, 0x000070c0 },	{ 90	, 0x00005d80 },	{ 60	, 0x00004a60 },	{ 45	, 0x00003a50 },	{ 30	, 0x00002a30 },	{ 20	, 0x00002921 },	{ 0	, 0 },}; static struct kauai_timing	shasta_pio_timings[] ={	{ 930	, 0x08000fff },	{ 600	, 0x0A000c97 },	{ 383	, 0x07000712 },	{ 360	, 0x040003cd },	{ 330	, 0x040003cd },	{ 300	, 0x040003cd },	{ 270	, 0x040003cd },	{ 240	, 0x040003cd },	{ 239	, 0x040003cd },	{ 180	, 0x0400028b },	{ 120	, 0x0400010a },	{ 0	, 0 },}; static struct kauai_timing	shasta_mdma_timings[] ={	{ 1260	, 0x00fff000 },	{ 480	, 0x00820800 },	{ 360	, 0x00820800 },	{ 270	, 0x00820800 },	{ 240	, 0x00820800 },	{ 210	, 0x00820800 },	{ 180	, 0x00820800 },	{ 150	, 0x0028b000 },	{ 120	, 0x001ca000 },	{ 0	, 0 },}; static struct kauai_timing	shasta_udma133_timings[] ={	{ 120   , 0x00035901, },	{ 90    , 0x000348b1, },	{ 60    , 0x00033881, },	{ 45    , 0x00033861, },	{ 30    , 0x00033841, },	{ 20    , 0x00033031, },	{ 15    , 0x00033021, },	{ 0	, 0 },};  static inline u32kauai_lookup_timing(struct kauai_timing* table, int cycle_time){	int i;		for (i=0; table[i].cycle_time; i++)		if (cycle_time > table[i+1].cycle_time)			return table[i].timing_reg;	BUG();	return 0;} /* allow up to 256 DBDMA commands per xfer */#define MAX_DCMDS		256 /*  * Wait 1s for disk to answer on IDE bus after a hard reset * of the device (via GPIO/FCR). *  * Some devices seem to "pollute" the bus even after dropping * the BSY bit (typically some combo drives slave on the UDMA * bus) after a hard reset. Since we hard reset all drives on * KeyLargo ATA66, we have to keep that delay around. I may end * up not hard resetting anymore on these and keep the delay only * for older interfaces instead (we have to reset when coming * from MacOS...) --BenH.  */#define IDE_WAKEUP_DELAY	(1*HZ) static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *); #define PMAC_IDE_REG(x) \	((void __iomem *)((drive)->hwif->io_ports.data_addr + (x))) /* * Apply the timings of the proper unit (master/slave) to the shared * timing register when selecting that unit. This version is for * ASICs with a single timing register */static void pmac_ide_apply_timings(ide_drive_t *drive){	ide_hwif_t *hwif = drive->hwif;	pmac_ide_hwif_t *pmif =		(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 	if (drive->dn & 1)		writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));	else		writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));	(void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));} /* * Apply the timings of the proper unit (master/slave) to the shared * timing register when selecting that unit. This version is for * ASICs with a dual timing register (Kauai) */static void pmac_ide_kauai_apply_timings(ide_drive_t *drive){	ide_hwif_t *hwif = drive->hwif;	pmac_ide_hwif_t *pmif =		(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 	if (drive->dn & 1) {		writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));		writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));	} else {		writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));		writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));	}	(void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));} /* * Force an update of controller timing values for a given drive */static voidpmac_ide_do_update_timings(ide_drive_t *drive){	ide_hwif_t *hwif = drive->hwif;	pmac_ide_hwif_t *pmif =		(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent); 	if (pmif->kind == controller_sh_ata6 ||	    pmif->kind == controller_un_ata6 ||	    pmif->kind == controller_k2_ata6)		pmac_ide_kauai_apply_timings(drive);	else		pmac_ide_apply_timings(drive);} static void pmac_dev_select(ide_drive_t *drive){	pmac_ide_apply_timings(drive); 	writeb(drive->select | ATA_DEVICE_OBS,	       (void __iomem *)drive->hwif->io_ports.device_addr);} static void pmac_kauai_dev_select(ide_drive_t *drive){	pmac_ide_kauai_apply_timings(drive); 	writeb(drive->select | ATA_DEVICE_OBS,	       (void __iomem *)drive->hwif->io_ports.device_addr);} static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd){	writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);	(void)readl((void __iomem *)(hwif->io_ports.data_addr				     + IDE_TIMING_CONFIG));} static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl){	writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);	(void)readl((void __iomem *)(hwif->io_ports.data_addr				     + IDE_TIMING_CONFIG));} /* * Old tuning functions (called on hdparm -p), sets up drive PIO timings */

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