/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 *//****************************************************************************** * * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec) * * Copyright (C) 2000 - 2020, Intel Corp. * *****************************************************************************/ #ifndef __ACTBL2_H__#define __ACTBL2_H__ /******************************************************************************* * * Additional ACPI Tables (2) * * These tables are not consumed directly by the ACPICA subsystem, but are * included here to support device drivers and the AML disassembler. * ******************************************************************************/ /* * Values for description table header signatures for tables defined in this * file. Useful because they make it more difficult to inadvertently type in * the wrong signature. */#define ACPI_SIG_IORT           "IORT"	/* IO Remapping Table */#define ACPI_SIG_IVRS           "IVRS"	/* I/O Virtualization Reporting Structure */#define ACPI_SIG_LPIT           "LPIT"	/* Low Power Idle Table */#define ACPI_SIG_MADT           "APIC"	/* Multiple APIC Description Table */#define ACPI_SIG_MCFG           "MCFG"	/* PCI Memory Mapped Configuration table */#define ACPI_SIG_MCHI           "MCHI"	/* Management Controller Host Interface table */#define ACPI_SIG_MPST           "MPST"	/* Memory Power State Table */#define ACPI_SIG_MSCT           "MSCT"	/* Maximum System Characteristics Table */#define ACPI_SIG_MSDM           "MSDM"	/* Microsoft Data Management Table */#define ACPI_SIG_MTMR           "MTMR"	/* MID Timer table */#define ACPI_SIG_NFIT           "NFIT"	/* NVDIMM Firmware Interface Table */#define ACPI_SIG_PCCT           "PCCT"	/* Platform Communications Channel Table */#define ACPI_SIG_PDTT           "PDTT"	/* Platform Debug Trigger Table */#define ACPI_SIG_PMTT           "PMTT"	/* Platform Memory Topology Table */#define ACPI_SIG_PPTT           "PPTT"	/* Processor Properties Topology Table */#define ACPI_SIG_RASF           "RASF"	/* RAS Feature table */#define ACPI_SIG_SBST           "SBST"	/* Smart Battery Specification Table */#define ACPI_SIG_SDEI           "SDEI"	/* Software Delegated Exception Interface Table */#define ACPI_SIG_SDEV           "SDEV"	/* Secure Devices table */#define ACPI_SIG_NHLT           "NHLT"	/* Non-HDAudio Link Table */ /* * All tables must be byte-packed to match the ACPI specification, since * the tables are provided by the system BIOS. */#pragma pack(1) /* * Note: C bitfields are not used for this reason: * * "Bitfields are great and easy to read, but unfortunately the C language * does not specify the layout of bitfields in memory, which means they are * essentially useless for dealing with packed data in on-disk formats or * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me, * this decision was a design error in C. Ritchie could have picked an order * and stuck with it." Norman Ramsey. * See http://stackoverflow.com/a/1053662/41661 */ /******************************************************************************* * * IORT - IO Remapping Table * * Conforms to "IO Remapping Table System Software on ARM Platforms", * Document number: ARM DEN 0049D, March 2018 * ******************************************************************************/ struct acpi_table_iort {	struct acpi_table_header header;	u32 node_count;	u32 node_offset;	u32 reserved;}; /* * IORT subtables */struct acpi_iort_node {	u8 type;	u16 length;	u8 revision;	u32 reserved;	u32 mapping_count;	u32 mapping_offset;	char node_data[1];}; /* Values for subtable Type above */ enum acpi_iort_node_type {	ACPI_IORT_NODE_ITS_GROUP = 0x00,	ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,	ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,	ACPI_IORT_NODE_SMMU = 0x03,	ACPI_IORT_NODE_SMMU_V3 = 0x04,	ACPI_IORT_NODE_PMCG = 0x05}; struct acpi_iort_id_mapping {	u32 input_base;		/* Lowest value in input range */	u32 id_count;		/* Number of IDs */	u32 output_base;	/* Lowest value in output range */	u32 output_reference;	/* A reference to the output node */	u32 flags;}; /* Masks for Flags field above for IORT subtable */ #define ACPI_IORT_ID_SINGLE_MAPPING (1) struct acpi_iort_memory_access {	u32 cache_coherency;	u8 hints;	u16 reserved;	u8 memory_flags;}; /* Values for cache_coherency field above */ #define ACPI_IORT_NODE_COHERENT         0x00000001	/* The device node is fully coherent */#define ACPI_IORT_NODE_NOT_COHERENT     0x00000000	/* The device node is not coherent */ /* Masks for Hints field above */ #define ACPI_IORT_HT_TRANSIENT          (1)#define ACPI_IORT_HT_WRITE              (1<<1)#define ACPI_IORT_HT_READ               (1<<2)#define ACPI_IORT_HT_OVERRIDE           (1<<3) /* Masks for memory_flags field above */ #define ACPI_IORT_MF_COHERENCY          (1)#define ACPI_IORT_MF_ATTRIBUTES         (1<<1) /* * IORT node specific subtables */struct acpi_iort_its_group {	u32 its_count;	u32 identifiers[1];	/* GIC ITS identifier array */}; struct acpi_iort_named_component {	u32 node_flags;	u64 memory_properties;	/* Memory access properties */	u8 memory_address_limit;	/* Memory address size limit */	char device_name[1];	/* Path of namespace object */}; /* Masks for Flags field above */ #define ACPI_IORT_NC_STALL_SUPPORTED    (1)#define ACPI_IORT_NC_PASID_BITS         (31<<1) struct acpi_iort_root_complex {	u64 memory_properties;	/* Memory access properties */	u32 ats_attribute;	u32 pci_segment_number;	u8 memory_address_limit;	/* Memory address size limit */	u8 reserved[3];		/* Reserved, must be zero */}; /* Values for ats_attribute field above */ #define ACPI_IORT_ATS_SUPPORTED         0x00000001	/* The root complex supports ATS */#define ACPI_IORT_ATS_UNSUPPORTED       0x00000000	/* The root complex doesn't support ATS */ struct acpi_iort_smmu {	u64 base_address;	/* SMMU base address */	u64 span;		/* Length of memory range */	u32 model;	u32 flags;	u32 global_interrupt_offset;	u32 context_interrupt_count;	u32 context_interrupt_offset;	u32 pmu_interrupt_count;	u32 pmu_interrupt_offset;	u64 interrupts[1];	/* Interrupt array */}; /* Values for Model field above */ #define ACPI_IORT_SMMU_V1               0x00000000	/* Generic SMMUv1 */#define ACPI_IORT_SMMU_V2               0x00000001	/* Generic SMMUv2 */#define ACPI_IORT_SMMU_CORELINK_MMU400  0x00000002	/* ARM Corelink MMU-400 */#define ACPI_IORT_SMMU_CORELINK_MMU500  0x00000003	/* ARM Corelink MMU-500 */#define ACPI_IORT_SMMU_CORELINK_MMU401  0x00000004	/* ARM Corelink MMU-401 */#define ACPI_IORT_SMMU_CAVIUM_THUNDERX  0x00000005	/* Cavium thunder_x SMMUv2 */ /* Masks for Flags field above */ #define ACPI_IORT_SMMU_DVM_SUPPORTED    (1)#define ACPI_IORT_SMMU_COHERENT_WALK    (1<<1) /* Global interrupt format */ struct acpi_iort_smmu_gsi {	u32 nsg_irpt;	u32 nsg_irpt_flags;	u32 nsg_cfg_irpt;	u32 nsg_cfg_irpt_flags;}; struct acpi_iort_smmu_v3 {	u64 base_address;	/* SMMUv3 base address */	u32 flags;	u32 reserved;	u64 vatos_address;	u32 model;	u32 event_gsiv;	u32 pri_gsiv;	u32 gerr_gsiv;	u32 sync_gsiv;	u32 pxm;	u32 id_mapping_index;}; /* Values for Model field above */ #define ACPI_IORT_SMMU_V3_GENERIC           0x00000000	/* Generic SMMUv3 */#define ACPI_IORT_SMMU_V3_HISILICON_HI161X  0x00000001	/* hi_silicon Hi161x SMMUv3 */#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX     0x00000002	/* Cavium CN99xx SMMUv3 */ /* Masks for Flags field above */ #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE   (1)#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE     (3<<1)#define ACPI_IORT_SMMU_V3_PXM_VALID         (1<<3) struct acpi_iort_pmcg {	u64 page0_base_address;	u32 overflow_gsiv;	u32 node_reference;	u64 page1_base_address;}; /******************************************************************************* * * IVRS - I/O Virtualization Reporting Structure *        Version 1 * * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification", * Revision 1.26, February 2009. * ******************************************************************************/ struct acpi_table_ivrs {	struct acpi_table_header header;	/* Common ACPI table header */	u32 info;		/* Common virtualization info */	u64 reserved;}; /* Values for Info field above */ #define ACPI_IVRS_PHYSICAL_SIZE     0x00007F00	/* 7 bits, physical address size */#define ACPI_IVRS_VIRTUAL_SIZE      0x003F8000	/* 7 bits, virtual address size */#define ACPI_IVRS_ATS_RESERVED      0x00400000	/* ATS address translation range reserved */ /* IVRS subtable header */ struct acpi_ivrs_header {	u8 type;		/* Subtable type */	u8 flags;	u16 length;		/* Subtable length */	u16 device_id;		/* ID of IOMMU */}; /* Values for subtable Type above */ enum acpi_ivrs_type {	ACPI_IVRS_TYPE_HARDWARE1 = 0x10,	ACPI_IVRS_TYPE_HARDWARE2 = 0x11,	ACPI_IVRS_TYPE_MEMORY1 = 0x20,	ACPI_IVRS_TYPE_MEMORY2 = 0x21,	ACPI_IVRS_TYPE_MEMORY3 = 0x22}; /* Masks for Flags field above for IVHD subtable */ #define ACPI_IVHD_TT_ENABLE         (1)#define ACPI_IVHD_PASS_PW           (1<<1)#define ACPI_IVHD_RES_PASS_PW       (1<<2)#define ACPI_IVHD_ISOC              (1<<3)#define ACPI_IVHD_IOTLB             (1<<4) /* Masks for Flags field above for IVMD subtable */ #define ACPI_IVMD_UNITY             (1)#define ACPI_IVMD_READ              (1<<1)#define ACPI_IVMD_WRITE             (1<<2)#define ACPI_IVMD_EXCLUSION_RANGE   (1<<3) /* * IVRS subtables, correspond to Type in struct acpi_ivrs_header */ /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ struct acpi_ivrs_hardware_10 {	struct acpi_ivrs_header header;	u16 capability_offset;	/* Offset for IOMMU control fields */	u64 base_address;	/* IOMMU control registers */	u16 pci_segment_group;	u16 info;		/* MSI number and unit ID */	u32 feature_reporting;}; /* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */ struct acpi_ivrs_hardware_11 {	struct acpi_ivrs_header header;	u16 capability_offset;	/* Offset for IOMMU control fields */	u64 base_address;	/* IOMMU control registers */	u16 pci_segment_group;	u16 info;		/* MSI number and unit ID */	u32 attributes;	u64 efr_register_image;	u64 reserved;}; /* Masks for Info field above */ #define ACPI_IVHD_MSI_NUMBER_MASK   0x001F	/* 5 bits, MSI message number */#define ACPI_IVHD_UNIT_ID_MASK      0x1F00	/* 5 bits, unit_ID */ /* * Device Entries for IVHD subtable, appear after struct acpi_ivrs_hardware structure. * Upper two bits of the Type field are the (encoded) length of the structure. * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries * are reserved for future use but not defined. */struct acpi_ivrs_de_header {	u8 type;	u16 id;	u8 data_setting;}; /* Length of device entry is in the top two bits of Type field above */ #define ACPI_IVHD_ENTRY_LENGTH      0xC0 /* Values for device entry Type field above */ enum acpi_ivrs_device_entry_type {	/* 4-byte device entries, all use struct acpi_ivrs_device4 */ 	ACPI_IVRS_TYPE_PAD4 = 0,	ACPI_IVRS_TYPE_ALL = 1,	ACPI_IVRS_TYPE_SELECT = 2,	ACPI_IVRS_TYPE_START = 3,	ACPI_IVRS_TYPE_END = 4, 	/* 8-byte device entries */ 	ACPI_IVRS_TYPE_PAD8 = 64,	ACPI_IVRS_TYPE_NOT_USED = 65,	ACPI_IVRS_TYPE_ALIAS_SELECT = 66,	/* Uses struct acpi_ivrs_device8a */	ACPI_IVRS_TYPE_ALIAS_START = 67,	/* Uses struct acpi_ivrs_device8a */	ACPI_IVRS_TYPE_EXT_SELECT = 70,	/* Uses struct acpi_ivrs_device8b */	ACPI_IVRS_TYPE_EXT_START = 71,	/* Uses struct acpi_ivrs_device8b */	ACPI_IVRS_TYPE_SPECIAL = 72	/* Uses struct acpi_ivrs_device8c */}; /* Values for Data field above */ #define ACPI_IVHD_INIT_PASS         (1)#define ACPI_IVHD_EINT_PASS         (1<<1)#define ACPI_IVHD_NMI_PASS          (1<<2)#define ACPI_IVHD_SYSTEM_MGMT       (3<<4)#define ACPI_IVHD_LINT0_PASS        (1<<6)#define ACPI_IVHD_LINT1_PASS        (1<<7) /* Types 0-4: 4-byte device entry */ struct acpi_ivrs_device4 {	struct acpi_ivrs_de_header header;}; /* Types 66-67: 8-byte device entry */ struct acpi_ivrs_device8a {	struct acpi_ivrs_de_header header;	u8 reserved1;	u16 used_id;	u8 reserved2;}; /* Types 70-71: 8-byte device entry */ struct acpi_ivrs_device8b {	struct acpi_ivrs_de_header header;	u32 extended_data;}; /* Values for extended_data above */ #define ACPI_IVHD_ATS_DISABLED      (1<<31) /* Type 72: 8-byte device entry */ struct acpi_ivrs_device8c {	struct acpi_ivrs_de_header header;	u8 handle;	u16 used_id;	u8 variety;}; /* Values for Variety field above */ #define ACPI_IVHD_IOAPIC            1#define ACPI_IVHD_HPET              2 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */ struct acpi_ivrs_memory {	struct acpi_ivrs_header header;	u16 aux_data;	u64 reserved;	u64 start_address;	u64 memory_length;}; /******************************************************************************* * * LPIT - Low Power Idle Table * * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014. * ******************************************************************************/ struct acpi_table_lpit {	struct acpi_table_header header;	/* Common ACPI table header */}; /* LPIT subtable header */ struct acpi_lpit_header {	u32 type;		/* Subtable type */	u32 length;		/* Subtable length */	u16 unique_id;	u16 reserved;	u32 flags;}; /* Values for subtable Type above */ enum acpi_lpit_type {	ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,	ACPI_LPIT_TYPE_RESERVED = 0x01	/* 1 and above are reserved */}; /* Masks for Flags field above  */ #define ACPI_LPIT_STATE_DISABLED    (1)#define ACPI_LPIT_NO_COUNTER        (1<<1) /* * LPIT subtables, correspond to Type in struct acpi_lpit_header */ /* 0x00: Native C-state instruction based LPI structure */ struct acpi_lpit_native {	struct acpi_lpit_header header;	struct acpi_generic_address entry_trigger;	u32 residency;	u32 latency;	struct acpi_generic_address residency_counter;	u64 counter_frequency;}; /******************************************************************************* * * MADT - Multiple APIC Description Table *        Version 3 * ******************************************************************************/ struct acpi_table_madt {	struct acpi_table_header header;	/* Common ACPI table header */	u32 address;		/* Physical address of local APIC */	u32 flags;}; /* Masks for Flags field above */ #define ACPI_MADT_PCAT_COMPAT       (1)	/* 00: System also has dual 8259s */ /* Values for PCATCompat flag */ #define ACPI_MADT_DUAL_PIC          1#define ACPI_MADT_MULTIPLE_APIC     0 

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