/* SPDX-License-Identifier: GPL-2.0 *//* *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> */#ifndef __LINUX_CLK_PROVIDER_H#define __LINUX_CLK_PROVIDER_H #include <linux/of.h>#include <linux/of_clk.h> /* * flags used across common struct clk.  these flags should only affect the * top-level framework.  custom flags for dealing with hardware specifics * belong in struct clk_foo * * Please update clk_flags[] in drivers/clk/clk.c when making changes here! */#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */				/* unused */				/* unused */#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever *//* parents need enable during gate/ungate, set rate and re-parent */#define CLK_OPS_PARENT_ENABLE	BIT(12)/* duty cycle call may be forwarded to the parent clock */#define CLK_DUTY_CYCLE_PARENT	BIT(13) struct clk;struct clk_hw;struct clk_core;struct dentry; /** * struct clk_rate_request - Structure encoding the clk constraints that * a clock user might require. * * @rate:		Requested clock rate. This field will be adjusted by *			clock drivers according to hardware capabilities. * @min_rate:		Minimum rate imposed by clk users. * @max_rate:		Maximum rate imposed by clk users. * @best_parent_rate:	The best parent rate a parent can provide to fulfill the *			requested constraints. * @best_parent_hw:	The most appropriate parent clock that fulfills the *			requested constraints. * */struct clk_rate_request {	unsigned long rate;	unsigned long min_rate;	unsigned long max_rate;	unsigned long best_parent_rate;	struct clk_hw *best_parent_hw;}; /** * struct clk_duty - Struture encoding the duty cycle ratio of a clock * * @num:	Numerator of the duty cycle ratio * @den:	Denominator of the duty cycle ratio */struct clk_duty {	unsigned int num;	unsigned int den;}; /** * struct clk_ops -  Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * * @prepare:	Prepare the clock for enabling. This must not return until *		the clock is fully prepared, and it's safe to call clk_enable. *		This callback is intended to allow clock implementations to *		do any initialisation that may sleep. Called with *		prepare_lock held. * * @unprepare:	Release the clock from its prepared state. This will typically *		undo any work done in the @prepare callback. Called with *		prepare_lock held. * * @is_prepared: Queries the hardware to determine if the clock is prepared. *		This function is allowed to sleep. Optional, if this op is not *		set then the prepare count will be used. * * @unprepare_unused: Unprepare the clock atomically.  Only called from *		clk_disable_unused for prepare clocks with special needs. *		Called with prepare mutex held. This function may sleep. * * @enable:	Enable the clock atomically. This must not return until the *		clock is generating a valid clock signal, usable by consumer *		devices. Called with enable_lock held. This function must not *		sleep. * * @disable:	Disable the clock atomically. Called with enable_lock held. *		This function must not sleep. * * @is_enabled:	Queries the hardware to determine if the clock is enabled. *		This function must not sleep. Optional, if this op is not *		set then the enable count will be used. * * @disable_unused: Disable the clock atomically.  Only called from *		clk_disable_unused for gate clocks with special needs. *		Called with enable_lock held.  This function must not *		sleep. * * @save_context: Save the context of the clock in prepration for poweroff. * * @restore_context: Restore the context of the clock after a restoration *		of power. * * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The *		parent rate is an input parameter.  It is up to the caller to *		ensure that the prepare_mutex is held across this call. *		Returns the calculated rate.  Optional, but recommended - if *		this op is not set then clock rate will be initialized to 0. * * @round_rate:	Given a target rate as input, returns the closest rate actually *		supported by the clock. The parent rate is an input/output *		parameter. * * @determine_rate: Given a target rate as input, returns the closest rate *		actually supported by the clock, and optionally the parent clock *		that should be used to provide the clock rate. * * @set_parent:	Change the input source of this clock; for clocks with multiple *		possible parents specify a new parent by passing in the index *		as a u8 corresponding to the parent in either the .parent_names *		or .parents arrays.  This function in affect translates an *		array index into the value programmed into the hardware. *		Returns 0 on success, -EERROR otherwise. * * @get_parent:	Queries the hardware to determine the parent of a clock.  The *		return value is a u8 which specifies the index corresponding to *		the parent clock.  This index can be applied to either the *		.parent_names or .parents arrays.  In short, this function *		translates the parent value read from hardware into an array *		index.  Currently only called when the clock is initialized by *		__clk_init.  This callback is mandatory for clocks with *		multiple parents.  It is optional (and unnecessary) for clocks *		with 0 or 1 parents. * * @set_rate:	Change the rate of this clock. The requested rate is specified *		by the second argument, which should typically be the return *		of .round_rate call.  The third argument gives the parent rate *		which is likely helpful for most .set_rate implementation. *		Returns 0 on success, -EERROR otherwise. * * @set_rate_and_parent: Change the rate and the parent of this clock. The *		requested rate is specified by the second argument, which *		should typically be the return of .round_rate call.  The *		third argument gives the parent rate which is likely helpful *		for most .set_rate_and_parent implementation. The fourth *		argument gives the parent index. This callback is optional (and *		unnecessary) for clocks with 0 or 1 parents as well as *		for clocks that can tolerate switching the rate and the parent *		separately via calls to .set_parent and .set_rate. *		Returns 0 on success, -EERROR otherwise. * * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy *		is expressed in ppb (parts per billion). The parent accuracy is *		an input parameter. *		Returns the calculated accuracy.  Optional - if	this op is not *		set then clock accuracy will be initialized to parent accuracy *		or 0 (perfect clock) if clock has no parent. * * @get_phase:	Queries the hardware to get the current phase of a clock. *		Returned values are 0-359 degrees on success, negative *		error codes on failure. * * @set_phase:	Shift the phase this clock signal in degrees specified *		by the second argument. Valid values for degrees are *		0-359. Return 0 on success, otherwise -EERROR. * * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio *              of a clock. Returned values denominator cannot be 0 and must be *              superior or equal to the numerator. * * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by *              the numerator (2nd argurment) and denominator (3rd  argument). *              Argument must be a valid ratio (denominator > 0 *              and >= numerator) Return 0 on success, otherwise -EERROR. * * @init:	Perform platform-specific initialization magic. *		This is not used by any of the basic clock types. *		This callback exist for HW which needs to perform some *		initialisation magic for CCF to get an accurate view of the *		clock. It may also be used dynamic resource allocation is *		required. It shall not used to deal with clock parameters, *		such as rate or parents. *		Returns 0 on success, -EERROR otherwise. * * @terminate:  Free any resource allocated by init. * * @debug_init:	Set up type-specific debugfs entries for this clock.  This *		is called once, after the debugfs directory entry for this *		clock has been created.  The dentry pointer representing that *		directory is provided as an argument.  Called with *		prepare_lock held.  Returns 0 on success, -EERROR otherwise. * * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts.  If enabling a clock requires code that might sleep, * this must be done in clk_prepare.  Clock enable code that will never be * called in a sleepable context may be implemented in clk_enable. * * Typically, drivers will call clk_prepare when a clock may be needed later * (eg. when a device is opened), and clk_enable when the clock is actually * required (eg. from an interrupt). Note that clk_prepare MUST have been * called before clk_enable. */struct clk_ops {	int		(*prepare)(struct clk_hw *hw);	void		(*unprepare)(struct clk_hw *hw);	int		(*is_prepared)(struct clk_hw *hw);	void		(*unprepare_unused)(struct clk_hw *hw);	int		(*enable)(struct clk_hw *hw);	void		(*disable)(struct clk_hw *hw);	int		(*is_enabled)(struct clk_hw *hw);	void		(*disable_unused)(struct clk_hw *hw);	int		(*save_context)(struct clk_hw *hw);	void		(*restore_context)(struct clk_hw *hw);	unsigned long	(*recalc_rate)(struct clk_hw *hw,					unsigned long parent_rate);	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,					unsigned long *parent_rate);	int		(*determine_rate)(struct clk_hw *hw,					  struct clk_rate_request *req);	int		(*set_parent)(struct clk_hw *hw, u8 index);	u8		(*get_parent)(struct clk_hw *hw);	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,				    unsigned long parent_rate);	int		(*set_rate_and_parent)(struct clk_hw *hw,				    unsigned long rate,				    unsigned long parent_rate, u8 index);	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,					   unsigned long parent_accuracy);	int		(*get_phase)(struct clk_hw *hw);	int		(*set_phase)(struct clk_hw *hw, int degrees);	int		(*get_duty_cycle)(struct clk_hw *hw,					  struct clk_duty *duty);	int		(*set_duty_cycle)(struct clk_hw *hw,					  struct clk_duty *duty);	int		(*init)(struct clk_hw *hw);	void		(*terminate)(struct clk_hw *hw);	void		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);}; /** * struct clk_parent_data - clk parent information * @hw: parent clk_hw pointer (used for clk providers with internal clks) * @fw_name: parent name local to provider registering clk * @name: globally unique parent name (used as a fallback) * @index: parent index local to provider registering clk (if @fw_name absent) */struct clk_parent_data {	const struct clk_hw	*hw;	const char		*fw_name;	const char		*name;	int			index;}; /** * struct clk_init_data - holds init data that's common to all clocks and is * shared between the clock provider and the common clock framework. * * @name: clock name * @ops: operations this clock supports * @parent_names: array of string names for all possible parents * @parent_data: array of parent data for all possible parents (when some *               parents are external to the clk controller) * @parent_hws: array of pointers to all possible parents (when all parents *              are internal to the clk controller) * @num_parents: number of possible parents * @flags: framework-level hints and quirks */struct clk_init_data {	const char		*name;	const struct clk_ops	*ops;	/* Only one of the following three should be assigned */	const char		* const *parent_names;	const struct clk_parent_data	*parent_data;	const struct clk_hw		**parent_hws;	u8			num_parents;	unsigned long		flags;}; /** * struct clk_hw - handle for traversing from a struct clk to its corresponding * hardware-specific structure.  struct clk_hw should be declared within struct * clk_foo and then referenced by the struct clk instance that uses struct * clk_foo's clk_ops * * @core: pointer to the struct clk_core instance that points back to this * struct clk_hw instance * * @clk: pointer to the per-user struct clk instance that can be used to call * into the clk API * * @init: pointer to struct clk_init_data that contains the init data shared * with the common clock framework. This pointer will be set to NULL once * a clk_register() variant is called on this clk_hw pointer. */struct clk_hw {	struct clk_core *core;	struct clk *clk;	const struct clk_init_data *init;}; /* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw:		handle between common and hardware-specific interfaces * @fixed_rate:	constant frequency of clock * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion) * @flags:	hardware specific flags * * Flags: * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk *                                    instead of what's set in @fixed_accuracy. */struct clk_fixed_rate {	struct		clk_hw hw;	unsigned long	fixed_rate;	unsigned long	fixed_accuracy;	unsigned long	flags;}; #define CLK_FIXED_RATE_PARENT_ACCURACY		BIT(0) extern const struct clk_ops clk_fixed_rate_ops;struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,		struct device_node *np, const char *name,		const char *parent_name, const struct clk_hw *parent_hw,		const struct clk_parent_data *parent_data, unsigned long flags,		unsigned long fixed_rate, unsigned long fixed_accuracy,		unsigned long clk_fixed_flags);struct clk *clk_register_fixed_rate(struct device *dev, const char *name,		const char *parent_name, unsigned long flags,		unsigned long fixed_rate);/** * clk_hw_register_fixed_rate - register fixed-rate clock with the clock * framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \				     NULL, (flags), (fixed_rate), 0, 0)/** * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags,     \					     fixed_rate)		      \	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \				     NULL, (flags), (fixed_rate), 0, 0)/** * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_data: parent clk data * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate */#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags,   \					     fixed_rate)		      \	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \				     (parent_data), (flags), (fixed_rate), 0, \				     0)/** * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with * the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,      \						 flags, fixed_rate,	      \						 fixed_accuracy)	      \	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name),      \				     NULL, NULL, (flags), (fixed_rate),       \				     (fixed_accuracy), 0)/** * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate * clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_hw: pointer to parent clk * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name,	      \		parent_hw, flags, fixed_rate, fixed_accuracy)		      \	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw)   \				     NULL, NULL, (flags), (fixed_rate),	      \				     (fixed_accuracy), 0)/** * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate * clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock * @parent_name: name of clock's parent * @flags: framework-specific flags * @fixed_rate: non-adjustable clock rate * @fixed_accuracy: non-adjustable clock accuracy */#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name,	      \		parent_data, flags, fixed_rate, fixed_accuracy)		      \	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \				     (parent_data), NULL, (flags),	      \				     (fixed_rate), (fixed_accuracy), 0) void clk_unregister_fixed_rate(struct clk *clk);void clk_hw_unregister_fixed_rate(struct clk_hw *hw); void of_fixed_clk_setup(struct device_node *np); /** * struct clk_gate - gating clock * * @hw:		handle between common and hardware-specific interfaces * @reg:	register controlling gate * @bit_idx:	single bit controlling gate * @flags:	hardware-specific flags * @lock:	register lock * * Clock which can gate its output.  Implements .enable & .disable * * Flags: * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to *	enable the clock.  Setting this flag does the opposite: setting the bit *	disable the clock and clearing it enables the clock * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit *	of this register, and mask of gate bits are in higher 16-bit of this *	register.  While setting the gate bits, higher 16-bit should also be *	updated to indicate changing gate bits. * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for *	the gate register.  Setting this flag makes the register accesses big *	endian. */struct clk_gate {	struct clk_hw hw;	void __iomem	*reg;	u8		bit_idx;	u8		flags;	spinlock_t	*lock;}; #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) #define CLK_GATE_SET_TO_DISABLE		BIT(0)#define CLK_GATE_HIWORD_MASK		BIT(1)#define CLK_GATE_BIG_ENDIAN		BIT(2) extern const struct clk_ops clk_gate_ops;struct clk_hw *__clk_hw_register_gate(struct device *dev,		struct device_node *np, const char *name,		const char *parent_name, const struct clk_hw *parent_hw,		const struct clk_parent_data *parent_data,		unsigned long flags,		void __iomem *reg, u8 bit_idx,		u8 clk_gate_flags, spinlock_t *lock);struct clk *clk_register_gate(struct device *dev, const char *name,		const char *parent_name, unsigned long flags,		void __iomem *reg, u8 bit_idx,		u8 clk_gate_flags, spinlock_t *lock);/** * clk_hw_register_gate - register a gate clock with the clock framework * @dev: device that is registering this clock * @name: name of this clock

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