#ifndef _SPARC64_HYPERVISOR_H#define _SPARC64_HYPERVISOR_H /* Sun4v hypervisor interfaces and defines. * * Hypervisor calls are made via traps to software traps number 0x80 * and above. Registers %o0 to %o5 serve as argument, status, and * return value registers. * * There are two kinds of these traps. First there are the normal * "fast traps" which use software trap 0x80 and encode the function * to invoke by number in register %o5. Argument and return value * handling is as follows: * * ----------------------------------------------- * | %o5 | function number | undefined | * | %o0 | argument 0 | return status | * | %o1 | argument 1 | return value 1 | * | %o2 | argument 2 | return value 2 | * | %o3 | argument 3 | return value 3 | * | %o4 | argument 4 | return value 4 | * ----------------------------------------------- * * The second type are "hyper-fast traps" which encode the function * number in the software trap number itself. So these use trap * numbers > 0x80. The register usage for hyper-fast traps is as * follows: * * ----------------------------------------------- * | %o0 | argument 0 | return status | * | %o1 | argument 1 | return value 1 | * | %o2 | argument 2 | return value 2 | * | %o3 | argument 3 | return value 3 | * | %o4 | argument 4 | return value 4 | * ----------------------------------------------- * * Registers providing explicit arguments to the hypervisor calls * are volatile across the call. Upon return their values are * undefined unless explicitly specified as containing a particular * return value by the specific call. The return status is always * returned in register %o0, zero indicates a successful execution of * the hypervisor call and other values indicate an error status as * defined below. So, for example, if a hyper-fast trap takes * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across * the call and %o3, %o4, and %o5 would be preserved. * * If the hypervisor trap is invalid, or the fast trap function number * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits * of the argument and return values are significant. */ /* Trap numbers. */#define HV_FAST_TRAP 0x80#define HV_MMU_MAP_ADDR_TRAP 0x83#define HV_MMU_UNMAP_ADDR_TRAP 0x84#define HV_TTRACE_ADDENTRY_TRAP 0x85#define HV_CORE_TRAP 0xff /* Error codes. */#define HV_EOK 0 /* Successful return */#define HV_ENOCPU 1 /* Invalid CPU id */#define HV_ENORADDR 2 /* Invalid real address */#define HV_ENOINTR 3 /* Invalid interrupt id */#define HV_EBADPGSZ 4 /* Invalid pagesize encoding */#define HV_EBADTSB 5 /* Invalid TSB description */#define HV_EINVAL 6 /* Invalid argument */#define HV_EBADTRAP 7 /* Invalid function number */#define HV_EBADALIGN 8 /* Invalid address alignment */#define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */#define HV_ENOACCESS 10 /* No access to resource */#define HV_EIO 11 /* I/O error */#define HV_ECPUERROR 12 /* CPU in error state */#define HV_ENOTSUPPORTED 13 /* Function not supported */#define HV_ENOMAP 14 /* No mapping found */#define HV_ETOOMANY 15 /* Too many items specified */ /* mach_exit() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_EXIT * ARG0: exit code * ERRORS: This service does not return. * * Stop all CPUs in the virtual domain and place them into the stopped * state. The 64-bit exit code may be passed to a service entity as * the domain's exit status. On systems without a service entity, the * domain will undergo a reset, and the boot firmware will be * reloaded. * * This function will never return to the guest that invokes it. * * Note: By convention an exit code of zero denotes a successful exit by * the guest code. A non-zero exit code denotes a guest specific * error indication. * */#define HV_FAST_MACH_EXIT 0x00 /* Domain services. */ /* mach_desc() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_DESC * ARG0: buffer * ARG1: length * RET0: status * RET1: length * ERRORS: HV_EBADALIGN Buffer is badly aligned * HV_ENORADDR Buffer is to an illegal real address. * HV_EINVAL Buffer length is too small for complete * machine description. * * Copy the most current machine description into the buffer indicated * by the real address in ARG0. The buffer provided must be 16 byte * aligned. Upon success or HV_EINVAL, this service returns the * actual size of the machine description in the RET1 return value. * * Note: A method of determining the appropriate buffer size for the * machine description is to first call this service with a buffer * length of 0 bytes. */#define HV_FAST_MACH_DESC 0x01 /* mach_exit() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_SIR * ERRORS: This service does not return. * * Perform a software initiated reset of the virtual machine domain. * All CPUs are captured as soon as possible, all hardware devices are * returned to the entry default state, and the domain is restarted at * the SIR (trap type 0x04) real trap table (RTBA) entry point on one * of the CPUs. The single CPU restarted is selected as determined by * platform specific policy. Memory is preserved across this * operation. */#define HV_FAST_MACH_SIR 0x02 /* mach_set_soft_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE * ARG0: software state * ARG1: software state description pointer * RET0: status * ERRORS: EINVAL software state not valid or software state * description is not NULL terminated * ENORADDR software state description pointer is not a * valid real address * EBADALIGNED software state description is not correctly * aligned * * This allows the guest to report it's soft state to the hypervisor. There * are two primary components to this state. The first part states whether * the guest software is running or not. The second containts optional * details specific to the software. * * The software state argument is defined below in HV_SOFT_STATE_*, and * indicates whether the guest is operating normally or in a transitional * state. * * The software state description argument is a real address of a data buffer * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL * terminated 7-bit ASCII string of up to 31 characters not including the * NULL termination. */#define HV_FAST_MACH_SET_SOFT_STATE 0x03#define HV_SOFT_STATE_NORMAL 0x01#define HV_SOFT_STATE_TRANSITION 0x02 /* mach_get_soft_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE * ARG0: software state description pointer * RET0: status * RET1: software state * ERRORS: ENORADDR software state description pointer is not a * valid real address * EBADALIGNED software state description is not correctly * aligned * * Retrieve the current value of the guest's software state. The rules * for the software state pointer are the same as for mach_set_soft_state() * above. */#define HV_FAST_MACH_GET_SOFT_STATE 0x04 /* CPU services. * * CPUs represent devices that can execute software threads. A single * chip that contains multiple cores or strands is represented as * multiple CPUs with unique CPU identifiers. CPUs are exported to * OBP via the machine description (and to the OS via the OBP device * tree). CPUs are always in one of three states: stopped, running, * or error. * * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a * CPU within a logical domain. Operations that are to be performed * on multiple CPUs specify them via a CPU list. A CPU list is an * array in real memory, of which each 16-bit word is a CPU ID. CPU * lists are passed through the API as two arguments. The first is * the number of entries (16-bit words) in the CPU list, and the * second is the (real address) pointer to the CPU ID list. */ /* cpu_start() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_START * ARG0: CPU ID * ARG1: PC * ARG1: RTBA * ARG1: target ARG0 * RET0: status * ERRORS: ENOCPU Invalid CPU ID * EINVAL Target CPU ID is not in the stopped state * ENORADDR Invalid PC or RTBA real address * EBADALIGN Unaligned PC or unaligned RTBA * EWOULDBLOCK Starting resources are not available * * Start CPU with given CPU ID with PC in %pc and with a real trap * base address value of RTBA. The indicated CPU must be in the * stopped state. The supplied RTBA must be aligned on a 256 byte * boundary. On successful completion, the specified CPU will be in * the running state and will be supplied with "target ARG0" in %o0 * and RTBA in %tba. */#define HV_FAST_CPU_START 0x10 /* cpu_stop() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_STOP * ARG0: CPU ID * RET0: status * ERRORS: ENOCPU Invalid CPU ID * EINVAL Target CPU ID is the current cpu * EINVAL Target CPU ID is not in the running state * EWOULDBLOCK Stopping resources are not available * ENOTSUPPORTED Not supported on this platform * * The specified CPU is stopped. The indicated CPU must be in the * running state. On completion, it will be in the stopped state. It * is not legal to stop the current CPU. * * Note: As this service cannot be used to stop the current cpu, this service * may not be used to stop the last running CPU in a domain. To stop * and exit a running domain, a guest must use the mach_exit() service. */#define HV_FAST_CPU_STOP 0x11 /* cpu_yield() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_YIELD * RET0: status * ERRORS: No possible error. * * Suspend execution on the current CPU. Execution will resume when * an interrupt (device, %stick_compare, or cross-call) is targeted to * the CPU. On some CPUs, this API may be used by the hypervisor to * save power by disabling hardware strands. */#define HV_FAST_CPU_YIELD 0x12 #ifndef __ASSEMBLY__extern unsigned long sun4v_cpu_yield(void);#endif /* cpu_qconf() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_QCONF * ARG0: queue * ARG1: base real address * ARG2: number of entries * RET0: status * ERRORS: ENORADDR Invalid base real address * EINVAL Invalid queue or number of entries is less * than 2 or too large. * EBADALIGN Base real address is not correctly aligned * for size. * * Configure the given queue to be placed at the given base real * address, with the given number of entries. The number of entries * must be a power of 2. The base real address must be aligned * exactly to match the queue size. Each queue entry is 64 bytes * long, so for example a 32 entry queue must be aligned on a 2048 * byte real address boundary. * * The specified queue is unconfigured if the number of entries is given * as zero. * * For the current version of this API service, the argument queue is defined * as follows: * * queue description * ----- ------------------------- * 0x3c cpu mondo queue * 0x3d device mondo queue * 0x3e resumable error queue * 0x3f non-resumable error queue * * Note: The maximum number of entries for each queue for a specific cpu may * be determined from the machine description. */#define HV_FAST_CPU_QCONF 0x14#define HV_CPU_QUEUE_CPU_MONDO 0x3c#define HV_CPU_QUEUE_DEVICE_MONDO 0x3d#define HV_CPU_QUEUE_RES_ERROR 0x3e#define HV_CPU_QUEUE_NONRES_ERROR 0x3f #ifndef __ASSEMBLY__extern unsigned long sun4v_cpu_qconf(unsigned long type, unsigned long queue_paddr, unsigned long num_queue_entries);#endif /* cpu_qinfo() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_QINFO * ARG0: queue * RET0: status * RET1: base real address * RET1: number of entries * ERRORS: EINVAL Invalid queue * * Return the configuration info for the given queue. The base real * address and number of entries of the defined queue are returned. * The queue argument values are the same as for cpu_qconf() above. * * If the specified queue is a valid queue number, but no queue has * been defined, the number of entries will be set to zero and the * base real address returned is undefined. */#define HV_FAST_CPU_QINFO 0x15 /* cpu_mondo_send() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_MONDO_SEND * ARG0-1: CPU list * ARG2: data real address * RET0: status * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list * is not 2-byte aligned. * ENORADDR Invalid data mondo address, or invalid cpu list * address. * ENOCPU Invalid cpu in CPU list * EWOULDBLOCK Some or all of the listed CPUs did not receive * the mondo * ECPUERROR One or more of the listed CPUs are in error * state, use HV_FAST_CPU_STATE to see which ones * EINVAL CPU list includes caller's CPU ID * * Send a mondo interrupt to the CPUs in the given CPU list with the * 64-bytes at the given data real address. The data must be 64-byte * aligned. The mondo data will be delivered to the cpu_mondo queues * of the recipient CPUs. * * In all cases, error or not, the CPUs in the CPU list to which the * mondo has been successfully delivered will be indicated by having * their entry in CPU list updated with the value 0xffff. */#define HV_FAST_CPU_MONDO_SEND 0x42 #ifndef __ASSEMBLY__extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa);#endif /* cpu_myid() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_MYID * RET0: status * RET1: CPU ID * ERRORS: No errors defined. * * Return the hypervisor ID handle for the current CPU. Use by a * virtual CPU to discover it's own identity. */#define HV_FAST_CPU_MYID 0x16 /* cpu_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_STATE * ARG0: CPU ID * RET0: status * RET1: state * ERRORS: ENOCPU Invalid CPU ID * * Retrieve the current state of the CPU with the given CPU ID. */#define HV_FAST_CPU_STATE 0x17#define HV_CPU_STATE_STOPPED 0x01#define HV_CPU_STATE_RUNNING 0x02#define HV_CPU_STATE_ERROR 0x03 #ifndef __ASSEMBLY__extern long sun4v_cpu_state(unsigned long cpuid);#endif /* cpu_set_rtba() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_SET_RTBA * ARG0: RTBA * RET0: status * RET1: previous RTBA * ERRORS: ENORADDR Invalid RTBA real address * EBADALIGN RTBA is incorrectly aligned for a trap table * * Set the real trap base address of the local cpu to the given RTBA. * The supplied RTBA must be aligned on a 256 byte boundary. Upon * success the previous value of the RTBA is returned in RET1. * * Note: This service does not affect %tba */#define HV_FAST_CPU_SET_RTBA 0x18 /* cpu_set_rtba() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_GET_RTBA * RET0: status * RET1: previous RTBA * ERRORS: No possible error. * * Returns the current value of RTBA in RET1. */#define HV_FAST_CPU_GET_RTBA 0x19 /* MMU services. * * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls. */#ifndef __ASSEMBLY__struct hv_tsb_descr { unsigned short pgsz_idx; unsigned short assoc; unsigned int num_ttes; /* in TTEs */ unsigned int ctx_idx; unsigned int pgsz_mask; unsigned long tsb_base; unsigned long resv;};#endif#define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00#define HV_TSB_DESCR_ASSOC_OFFSET 0x02#define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04#define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08#define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c#define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10#define HV_TSB_DESCR_RESV_OFFSET 0x18 /* Page size bitmask. */#define HV_PGSZ_MASK_8K (1 << 0)#define HV_PGSZ_MASK_64K (1 << 1)#define HV_PGSZ_MASK_512K (1 << 2)#define HV_PGSZ_MASK_4MB (1 << 3)#define HV_PGSZ_MASK_32MB (1 << 4)#define HV_PGSZ_MASK_256MB (1 << 5)#define HV_PGSZ_MASK_2GB (1 << 6)#define HV_PGSZ_MASK_16GB (1 << 7) /* Page size index. The value given in the TSB descriptor must correspond * to the smallest page size specified in the pgsz_mask page size bitmask. */#define HV_PGSZ_IDX_8K 0#define HV_PGSZ_IDX_64K 1#define HV_PGSZ_IDX_512K 2#define HV_PGSZ_IDX_4MB 3#define HV_PGSZ_IDX_32MB 4#define HV_PGSZ_IDX_256MB 5#define HV_PGSZ_IDX_2GB 6#define HV_PGSZ_IDX_16GB 7 /* MMU fault status area. * * MMU related faults have their status and fault address information * placed into a memory region made available by privileged code. Each * virtual processor must make a mmu_fault_area_conf() call to tell the * hypervisor where that processor's fault status should be stored. * * The fault status block is a multiple of 64-bytes and must be aligned * on a 64-byte boundary. */#ifndef __ASSEMBLY__struct hv_fault_status { unsigned long i_fault_type; unsigned long i_fault_addr; unsigned long i_fault_ctx; unsigned long i_reserved[5]; unsigned long d_fault_type; unsigned long d_fault_addr; unsigned long d_fault_ctx; unsigned long d_reserved[5];};#endif#define HV_FAULT_I_TYPE_OFFSET 0x00#define HV_FAULT_I_ADDR_OFFSET 0x08#define HV_FAULT_I_CTX_OFFSET 0x10#define HV_FAULT_D_TYPE_OFFSET 0x40#define HV_FAULT_D_ADDR_OFFSET 0x48#define HV_FAULT_D_CTX_OFFSET 0x50 #define HV_FAULT_TYPE_FAST_MISS 1#define HV_FAULT_TYPE_FAST_PROT 2#define HV_FAULT_TYPE_MMU_MISS 3#define HV_FAULT_TYPE_INV_RA 4Lines 1–500 of 2128. Load more
#ifndef _SPARC64_HYPERVISOR_H #define _SPARC64_HYPERVISOR_H /* Sun4v hypervisor interfaces and defines. * * Hypervisor calls are made via traps to software traps number 0x80 * and above. Registers %o0 to %o5 serve as argument, status, and * return value registers. * * There are two kinds of these traps. First there are the normal * "fast traps" which use software trap 0x80 and encode the function * to invoke by number in register %o5. Argument and return value * handling is as follows: * * ----------------------------------------------- * | %o5 | function number | undefined | * | %o0 | argument 0 | return status | * | %o1 | argument 1 | return value 1 | * | %o2 | argument 2 | return value 2 | * | %o3 | argument 3 | return value 3 | * | %o4 | argument 4 | return value 4 | * ----------------------------------------------- * * The second type are "hyper-fast traps" which encode the function * number in the software trap number itself. So these use trap * numbers > 0x80. The register usage for hyper-fast traps is as * follows: * * ----------------------------------------------- * | %o0 | argument 0 | return status | * | %o1 | argument 1 | return value 1 | * | %o2 | argument 2 | return value 2 | * | %o3 | argument 3 | return value 3 | * | %o4 | argument 4 | return value 4 | * ----------------------------------------------- * * Registers providing explicit arguments to the hypervisor calls * are volatile across the call. Upon return their values are * undefined unless explicitly specified as containing a particular * return value by the specific call. The return status is always * returned in register %o0, zero indicates a successful execution of * the hypervisor call and other values indicate an error status as * defined below. So, for example, if a hyper-fast trap takes * arguments 0, 1, and 2, then %o0, %o1, and %o2 are volatile across * the call and %o3, %o4, and %o5 would be preserved. * * If the hypervisor trap is invalid, or the fast trap function number * is invalid, HV_EBADTRAP will be returned in %o0. Also, all 64-bits * of the argument and return values are significant. */ /* Trap numbers. */ #define HV_FAST_TRAP 0x80 #define HV_MMU_MAP_ADDR_TRAP 0x83 #define HV_MMU_UNMAP_ADDR_TRAP 0x84 #define HV_TTRACE_ADDENTRY_TRAP 0x85 #define HV_CORE_TRAP 0xff /* Error codes. */ #define HV_EOK 0 /* Successful return */ #define HV_ENOCPU 1 /* Invalid CPU id */ #define HV_ENORADDR 2 /* Invalid real address */ #define HV_ENOINTR 3 /* Invalid interrupt id */ #define HV_EBADPGSZ 4 /* Invalid pagesize encoding */ #define HV_EBADTSB 5 /* Invalid TSB description */ #define HV_EINVAL 6 /* Invalid argument */ #define HV_EBADTRAP 7 /* Invalid function number */ #define HV_EBADALIGN 8 /* Invalid address alignment */ #define HV_EWOULDBLOCK 9 /* Cannot complete w/o blocking */ #define HV_ENOACCESS 10 /* No access to resource */ #define HV_EIO 11 /* I/O error */ #define HV_ECPUERROR 12 /* CPU in error state */ #define HV_ENOTSUPPORTED 13 /* Function not supported */ #define HV_ENOMAP 14 /* No mapping found */ #define HV_ETOOMANY 15 /* Too many items specified */ /* mach_exit() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_EXIT * ARG0: exit code * ERRORS: This service does not return. * * Stop all CPUs in the virtual domain and place them into the stopped * state. The 64-bit exit code may be passed to a service entity as * the domain's exit status. On systems without a service entity, the * domain will undergo a reset, and the boot firmware will be * reloaded. * * This function will never return to the guest that invokes it. * * Note: By convention an exit code of zero denotes a successful exit by * the guest code. A non-zero exit code denotes a guest specific * error indication. * */ #define HV_FAST_MACH_EXIT 0x00 /* Domain services. */ /* mach_desc() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_DESC * ARG0: buffer * ARG1: length * RET0: status * RET1: length * ERRORS: HV_EBADALIGN Buffer is badly aligned * HV_ENORADDR Buffer is to an illegal real address. * HV_EINVAL Buffer length is too small for complete * machine description. * * Copy the most current machine description into the buffer indicated * by the real address in ARG0. The buffer provided must be 16 byte * aligned. Upon success or HV_EINVAL, this service returns the * actual size of the machine description in the RET1 return value. * * Note: A method of determining the appropriate buffer size for the * machine description is to first call this service with a buffer * length of 0 bytes. */ #define HV_FAST_MACH_DESC 0x01 /* mach_exit() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_SIR * ERRORS: This service does not return. * * Perform a software initiated reset of the virtual machine domain. * All CPUs are captured as soon as possible, all hardware devices are * returned to the entry default state, and the domain is restarted at * the SIR (trap type 0x04) real trap table (RTBA) entry point on one * of the CPUs. The single CPU restarted is selected as determined by * platform specific policy. Memory is preserved across this * operation. */ #define HV_FAST_MACH_SIR 0x02 /* mach_set_soft_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_SET_SOFT_STATE * ARG0: software state * ARG1: software state description pointer * RET0: status * ERRORS: EINVAL software state not valid or software state * description is not NULL terminated * ENORADDR software state description pointer is not a * valid real address * EBADALIGNED software state description is not correctly * aligned * * This allows the guest to report it's soft state to the hypervisor. There * are two primary components to this state. The first part states whether * the guest software is running or not. The second containts optional * details specific to the software. * * The software state argument is defined below in HV_SOFT_STATE_*, and * indicates whether the guest is operating normally or in a transitional * state. * * The software state description argument is a real address of a data buffer * of size 32-bytes aligned on a 32-byte boundary. It is treated as a NULL * terminated 7-bit ASCII string of up to 31 characters not including the * NULL termination. */ #define HV_FAST_MACH_SET_SOFT_STATE 0x03 #define HV_SOFT_STATE_NORMAL 0x01 #define HV_SOFT_STATE_TRANSITION 0x02 /* mach_get_soft_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_MACH_GET_SOFT_STATE * ARG0: software state description pointer * RET0: status * RET1: software state * ERRORS: ENORADDR software state description pointer is not a * valid real address * EBADALIGNED software state description is not correctly * aligned * * Retrieve the current value of the guest's software state. The rules * for the software state pointer are the same as for mach_set_soft_state() * above. */ #define HV_FAST_MACH_GET_SOFT_STATE 0x04 /* CPU services. * * CPUs represent devices that can execute software threads. A single * chip that contains multiple cores or strands is represented as * multiple CPUs with unique CPU identifiers. CPUs are exported to * OBP via the machine description (and to the OS via the OBP device * tree). CPUs are always in one of three states: stopped, running, * or error. * * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a * CPU within a logical domain. Operations that are to be performed * on multiple CPUs specify them via a CPU list. A CPU list is an * array in real memory, of which each 16-bit word is a CPU ID. CPU * lists are passed through the API as two arguments. The first is * the number of entries (16-bit words) in the CPU list, and the * second is the (real address) pointer to the CPU ID list. */ /* cpu_start() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_START * ARG0: CPU ID * ARG1: PC * ARG1: RTBA * ARG1: target ARG0 * RET0: status * ERRORS: ENOCPU Invalid CPU ID * EINVAL Target CPU ID is not in the stopped state * ENORADDR Invalid PC or RTBA real address * EBADALIGN Unaligned PC or unaligned RTBA * EWOULDBLOCK Starting resources are not available * * Start CPU with given CPU ID with PC in %pc and with a real trap * base address value of RTBA. The indicated CPU must be in the * stopped state. The supplied RTBA must be aligned on a 256 byte * boundary. On successful completion, the specified CPU will be in * the running state and will be supplied with "target ARG0" in %o0 * and RTBA in %tba. */ #define HV_FAST_CPU_START 0x10 /* cpu_stop() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_STOP * ARG0: CPU ID * RET0: status * ERRORS: ENOCPU Invalid CPU ID * EINVAL Target CPU ID is the current cpu * EINVAL Target CPU ID is not in the running state * EWOULDBLOCK Stopping resources are not available * ENOTSUPPORTED Not supported on this platform * * The specified CPU is stopped. The indicated CPU must be in the * running state. On completion, it will be in the stopped state. It * is not legal to stop the current CPU. * * Note: As this service cannot be used to stop the current cpu, this service * may not be used to stop the last running CPU in a domain. To stop * and exit a running domain, a guest must use the mach_exit() service. */ #define HV_FAST_CPU_STOP 0x11 /* cpu_yield() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_YIELD * RET0: status * ERRORS: No possible error. * * Suspend execution on the current CPU. Execution will resume when * an interrupt (device, %stick_compare, or cross-call) is targeted to * the CPU. On some CPUs, this API may be used by the hypervisor to * save power by disabling hardware strands. */ #define HV_FAST_CPU_YIELD 0x12 #ifndef __ASSEMBLY__ extern unsigned long sun4v_cpu_yield(void); #endif /* cpu_qconf() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_QCONF * ARG0: queue * ARG1: base real address * ARG2: number of entries * RET0: status * ERRORS: ENORADDR Invalid base real address * EINVAL Invalid queue or number of entries is less * than 2 or too large. * EBADALIGN Base real address is not correctly aligned * for size. * * Configure the given queue to be placed at the given base real * address, with the given number of entries. The number of entries * must be a power of 2. The base real address must be aligned * exactly to match the queue size. Each queue entry is 64 bytes * long, so for example a 32 entry queue must be aligned on a 2048 * byte real address boundary. * * The specified queue is unconfigured if the number of entries is given * as zero. * * For the current version of this API service, the argument queue is defined * as follows: * * queue description * ----- ------------------------- * 0x3c cpu mondo queue * 0x3d device mondo queue * 0x3e resumable error queue * 0x3f non-resumable error queue * * Note: The maximum number of entries for each queue for a specific cpu may * be determined from the machine description. */ #define HV_FAST_CPU_QCONF 0x14 #define HV_CPU_QUEUE_CPU_MONDO 0x3c #define HV_CPU_QUEUE_DEVICE_MONDO 0x3d #define HV_CPU_QUEUE_RES_ERROR 0x3e #define HV_CPU_QUEUE_NONRES_ERROR 0x3f #ifndef __ASSEMBLY__ extern unsigned long sun4v_cpu_qconf(unsigned long type, unsigned long queue_paddr, unsigned long num_queue_entries); #endif /* cpu_qinfo() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_QINFO * ARG0: queue * RET0: status * RET1: base real address * RET1: number of entries * ERRORS: EINVAL Invalid queue * * Return the configuration info for the given queue. The base real * address and number of entries of the defined queue are returned. * The queue argument values are the same as for cpu_qconf() above. * * If the specified queue is a valid queue number, but no queue has * been defined, the number of entries will be set to zero and the * base real address returned is undefined. */ #define HV_FAST_CPU_QINFO 0x15 /* cpu_mondo_send() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_MONDO_SEND * ARG0-1: CPU list * ARG2: data real address * RET0: status * ERRORS: EBADALIGN Mondo data is not 64-byte aligned or CPU list * is not 2-byte aligned. * ENORADDR Invalid data mondo address, or invalid cpu list * address. * ENOCPU Invalid cpu in CPU list * EWOULDBLOCK Some or all of the listed CPUs did not receive * the mondo * ECPUERROR One or more of the listed CPUs are in error * state, use HV_FAST_CPU_STATE to see which ones * EINVAL CPU list includes caller's CPU ID * * Send a mondo interrupt to the CPUs in the given CPU list with the * 64-bytes at the given data real address. The data must be 64-byte * aligned. The mondo data will be delivered to the cpu_mondo queues * of the recipient CPUs. * * In all cases, error or not, the CPUs in the CPU list to which the * mondo has been successfully delivered will be indicated by having * their entry in CPU list updated with the value 0xffff. */ #define HV_FAST_CPU_MONDO_SEND 0x42 #ifndef __ASSEMBLY__ extern unsigned long sun4v_cpu_mondo_send(unsigned long cpu_count, unsigned long cpu_list_pa, unsigned long mondo_block_pa); #endif /* cpu_myid() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_MYID * RET0: status * RET1: CPU ID * ERRORS: No errors defined. * * Return the hypervisor ID handle for the current CPU. Use by a * virtual CPU to discover it's own identity. */ #define HV_FAST_CPU_MYID 0x16 /* cpu_state() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_STATE * ARG0: CPU ID * RET0: status * RET1: state * ERRORS: ENOCPU Invalid CPU ID * * Retrieve the current state of the CPU with the given CPU ID. */ #define HV_FAST_CPU_STATE 0x17 #define HV_CPU_STATE_STOPPED 0x01 #define HV_CPU_STATE_RUNNING 0x02 #define HV_CPU_STATE_ERROR 0x03 #ifndef __ASSEMBLY__ extern long sun4v_cpu_state(unsigned long cpuid); #endif /* cpu_set_rtba() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_SET_RTBA * ARG0: RTBA * RET0: status * RET1: previous RTBA * ERRORS: ENORADDR Invalid RTBA real address * EBADALIGN RTBA is incorrectly aligned for a trap table * * Set the real trap base address of the local cpu to the given RTBA. * The supplied RTBA must be aligned on a 256 byte boundary. Upon * success the previous value of the RTBA is returned in RET1. * * Note: This service does not affect %tba */ #define HV_FAST_CPU_SET_RTBA 0x18 /* cpu_set_rtba() * TRAP: HV_FAST_TRAP * FUNCTION: HV_FAST_CPU_GET_RTBA * RET0: status * RET1: previous RTBA * ERRORS: No possible error. * * Returns the current value of RTBA in RET1. */ #define HV_FAST_CPU_GET_RTBA 0x19 /* MMU services. * * Layout of a TSB description for mmu_tsb_ctx{,non}0() calls. */ #ifndef __ASSEMBLY__ struct hv_tsb_descr { unsigned short pgsz_idx; unsigned short assoc; unsigned int num_ttes; /* in TTEs */ unsigned int ctx_idx; unsigned int pgsz_mask; unsigned long tsb_base; unsigned long resv; }; #endif #define HV_TSB_DESCR_PGSZ_IDX_OFFSET 0x00 #define HV_TSB_DESCR_ASSOC_OFFSET 0x02 #define HV_TSB_DESCR_NUM_TTES_OFFSET 0x04 #define HV_TSB_DESCR_CTX_IDX_OFFSET 0x08 #define HV_TSB_DESCR_PGSZ_MASK_OFFSET 0x0c #define HV_TSB_DESCR_TSB_BASE_OFFSET 0x10 #define HV_TSB_DESCR_RESV_OFFSET 0x18 /* Page size bitmask. */ #define HV_PGSZ_MASK_8K (1 << 0) #define HV_PGSZ_MASK_64K (1 << 1) #define HV_PGSZ_MASK_512K (1 << 2) #define HV_PGSZ_MASK_4MB (1 << 3) #define HV_PGSZ_MASK_32MB (1 << 4) #define HV_PGSZ_MASK_256MB (1 << 5) #define HV_PGSZ_MASK_2GB (1 << 6) #define HV_PGSZ_MASK_16GB (1 << 7) /* Page size index. The value given in the TSB descriptor must correspond * to the smallest page size specified in the pgsz_mask page size bitmask. */ #define HV_PGSZ_IDX_8K 0 #define HV_PGSZ_IDX_64K 1 #define HV_PGSZ_IDX_512K 2 #define HV_PGSZ_IDX_4MB 3 #define HV_PGSZ_IDX_32MB 4 #define HV_PGSZ_IDX_256MB 5 #define HV_PGSZ_IDX_2GB 6 #define HV_PGSZ_IDX_16GB 7 /* MMU fault status area. * * MMU related faults have their status and fault address information * placed into a memory region made available by privileged code. Each * virtual processor must make a mmu_fault_area_conf() call to tell the * hypervisor where that processor's fault status should be stored. * * The fault status block is a multiple of 64-bytes and must be aligned * on a 64-byte boundary. */ #ifndef __ASSEMBLY__ struct hv_fault_status { unsigned long i_fault_type; unsigned long i_fault_addr; unsigned long i_fault_ctx; unsigned long i_reserved[5]; unsigned long d_fault_type; unsigned long d_fault_addr; unsigned long d_fault_ctx; unsigned long d_reserved[5]; }; #endif #define HV_FAULT_I_TYPE_OFFSET 0x00 #define HV_FAULT_I_ADDR_OFFSET 0x08 #define HV_FAULT_I_CTX_OFFSET 0x10 #define HV_FAULT_D_TYPE_OFFSET 0x40 #define HV_FAULT_D_ADDR_OFFSET 0x48 #define HV_FAULT_D_CTX_OFFSET 0x50 #define HV_FAULT_TYPE_FAST_MISS 1 #define HV_FAULT_TYPE_FAST_PROT 2 #define HV_FAULT_TYPE_MMU_MISS 3 #define HV_FAULT_TYPE_INV_RA 4