/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note *//* * Format of an instruction in memory. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2014 Imagination Technologies Ltd. */#ifndef _UAPI_ASM_INST_H#define _UAPI_ASM_INST_H #include <asm/bitfield.h> /* * Major opcodes; before MIPS IV cop1x was called cop3. */enum major_op { spec_op, bcond_op, j_op, jal_op, beq_op, bne_op, blez_op, bgtz_op, addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, andi_op, ori_op, xori_op, lui_op, cop0_op, cop1_op, cop2_op, cop1x_op, beql_op, bnel_op, blezl_op, bgtzl_op, daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, lb_op, lh_op, lwl_op, lw_op, lbu_op, lhu_op, lwr_op, lwu_op, sb_op, sh_op, swl_op, sw_op, sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op}; /* * func field of spec opcode. */enum spec_op { sll_op, movc_op, srl_op, sra_op, sllv_op, pmon_op, srlv_op, srav_op, jr_op, jalr_op, movz_op, movn_op, syscall_op, break_op, spim_op, sync_op, mfhi_op, mthi_op, mflo_op, mtlo_op, dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, mult_op, multu_op, div_op, divu_op, dmult_op, dmultu_op, ddiv_op, ddivu_op, add_op, addu_op, sub_op, subu_op, and_op, or_op, xor_op, nor_op, spec3_unused_op, spec4_unused_op, slt_op, sltu_op, dadd_op, daddu_op, dsub_op, dsubu_op, tge_op, tgeu_op, tlt_op, tltu_op, teq_op, seleqz_op, tne_op, selnez_op, dsll_op, spec5_unused_op, dsrl_op, dsra_op, dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op}; /* * func field of spec2 opcode. */enum spec2_op { madd_op, maddu_op, mul_op, spec2_3_unused_op, msub_op, msubu_op, /* more unused ops */ clz_op = 0x20, clo_op, dclz_op = 0x24, dclo_op, sdbpp_op = 0x3f}; /* * func field of spec3 opcode. */enum spec3_op { ext_op, dextm_op, dextu_op, dext_op, ins_op, dinsm_op, dinsu_op, dins_op, yield_op = 0x09, lx_op = 0x0a, lwle_op = 0x19, lwre_op = 0x1a, cachee_op = 0x1b, sbe_op = 0x1c, she_op = 0x1d, sce_op = 0x1e, swe_op = 0x1f, bshfl_op = 0x20, swle_op = 0x21, swre_op = 0x22, prefe_op = 0x23, dbshfl_op = 0x24, cache6_op = 0x25, sc6_op = 0x26, scd6_op = 0x27, lbue_op = 0x28, lhue_op = 0x29, lbe_op = 0x2c, lhe_op = 0x2d, lle_op = 0x2e, lwe_op = 0x2f, pref6_op = 0x35, ll6_op = 0x36, lld6_op = 0x37, rdhwr_op = 0x3b}; /* * Bits 10-6 minor opcode for r6 spec mult/div encodings */enum mult_op { mult_mult_op = 0x0, mult_mul_op = 0x2, mult_muh_op = 0x3,};enum multu_op { multu_multu_op = 0x0, multu_mulu_op = 0x2, multu_muhu_op = 0x3,};enum div_op { div_div_op = 0x0, div_div6_op = 0x2, div_mod_op = 0x3,};enum divu_op { divu_divu_op = 0x0, divu_divu6_op = 0x2, divu_modu_op = 0x3,};enum dmult_op { dmult_dmult_op = 0x0, dmult_dmul_op = 0x2, dmult_dmuh_op = 0x3,};enum dmultu_op { dmultu_dmultu_op = 0x0, dmultu_dmulu_op = 0x2, dmultu_dmuhu_op = 0x3,};enum ddiv_op { ddiv_ddiv_op = 0x0, ddiv_ddiv6_op = 0x2, ddiv_dmod_op = 0x3,};enum ddivu_op { ddivu_ddivu_op = 0x0, ddivu_ddivu6_op = 0x2, ddivu_dmodu_op = 0x3,}; /* * rt field of bcond opcodes. */enum rt_op { bltz_op, bgez_op, bltzl_op, bgezl_op, spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, tgei_op, tgeiu_op, tlti_op, tltiu_op, teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, bltzal_op, bgezal_op, bltzall_op, bgezall_op, rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op}; /* * rs field of cop opcodes. */enum cop_op { mfc_op = 0x00, dmfc_op = 0x01, cfc_op = 0x02, mfhc0_op = 0x02, mfhc_op = 0x03, mtc_op = 0x04, dmtc_op = 0x05, ctc_op = 0x06, mthc0_op = 0x06, mthc_op = 0x07, bc_op = 0x08, bc1eqz_op = 0x09, mfmc0_op = 0x0b, bc1nez_op = 0x0d, wrpgpr_op = 0x0e, cop_op = 0x10, copm_op = 0x18}; /* * rt field of cop.bc_op opcodes */enum bcop_op { bcf_op, bct_op, bcfl_op, bctl_op}; /* * func field of cop0 coi opcodes. */enum cop0_coi_func { tlbr_op = 0x01, tlbwi_op = 0x02, tlbwr_op = 0x06, tlbp_op = 0x08, rfe_op = 0x10, eret_op = 0x18, wait_op = 0x20, hypcall_op = 0x28}; /* * func field of cop0 com opcodes. */enum cop0_com_func { tlbr1_op = 0x01, tlbw_op = 0x02, tlbp1_op = 0x08, dctr_op = 0x09, dctw_op = 0x0a}; /* * fmt field of cop1 opcodes. */enum cop1_fmt { s_fmt, d_fmt, e_fmt, q_fmt, w_fmt, l_fmt}; /* * func field of cop1 instructions using d, s or w format. */enum cop1_sdw_func { fadd_op = 0x00, fsub_op = 0x01, fmul_op = 0x02, fdiv_op = 0x03, fsqrt_op = 0x04, fabs_op = 0x05, fmov_op = 0x06, fneg_op = 0x07, froundl_op = 0x08, ftruncl_op = 0x09, fceill_op = 0x0a, ffloorl_op = 0x0b, fround_op = 0x0c, ftrunc_op = 0x0d, fceil_op = 0x0e, ffloor_op = 0x0f, fsel_op = 0x10, fmovc_op = 0x11, fmovz_op = 0x12, fmovn_op = 0x13, fseleqz_op = 0x14, frecip_op = 0x15, frsqrt_op = 0x16, fselnez_op = 0x17, fmaddf_op = 0x18, fmsubf_op = 0x19, frint_op = 0x1a, fclass_op = 0x1b, fmin_op = 0x1c, fmina_op = 0x1d, fmax_op = 0x1e, fmaxa_op = 0x1f, fcvts_op = 0x20, fcvtd_op = 0x21, fcvte_op = 0x22, fcvtw_op = 0x24, fcvtl_op = 0x25, fcmp_op = 0x30}; /* * func field of cop1x opcodes (MIPS IV). */enum cop1x_func { lwxc1_op = 0x00, ldxc1_op = 0x01, swxc1_op = 0x08, sdxc1_op = 0x09, pfetch_op = 0x0f, madd_s_op = 0x20, madd_d_op = 0x21, madd_e_op = 0x22, msub_s_op = 0x28, msub_d_op = 0x29, msub_e_op = 0x2a, nmadd_s_op = 0x30, nmadd_d_op = 0x31, nmadd_e_op = 0x32, nmsub_s_op = 0x38, nmsub_d_op = 0x39, nmsub_e_op = 0x3a}; /* * func field for mad opcodes (MIPS IV). */enum mad_func { madd_fp_op = 0x08, msub_fp_op = 0x0a, nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e}; /* * func field for page table walker (Loongson-3). */enum ptw_func { lwdir_op = 0x00, lwpte_op = 0x01, lddir_op = 0x02, ldpte_op = 0x03,}; /* * func field for special3 lx opcodes (Cavium Octeon). */enum lx_func { lwx_op = 0x00, lhx_op = 0x04, lbux_op = 0x06, ldx_op = 0x08, lwux_op = 0x10, lhux_op = 0x14, lbx_op = 0x16,}; /* * func field for special2 MXU opcodes (Ingenic XBurst MXU). */enum mxu_func { /* TODO, other MXU funcs */ mxu_lx_op = 0x28,}; /* * op field for special2 MXU LX opcodes (Ingenic XBurst MXU). */enum lx_ingenic_func { mxu_lxb_op, mxu_lxh_op, /* reserved */ mxu_lxw_op = 3, mxu_lxbu_op, mxu_lxhu_op, /* more reserved */}; /* * BSHFL opcodes */enum bshfl_func { wsbh_op = 0x2, seb_op = 0x10, seh_op = 0x18,}; /* * DBSHFL opcodes */enum dbshfl_func { dsbh_op = 0x2, dshd_op = 0x5,}; /* * MSA minor opcodes. */enum msa_func { msa_elm_op = 0x19,}; /* * MSA ELM opcodes. */enum msa_elm { msa_ctc_op = 0x3e, msa_cfc_op = 0x7e,}; /* * func field for MSA MI10 format. */enum msa_mi10_func { msa_ld_op = 8, msa_st_op = 9,}; /* * MSA 2 bit format fields. */enum msa_2b_fmt { msa_fmt_b = 0, msa_fmt_h = 1, msa_fmt_w = 2, msa_fmt_d = 3,}; /* * (microMIPS) Major opcodes. */enum mm_major_op { mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op, mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,}; /* * (microMIPS) POOL32I minor opcodes. */enum mm_32i_minor_op { mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,}; /* * (microMIPS) POOL32A minor opcodes. */enum mm_32a_minor_op { mm_sll32_op = 0x000, mm_ins_op = 0x00c, mm_sllv32_op = 0x010, mm_ext_op = 0x02c, mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, mm_srlv32_op = 0x050, mm_sra_op = 0x080, mm_srav_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, mm_subu32_op = 0x1d0, mm_wsbh_op = 0x1ec, mm_mul_op = 0x210, mm_and_op = 0x250, mm_or32_op = 0x290, mm_xor32_op = 0x310, mm_slt_op = 0x350, mm_sltu_op = 0x390,}; /* * (microMIPS) POOL32B functions. */enum mm_32b_func { mm_lwc2_func = 0x0, mm_lwp_func = 0x1, mm_ldc2_func = 0x2, mm_ldp_func = 0x4, mm_lwm32_func = 0x5, mm_cache_func = 0x6, mm_ldm_func = 0x7, mm_swc2_func = 0x8, mm_swp_func = 0x9, mm_sdc2_func = 0xa, mm_sdp_func = 0xc, mm_swm32_func = 0xd, mm_sdm_func = 0xf,}; /* * (microMIPS) POOL32C functions. */enum mm_32c_func { mm_pref_func = 0x2, mm_ll_func = 0x3, mm_swr_func = 0x9, mm_sc_func = 0xb, mm_lwu_func = 0xe,}; /* * (microMIPS) POOL32AXF minor opcodes. */enum mm_32axf_minor_op { mm_mfc0_op = 0x003, mm_mtc0_op = 0x00b, mm_tlbp_op = 0x00d, mm_mfhi32_op = 0x035, mm_jalr_op = 0x03c, mm_tlbr_op = 0x04d, mm_mflo32_op = 0x075, mm_jalrhb_op = 0x07c, mm_tlbwi_op = 0x08d, mm_mthi32_op = 0x0b5, mm_tlbwr_op = 0x0cd, mm_mtlo32_op = 0x0f5, mm_di_op = 0x11d, mm_jalrs_op = 0x13c, mm_jalrshb_op = 0x17c, mm_sync_op = 0x1ad, mm_syscall_op = 0x22d, mm_wait_op = 0x24d, mm_eret_op = 0x3cd, mm_divu_op = 0x5dc,}; /* * (microMIPS) POOL32F minor opcodes. */enum mm_32f_minor_op { mm_32f_00_op = 0x00, mm_32f_01_op = 0x01, mm_32f_02_op = 0x02, mm_32f_10_op = 0x08, mm_32f_11_op = 0x09, mm_32f_12_op = 0x0a, mm_32f_20_op = 0x10, mm_32f_30_op = 0x18, mm_32f_40_op = 0x20, mm_32f_41_op = 0x21, mm_32f_42_op = 0x22, mm_32f_50_op = 0x28, mm_32f_51_op = 0x29, mm_32f_52_op = 0x2a, mm_32f_60_op = 0x30, mm_32f_70_op = 0x38, mm_32f_73_op = 0x3b, mm_32f_74_op = 0x3c,}; /* * (microMIPS) POOL32F secondary minor opcodes. */enum mm_32f_10_minor_op { mm_lwxc1_op = 0x1, mm_swxc1_op, mm_ldxc1_op, mm_sdxc1_op, mm_luxc1_op, mm_suxc1_op,}; Lines 1–500 of 1174. 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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Format of an instruction in memory. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1996, 2000 by Ralf Baechle * Copyright (C) 2006 by Thiemo Seufer * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2014 Imagination Technologies Ltd. */ #ifndef _UAPI_ASM_INST_H #define _UAPI_ASM_INST_H #include <asm/bitfield.h> /* * Major opcodes; before MIPS IV cop1x was called cop3. */ enum major_op { spec_op, bcond_op, j_op, jal_op, beq_op, bne_op, blez_op, bgtz_op, addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op, andi_op, ori_op, xori_op, lui_op, cop0_op, cop1_op, cop2_op, cop1x_op, beql_op, bnel_op, blezl_op, bgtzl_op, daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op, spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op, lb_op, lh_op, lwl_op, lw_op, lbu_op, lhu_op, lwr_op, lwu_op, sb_op, sh_op, swl_op, sw_op, sdl_op, sdr_op, swr_op, cache_op, ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op, lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op, sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op, scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op }; /* * func field of spec opcode. */ enum spec_op { sll_op, movc_op, srl_op, sra_op, sllv_op, pmon_op, srlv_op, srav_op, jr_op, jalr_op, movz_op, movn_op, syscall_op, break_op, spim_op, sync_op, mfhi_op, mthi_op, mflo_op, mtlo_op, dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op, mult_op, multu_op, div_op, divu_op, dmult_op, dmultu_op, ddiv_op, ddivu_op, add_op, addu_op, sub_op, subu_op, and_op, or_op, xor_op, nor_op, spec3_unused_op, spec4_unused_op, slt_op, sltu_op, dadd_op, daddu_op, dsub_op, dsubu_op, tge_op, tgeu_op, tlt_op, tltu_op, teq_op, seleqz_op, tne_op, selnez_op, dsll_op, spec5_unused_op, dsrl_op, dsra_op, dsll32_op, spec6_unused_op, dsrl32_op, dsra32_op }; /* * func field of spec2 opcode. */ enum spec2_op { madd_op, maddu_op, mul_op, spec2_3_unused_op, msub_op, msubu_op, /* more unused ops */ clz_op = 0x20, clo_op, dclz_op = 0x24, dclo_op, sdbpp_op = 0x3f }; /* * func field of spec3 opcode. */ enum spec3_op { ext_op, dextm_op, dextu_op, dext_op, ins_op, dinsm_op, dinsu_op, dins_op, yield_op = 0x09, lx_op = 0x0a, lwle_op = 0x19, lwre_op = 0x1a, cachee_op = 0x1b, sbe_op = 0x1c, she_op = 0x1d, sce_op = 0x1e, swe_op = 0x1f, bshfl_op = 0x20, swle_op = 0x21, swre_op = 0x22, prefe_op = 0x23, dbshfl_op = 0x24, cache6_op = 0x25, sc6_op = 0x26, scd6_op = 0x27, lbue_op = 0x28, lhue_op = 0x29, lbe_op = 0x2c, lhe_op = 0x2d, lle_op = 0x2e, lwe_op = 0x2f, pref6_op = 0x35, ll6_op = 0x36, lld6_op = 0x37, rdhwr_op = 0x3b }; /* * Bits 10-6 minor opcode for r6 spec mult/div encodings */ enum mult_op { mult_mult_op = 0x0, mult_mul_op = 0x2, mult_muh_op = 0x3, }; enum multu_op { multu_multu_op = 0x0, multu_mulu_op = 0x2, multu_muhu_op = 0x3, }; enum div_op { div_div_op = 0x0, div_div6_op = 0x2, div_mod_op = 0x3, }; enum divu_op { divu_divu_op = 0x0, divu_divu6_op = 0x2, divu_modu_op = 0x3, }; enum dmult_op { dmult_dmult_op = 0x0, dmult_dmul_op = 0x2, dmult_dmuh_op = 0x3, }; enum dmultu_op { dmultu_dmultu_op = 0x0, dmultu_dmulu_op = 0x2, dmultu_dmuhu_op = 0x3, }; enum ddiv_op { ddiv_ddiv_op = 0x0, ddiv_ddiv6_op = 0x2, ddiv_dmod_op = 0x3, }; enum ddivu_op { ddivu_ddivu_op = 0x0, ddivu_ddivu6_op = 0x2, ddivu_dmodu_op = 0x3, }; /* * rt field of bcond opcodes. */ enum rt_op { bltz_op, bgez_op, bltzl_op, bgezl_op, spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, tgei_op, tgeiu_op, tlti_op, tltiu_op, teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, bltzal_op, bgezal_op, bltzall_op, bgezall_op, rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op }; /* * rs field of cop opcodes. */ enum cop_op { mfc_op = 0x00, dmfc_op = 0x01, cfc_op = 0x02, mfhc0_op = 0x02, mfhc_op = 0x03, mtc_op = 0x04, dmtc_op = 0x05, ctc_op = 0x06, mthc0_op = 0x06, mthc_op = 0x07, bc_op = 0x08, bc1eqz_op = 0x09, mfmc0_op = 0x0b, bc1nez_op = 0x0d, wrpgpr_op = 0x0e, cop_op = 0x10, copm_op = 0x18 }; /* * rt field of cop.bc_op opcodes */ enum bcop_op { bcf_op, bct_op, bcfl_op, bctl_op }; /* * func field of cop0 coi opcodes. */ enum cop0_coi_func { tlbr_op = 0x01, tlbwi_op = 0x02, tlbwr_op = 0x06, tlbp_op = 0x08, rfe_op = 0x10, eret_op = 0x18, wait_op = 0x20, hypcall_op = 0x28 }; /* * func field of cop0 com opcodes. */ enum cop0_com_func { tlbr1_op = 0x01, tlbw_op = 0x02, tlbp1_op = 0x08, dctr_op = 0x09, dctw_op = 0x0a }; /* * fmt field of cop1 opcodes. */ enum cop1_fmt { s_fmt, d_fmt, e_fmt, q_fmt, w_fmt, l_fmt }; /* * func field of cop1 instructions using d, s or w format. */ enum cop1_sdw_func { fadd_op = 0x00, fsub_op = 0x01, fmul_op = 0x02, fdiv_op = 0x03, fsqrt_op = 0x04, fabs_op = 0x05, fmov_op = 0x06, fneg_op = 0x07, froundl_op = 0x08, ftruncl_op = 0x09, fceill_op = 0x0a, ffloorl_op = 0x0b, fround_op = 0x0c, ftrunc_op = 0x0d, fceil_op = 0x0e, ffloor_op = 0x0f, fsel_op = 0x10, fmovc_op = 0x11, fmovz_op = 0x12, fmovn_op = 0x13, fseleqz_op = 0x14, frecip_op = 0x15, frsqrt_op = 0x16, fselnez_op = 0x17, fmaddf_op = 0x18, fmsubf_op = 0x19, frint_op = 0x1a, fclass_op = 0x1b, fmin_op = 0x1c, fmina_op = 0x1d, fmax_op = 0x1e, fmaxa_op = 0x1f, fcvts_op = 0x20, fcvtd_op = 0x21, fcvte_op = 0x22, fcvtw_op = 0x24, fcvtl_op = 0x25, fcmp_op = 0x30 }; /* * func field of cop1x opcodes (MIPS IV). */ enum cop1x_func { lwxc1_op = 0x00, ldxc1_op = 0x01, swxc1_op = 0x08, sdxc1_op = 0x09, pfetch_op = 0x0f, madd_s_op = 0x20, madd_d_op = 0x21, madd_e_op = 0x22, msub_s_op = 0x28, msub_d_op = 0x29, msub_e_op = 0x2a, nmadd_s_op = 0x30, nmadd_d_op = 0x31, nmadd_e_op = 0x32, nmsub_s_op = 0x38, nmsub_d_op = 0x39, nmsub_e_op = 0x3a }; /* * func field for mad opcodes (MIPS IV). */ enum mad_func { madd_fp_op = 0x08, msub_fp_op = 0x0a, nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e }; /* * func field for page table walker (Loongson-3). */ enum ptw_func { lwdir_op = 0x00, lwpte_op = 0x01, lddir_op = 0x02, ldpte_op = 0x03, }; /* * func field for special3 lx opcodes (Cavium Octeon). */ enum lx_func { lwx_op = 0x00, lhx_op = 0x04, lbux_op = 0x06, ldx_op = 0x08, lwux_op = 0x10, lhux_op = 0x14, lbx_op = 0x16, }; /* * func field for special2 MXU opcodes (Ingenic XBurst MXU). */ enum mxu_func { /* TODO, other MXU funcs */ mxu_lx_op = 0x28, }; /* * op field for special2 MXU LX opcodes (Ingenic XBurst MXU). */ enum lx_ingenic_func { mxu_lxb_op, mxu_lxh_op, /* reserved */ mxu_lxw_op = 3, mxu_lxbu_op, mxu_lxhu_op, /* more reserved */ }; /* * BSHFL opcodes */ enum bshfl_func { wsbh_op = 0x2, seb_op = 0x10, seh_op = 0x18, }; /* * DBSHFL opcodes */ enum dbshfl_func { dsbh_op = 0x2, dshd_op = 0x5, }; /* * MSA minor opcodes. */ enum msa_func { msa_elm_op = 0x19, }; /* * MSA ELM opcodes. */ enum msa_elm { msa_ctc_op = 0x3e, msa_cfc_op = 0x7e, }; /* * func field for MSA MI10 format. */ enum msa_mi10_func { msa_ld_op = 8, msa_st_op = 9, }; /* * MSA 2 bit format fields. */ enum msa_2b_fmt { msa_fmt_b = 0, msa_fmt_h = 1, msa_fmt_w = 2, msa_fmt_d = 3, }; /* * (microMIPS) Major opcodes. */ enum mm_major_op { mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op, mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op, mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op, mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op, mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op, mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op, mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op, mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op, mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op, mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op, mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op, mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op, mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op, mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op, mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op, mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op, }; /* * (microMIPS) POOL32I minor opcodes. */ enum mm_32i_minor_op { mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op, mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op, mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op, mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op, mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op, mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op, mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op, mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op, mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op, }; /* * (microMIPS) POOL32A minor opcodes. */ enum mm_32a_minor_op { mm_sll32_op = 0x000, mm_ins_op = 0x00c, mm_sllv32_op = 0x010, mm_ext_op = 0x02c, mm_pool32axf_op = 0x03c, mm_srl32_op = 0x040, mm_srlv32_op = 0x050, mm_sra_op = 0x080, mm_srav_op = 0x090, mm_rotr_op = 0x0c0, mm_lwxs_op = 0x118, mm_addu32_op = 0x150, mm_subu32_op = 0x1d0, mm_wsbh_op = 0x1ec, mm_mul_op = 0x210, mm_and_op = 0x250, mm_or32_op = 0x290, mm_xor32_op = 0x310, mm_slt_op = 0x350, mm_sltu_op = 0x390, }; /* * (microMIPS) POOL32B functions. */ enum mm_32b_func { mm_lwc2_func = 0x0, mm_lwp_func = 0x1, mm_ldc2_func = 0x2, mm_ldp_func = 0x4, mm_lwm32_func = 0x5, mm_cache_func = 0x6, mm_ldm_func = 0x7, mm_swc2_func = 0x8, mm_swp_func = 0x9, mm_sdc2_func = 0xa, mm_sdp_func = 0xc, mm_swm32_func = 0xd, mm_sdm_func = 0xf, }; /* * (microMIPS) POOL32C functions. */ enum mm_32c_func { mm_pref_func = 0x2, mm_ll_func = 0x3, mm_swr_func = 0x9, mm_sc_func = 0xb, mm_lwu_func = 0xe, }; /* * (microMIPS) POOL32AXF minor opcodes. */ enum mm_32axf_minor_op { mm_mfc0_op = 0x003, mm_mtc0_op = 0x00b, mm_tlbp_op = 0x00d, mm_mfhi32_op = 0x035, mm_jalr_op = 0x03c, mm_tlbr_op = 0x04d, mm_mflo32_op = 0x075, mm_jalrhb_op = 0x07c, mm_tlbwi_op = 0x08d, mm_mthi32_op = 0x0b5, mm_tlbwr_op = 0x0cd, mm_mtlo32_op = 0x0f5, mm_di_op = 0x11d, mm_jalrs_op = 0x13c, mm_jalrshb_op = 0x17c, mm_sync_op = 0x1ad, mm_syscall_op = 0x22d, mm_wait_op = 0x24d, mm_eret_op = 0x3cd, mm_divu_op = 0x5dc, }; /* * (microMIPS) POOL32F minor opcodes. */ enum mm_32f_minor_op { mm_32f_00_op = 0x00, mm_32f_01_op = 0x01, mm_32f_02_op = 0x02, mm_32f_10_op = 0x08, mm_32f_11_op = 0x09, mm_32f_12_op = 0x0a, mm_32f_20_op = 0x10, mm_32f_30_op = 0x18, mm_32f_40_op = 0x20, mm_32f_41_op = 0x21, mm_32f_42_op = 0x22, mm_32f_50_op = 0x28, mm_32f_51_op = 0x29, mm_32f_52_op = 0x2a, mm_32f_60_op = 0x30, mm_32f_70_op = 0x38, mm_32f_73_op = 0x3b, mm_32f_74_op = 0x3c, }; /* * (microMIPS) POOL32F secondary minor opcodes. */ enum mm_32f_10_minor_op { mm_lwxc1_op = 0x1, mm_swxc1_op, mm_ldxc1_op, mm_sdxc1_op, mm_luxc1_op, mm_suxc1_op, };