// SPDX-License-Identifier: GPL-2.0/* * General MIPS MT support routines, usable in AP/SP and SMVP. * Copyright (C) 2005 Mips Technologies, Inc */ #include <linux/device.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/export.h>#include <linux/interrupt.h>#include <linux/security.h> #include <asm/cpu.h>#include <asm/processor.h>#include <linux/atomic.h>#include <asm/hardirq.h>#include <asm/mmu_context.h>#include <asm/mipsmtregs.h>#include <asm/r4kcache.h>#include <asm/cacheflush.h>#include <asm/mips_mt.h> int vpelimit; static int __init maxvpes(char *str){	get_option(&str, &vpelimit); 	return 1;} __setup("maxvpes=", maxvpes); int tclimit; static int __init maxtcs(char *str){	get_option(&str, &tclimit); 	return 1;} __setup("maxtcs=", maxtcs); static int mt_opt_rpsctl = -1;static int mt_opt_nblsu = -1;static int mt_opt_forceconfig7;static int mt_opt_config7 = -1; static int __init rpsctl_set(char *str){	get_option(&str, &mt_opt_rpsctl);	return 1;}__setup("rpsctl=", rpsctl_set); static int __init nblsu_set(char *str){	get_option(&str, &mt_opt_nblsu);	return 1;}__setup("nblsu=", nblsu_set); static int __init config7_set(char *str){	get_option(&str, &mt_opt_config7);	mt_opt_forceconfig7 = 1;	return 1;}__setup("config7=", config7_set); static unsigned int itc_base; static int __init set_itc_base(char *str){	get_option(&str, &itc_base);	return 1;} __setup("itcbase=", set_itc_base); void mips_mt_set_cpuoptions(void){	unsigned int oconfig7 = read_c0_config7();	unsigned int nconfig7 = oconfig7; 	if (mt_opt_rpsctl >= 0) {		printk("34K return prediction stack override set to %d.\n",			mt_opt_rpsctl);		if (mt_opt_rpsctl)			nconfig7 |= (1 << 2);		else			nconfig7 &= ~(1 << 2);	}	if (mt_opt_nblsu >= 0) {		printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);		if (mt_opt_nblsu)			nconfig7 |= (1 << 5);		else			nconfig7 &= ~(1 << 5);	}	if (mt_opt_forceconfig7) {		printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);		nconfig7 = mt_opt_config7;	}	if (oconfig7 != nconfig7) {		__asm__ __volatile("sync");		write_c0_config7(nconfig7);		ehb();		printk("Config7: 0x%08x\n", read_c0_config7());	} 	if (itc_base != 0) {		/*		 * Configure ITC mapping.  This code is very		 * specific to the 34K core family, which uses		 * a special mode bit ("ITC") in the ErrCtl		 * register to enable access to ITC control		 * registers via cache "tag" operations.		 */		unsigned long ectlval;		unsigned long itcblkgrn; 		ectlval = read_c0_errctl();		write_c0_errctl(ectlval | (0x1 << 26));		ehb();#define INDEX_0 (0x80000000)#define INDEX_8 (0x80000008)		/* Read "cache tag" for Dcache pseudo-index 8 */		cache_op(Index_Load_Tag_D, INDEX_8);		ehb();		itcblkgrn = read_c0_dtaglo();		itcblkgrn &= 0xfffe0000;		/* Set for 128 byte pitch of ITC cells */		itcblkgrn |= 0x00000c00;		/* Stage in Tag register */		write_c0_dtaglo(itcblkgrn);		ehb();		/* Write out to ITU with CACHE op */		cache_op(Index_Store_Tag_D, INDEX_8);		/* Now set base address, and turn ITC on with 0x1 bit */		write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );		ehb();		/* Write out to ITU with CACHE op */		cache_op(Index_Store_Tag_D, INDEX_0);		write_c0_errctl(ectlval);		ehb();		printk("Mapped %ld ITC cells starting at 0x%08x\n",			((itcblkgrn & 0x7fe00000) >> 20), itc_base);	}} const struct class mt_class = {	.name = "mt",}; static int __init mips_mt_init(void){	return class_register(&mt_class);} subsys_initcall(mips_mt_init);