/* SPDX-License-Identifier: GPL-2.0-or-later *//* * OpenRISC head.S * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * Modifications for the OpenRISC architecture: * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> */ #include <linux/linkage.h>#include <linux/threads.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/serial_reg.h>#include <linux/pgtable.h>#include <asm/processor.h>#include <asm/page.h>#include <asm/mmu.h>#include <asm/thread_info.h>#include <asm/cache.h>#include <asm/spr_defs.h>#include <asm/asm-offsets.h>#include <linux/of_fdt.h> #define tophys(rd,rs) \ l.movhi rd,hi(-KERNELBASE) ;\ l.add rd,rd,rs #define CLEAR_GPR(gpr) \ l.movhi gpr,0x0 #define LOAD_SYMBOL_2_GPR(gpr,symbol) \ l.movhi gpr,hi(symbol) ;\ l.ori gpr,gpr,lo(symbol) #define UART_BASE_ADD 0x90000000 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)#define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM) /* ============================================[ tmp store locations ]=== */ #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32) /* * emergency_print temporary stores */#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)#define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14) #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)#define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15) #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)#define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16) #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)#define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7) #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)#define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8) #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)#define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0) #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5#define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0) #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6#define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0) #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7#define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0) #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8#define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0) #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0) #endif /* * TLB miss handlers temorary stores */#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS#define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)#define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2) #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)#define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3) #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)#define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4) #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)#define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5) #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)#define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0) #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3#define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0) #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4#define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0) #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5#define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0) #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0) #endif /* * EXCEPTION_HANDLE temporary stores */ #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS#define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)#define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30) #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)#define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10) #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)#define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0) #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0) #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)#endif /* =========================================================[ macros ]=== */ #ifdef CONFIG_SMP#define GET_CURRENT_PGD(reg,t1) \ LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ l.mfspr t1,r0,SPR_COREID ;\ l.slli t1,t1,2 ;\ l.add reg,reg,t1 ;\ tophys (t1,reg) ;\ l.lwz reg,0(t1)#else#define GET_CURRENT_PGD(reg,t1) \ LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ tophys (t1,reg) ;\ l.lwz reg,0(t1)#endif /* Load r10 from current_thread_info_set - clobbers r1 and r30 */#ifdef CONFIG_SMP#define GET_CURRENT_THREAD_INFO \ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ tophys (r30,r1) ;\ l.mfspr r10,r0,SPR_COREID ;\ l.slli r10,r10,2 ;\ l.add r30,r30,r10 ;\ /* r10: current_thread_info */ ;\ l.lwz r10,0(r30)#else#define GET_CURRENT_THREAD_INFO \ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ tophys (r30,r1) ;\ /* r10: current_thread_info */ ;\ l.lwz r10,0(r30)#endif /* * DSCR: this is a common hook for handling exceptions. it will save * the needed registers, set up stack and pointer to current * then jump to the handler while enabling MMU * * PRMS: handler - a function to jump to. it has to save the * remaining registers to kernel stack, call * appropriate arch-independant exception handler * and finaly jump to ret_from_except * * PREQ: unchanged state from the time exception happened * * POST: SAVED the following registers original value * to the new created exception frame pointed to by r1 * * r1 - ksp pointing to the new (exception) frame * r4 - EEAR exception EA * r10 - current pointing to current_thread_info struct * r12 - syscall 0, since we didn't come from syscall * r30 - handler address of the handler we'll jump to * * handler has to save remaining registers to the exception * ksp frame *before* tainting them! * * NOTE: this function is not reentrant per se. reentrancy is guaranteed * by processor disabling all exceptions/interrupts when exception * accours. * * OPTM: no need to make it so wasteful to extract ksp when in user mode */ #define EXCEPTION_HANDLE(handler) \ EXCEPTION_T_STORE_GPR30 ;\ l.mfspr r30,r0,SPR_ESR_BASE ;\ l.andi r30,r30,SPR_SR_SM ;\ l.sfeqi r30,0 ;\ EXCEPTION_T_STORE_GPR10 ;\ l.bnf 2f /* kernel_mode */ ;\ EXCEPTION_T_STORE_SP /* delay slot */ ;\1: /* user_mode: */ ;\ GET_CURRENT_THREAD_INFO ;\ tophys (r30,r10) ;\ l.lwz r1,(TI_KSP)(r30) ;\ /* fall through */ ;\2: /* kernel_mode: */ ;\ /* create new stack frame, save only needed gprs */ ;\ /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\ /* r12: temp, syscall indicator */ ;\ l.addi r1,r1,-(INT_FRAME_SIZE) ;\ /* r1 is KSP, r30 is __pa(KSP) */ ;\ tophys (r30,r1) ;\ l.sw PT_GPR12(r30),r12 ;\ /* r4 use for tmp before EA */ ;\ l.mfspr r12,r0,SPR_EPCR_BASE ;\ l.sw PT_PC(r30),r12 ;\ l.mfspr r12,r0,SPR_ESR_BASE ;\ l.sw PT_SR(r30),r12 ;\ /* save r30 */ ;\ EXCEPTION_T_LOAD_GPR30(r12) ;\ l.sw PT_GPR30(r30),r12 ;\ /* save r10 as was prior to exception */ ;\ EXCEPTION_T_LOAD_GPR10(r12) ;\ l.sw PT_GPR10(r30),r12 ;\ /* save PT_SP as was prior to exception */ ;\ EXCEPTION_T_LOAD_SP(r12) ;\ l.sw PT_SP(r30),r12 ;\ /* save exception r4, set r4 = EA */ ;\ l.sw PT_GPR4(r30),r4 ;\ l.mfspr r4,r0,SPR_EEAR_BASE ;\ /* r12 == 1 if we come from syscall */ ;\ CLEAR_GPR(r12) ;\ /* ----- turn on MMU ----- */ ;\ /* Carry DSX into exception SR */ ;\ l.mfspr r30,r0,SPR_SR ;\ l.andi r30,r30,SPR_SR_DSX ;\ l.ori r30,r30,(EXCEPTION_SR) ;\ l.mtspr r0,r30,SPR_ESR_BASE ;\ /* r30: EA address of handler */ ;\ LOAD_SYMBOL_2_GPR(r30,handler) ;\ l.mtspr r0,r30,SPR_EPCR_BASE ;\ l.rfe /* * this doesn't work * * * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION * #define UNHANDLED_EXCEPTION(handler) \ * l.ori r3,r0,0x1 ;\ * l.mtspr r0,r3,SPR_SR ;\ * l.movhi r3,hi(0xf0000100) ;\ * l.ori r3,r3,lo(0xf0000100) ;\ * l.jr r3 ;\ * l.nop 1 * * #endif */ /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just * a bit more carefull (if we have a PT_SP or current pointer * corruption) and set them up from 'current_set' * */#define UNHANDLED_EXCEPTION(handler) \ EXCEPTION_T_STORE_GPR30 ;\ EXCEPTION_T_STORE_GPR10 ;\ EXCEPTION_T_STORE_SP ;\ /* temporary store r3, r9 into r1, r10 */ ;\ l.addi r1,r3,0x0 ;\ l.addi r10,r9,0x0 ;\ LOAD_SYMBOL_2_GPR(r9,_string_unhandled_exception) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ l.mfspr r3,r0,SPR_NPC ;\ l.jal _emergency_print_nr ;\ l.andi r3,r3,0x1f00 ;\ LOAD_SYMBOL_2_GPR(r9,_string_epc_prefix) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ l.jal _emergency_print_nr ;\ l.mfspr r3,r0,SPR_EPCR_BASE ;\ LOAD_SYMBOL_2_GPR(r9,_string_nl) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ /* end of printing */ ;\ l.addi r3,r1,0x0 ;\ l.addi r9,r10,0x0 ;\ /* extract current, ksp from current_set */ ;\ LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\ LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\ /* create new stack frame, save only needed gprs */ ;\ /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\ /* r12: temp, syscall indicator, r13 temp */ ;\ l.addi r1,r1,-(INT_FRAME_SIZE) ;\ /* r1 is KSP, r30 is __pa(KSP) */ ;\ tophys (r30,r1) ;\ l.sw PT_GPR12(r30),r12 ;\ l.mfspr r12,r0,SPR_EPCR_BASE ;\ l.sw PT_PC(r30),r12 ;\ l.mfspr r12,r0,SPR_ESR_BASE ;\ l.sw PT_SR(r30),r12 ;\ /* save r31 */ ;\ EXCEPTION_T_LOAD_GPR30(r12) ;\ l.sw PT_GPR30(r30),r12 ;\ /* save r10 as was prior to exception */ ;\ EXCEPTION_T_LOAD_GPR10(r12) ;\ l.sw PT_GPR10(r30),r12 ;\ /* save PT_SP as was prior to exception */ ;\ EXCEPTION_T_LOAD_SP(r12) ;\ l.sw PT_SP(r30),r12 ;\ l.sw PT_GPR13(r30),r13 ;\ /* --> */ ;\ /* save exception r4, set r4 = EA */ ;\ l.sw PT_GPR4(r30),r4 ;\ l.mfspr r4,r0,SPR_EEAR_BASE ;\ /* r12 == 1 if we come from syscall */ ;\ CLEAR_GPR(r12) ;\ /* ----- play a MMU trick ----- */ ;\ l.ori r30,r0,(EXCEPTION_SR) ;\ l.mtspr r0,r30,SPR_ESR_BASE ;\ /* r31: EA address of handler */ ;\ LOAD_SYMBOL_2_GPR(r30,handler) ;\ l.mtspr r0,r30,SPR_EPCR_BASE ;\ l.rfe /* =====================================================[ exceptions] === */ __HEAD /* ---[ 0x100: RESET exception ]----------------------------------------- */ .org 0x100 /* Jump to .init code at _start which lives in the .head section * and will be discarded after boot. */ LOAD_SYMBOL_2_GPR(r15, _start) tophys (r13,r15) /* MMU disabled */ l.jr r13 l.nop /* ---[ 0x200: BUS exception ]------------------------------------------- */ .org 0x200_dispatch_bus_fault: EXCEPTION_HANDLE(_bus_fault_handler) /* ---[ 0x300: Data Page Fault exception ]------------------------------- */ .org 0x300_dispatch_do_dpage_fault:// totaly disable timer interrupt// l.mtspr r0,r0,SPR_TTMR// DEBUG_TLB_PROBE(0x300)// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300) EXCEPTION_HANDLE(_data_page_fault_handler) /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ .org 0x400_dispatch_do_ipage_fault:// totaly disable timer interrupt// l.mtspr r0,r0,SPR_TTMR// DEBUG_TLB_PROBE(0x400)// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400) EXCEPTION_HANDLE(_insn_page_fault_handler) /* ---[ 0x500: Timer exception ]----------------------------------------- */ .org 0x500 EXCEPTION_HANDLE(_timer_handler) /* ---[ 0x600: Alignment exception ]------------------------------------- */ .org 0x600 EXCEPTION_HANDLE(_alignment_handler) /* ---[ 0x700: Illegal insn exception ]---------------------------------- */ .org 0x700 EXCEPTION_HANDLE(_illegal_instruction_handler) /* ---[ 0x800: External interrupt exception ]---------------------------- */ .org 0x800 EXCEPTION_HANDLE(_external_irq_handler) /* ---[ 0x900: DTLB miss exception ]------------------------------------- */ .org 0x900 l.j boot_dtlb_miss_handler l.nop /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ .org 0xa00 l.j boot_itlb_miss_handler l.nop /* ---[ 0xb00: Range exception ]----------------------------------------- */ .org 0xb00 UNHANDLED_EXCEPTION(_vector_0xb00) /* ---[ 0xc00: Syscall exception ]--------------------------------------- */ .org 0xc00 EXCEPTION_HANDLE(_sys_call_handler) /* ---[ 0xd00: Floating point exception ]-------------------------------- */ .org 0xd00 EXCEPTION_HANDLE(_fpe_trap_handler) /* ---[ 0xe00: Trap exception ]------------------------------------------ */ .org 0xe00// UNHANDLED_EXCEPTION(_vector_0xe00) EXCEPTION_HANDLE(_trap_handler) /* ---[ 0xf00: Reserved exception ]-------------------------------------- */ .org 0xf00 UNHANDLED_EXCEPTION(_vector_0xf00) /* ---[ 0x1000: Reserved exception ]------------------------------------- */ .org 0x1000 UNHANDLED_EXCEPTION(_vector_0x1000) /* ---[ 0x1100: Reserved exception ]------------------------------------- */ .org 0x1100 UNHANDLED_EXCEPTION(_vector_0x1100) /* ---[ 0x1200: Reserved exception ]------------------------------------- */ .org 0x1200 UNHANDLED_EXCEPTION(_vector_0x1200) /* ---[ 0x1300: Reserved exception ]------------------------------------- */ .org 0x1300 UNHANDLED_EXCEPTION(_vector_0x1300) /* ---[ 0x1400: Reserved exception ]------------------------------------- */ .org 0x1400 UNHANDLED_EXCEPTION(_vector_0x1400) /* ---[ 0x1500: Reserved exception ]------------------------------------- */ .org 0x1500 UNHANDLED_EXCEPTION(_vector_0x1500) /* ---[ 0x1600: Reserved exception ]------------------------------------- */ .org 0x1600 UNHANDLED_EXCEPTION(_vector_0x1600) /* ---[ 0x1700: Reserved exception ]------------------------------------- */ .org 0x1700 UNHANDLED_EXCEPTION(_vector_0x1700) /* ---[ 0x1800: Reserved exception ]------------------------------------- */ .org 0x1800 UNHANDLED_EXCEPTION(_vector_0x1800) /* ---[ 0x1900: Reserved exception ]------------------------------------- */ .org 0x1900 UNHANDLED_EXCEPTION(_vector_0x1900) /* ---[ 0x1a00: Reserved exception ]------------------------------------- */ .org 0x1a00 UNHANDLED_EXCEPTION(_vector_0x1a00) /* ---[ 0x1b00: Reserved exception ]------------------------------------- */ .org 0x1b00 UNHANDLED_EXCEPTION(_vector_0x1b00) /* ---[ 0x1c00: Reserved exception ]------------------------------------- */ .org 0x1c00 UNHANDLED_EXCEPTION(_vector_0x1c00) /* ---[ 0x1d00: Reserved exception ]------------------------------------- */ .org 0x1d00 UNHANDLED_EXCEPTION(_vector_0x1d00) /* ---[ 0x1e00: Reserved exception ]------------------------------------- */ .org 0x1e00 UNHANDLED_EXCEPTION(_vector_0x1e00)Lines 1–500 of 1566. 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/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * OpenRISC head.S * * Linux architectural port borrowing liberally from similar works of * others. All original copyrights apply as per the original source * declaration. * * Modifications for the OpenRISC architecture: * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> */ #include <linux/linkage.h> #include <linux/threads.h> #include <linux/errno.h> #include <linux/init.h> #include <linux/serial_reg.h> #include <linux/pgtable.h> #include <asm/processor.h> #include <asm/page.h> #include <asm/mmu.h> #include <asm/thread_info.h> #include <asm/cache.h> #include <asm/spr_defs.h> #include <asm/asm-offsets.h> #include <linux/of_fdt.h> #define tophys(rd,rs) \ l.movhi rd,hi(-KERNELBASE) ;\ l.add rd,rd,rs #define CLEAR_GPR(gpr) \ l.movhi gpr,0x0 #define LOAD_SYMBOL_2_GPR(gpr,symbol) \ l.movhi gpr,hi(symbol) ;\ l.ori gpr,gpr,lo(symbol) #define UART_BASE_ADD 0x90000000 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM) #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM) /* ============================================[ tmp store locations ]=== */ #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32) /* * emergency_print temporary stores */ #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14) #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14) #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15) #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15) #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16) #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16) #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7) #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7) #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8) #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8) #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9) #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0) #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0) #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0) #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0) #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0) #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0) #endif /* * TLB miss handlers temorary stores */ #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2) #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2) #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3) #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3) #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4) #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4) #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5) #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5) #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6) #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0) #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0) #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0) #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0) #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0) #endif /* * EXCEPTION_HANDLE temporary stores */ #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30) #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30) #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10) #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10) #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1) #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1) #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0) #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0) #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0) #endif /* =========================================================[ macros ]=== */ #ifdef CONFIG_SMP #define GET_CURRENT_PGD(reg,t1) \ LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ l.mfspr t1,r0,SPR_COREID ;\ l.slli t1,t1,2 ;\ l.add reg,reg,t1 ;\ tophys (t1,reg) ;\ l.lwz reg,0(t1) #else #define GET_CURRENT_PGD(reg,t1) \ LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ tophys (t1,reg) ;\ l.lwz reg,0(t1) #endif /* Load r10 from current_thread_info_set - clobbers r1 and r30 */ #ifdef CONFIG_SMP #define GET_CURRENT_THREAD_INFO \ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ tophys (r30,r1) ;\ l.mfspr r10,r0,SPR_COREID ;\ l.slli r10,r10,2 ;\ l.add r30,r30,r10 ;\ /* r10: current_thread_info */ ;\ l.lwz r10,0(r30) #else #define GET_CURRENT_THREAD_INFO \ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ tophys (r30,r1) ;\ /* r10: current_thread_info */ ;\ l.lwz r10,0(r30) #endif /* * DSCR: this is a common hook for handling exceptions. it will save * the needed registers, set up stack and pointer to current * then jump to the handler while enabling MMU * * PRMS: handler - a function to jump to. it has to save the * remaining registers to kernel stack, call * appropriate arch-independant exception handler * and finaly jump to ret_from_except * * PREQ: unchanged state from the time exception happened * * POST: SAVED the following registers original value * to the new created exception frame pointed to by r1 * * r1 - ksp pointing to the new (exception) frame * r4 - EEAR exception EA * r10 - current pointing to current_thread_info struct * r12 - syscall 0, since we didn't come from syscall * r30 - handler address of the handler we'll jump to * * handler has to save remaining registers to the exception * ksp frame *before* tainting them! * * NOTE: this function is not reentrant per se. reentrancy is guaranteed * by processor disabling all exceptions/interrupts when exception * accours. * * OPTM: no need to make it so wasteful to extract ksp when in user mode */ #define EXCEPTION_HANDLE(handler) \ EXCEPTION_T_STORE_GPR30 ;\ l.mfspr r30,r0,SPR_ESR_BASE ;\ l.andi r30,r30,SPR_SR_SM ;\ l.sfeqi r30,0 ;\ EXCEPTION_T_STORE_GPR10 ;\ l.bnf 2f /* kernel_mode */ ;\ EXCEPTION_T_STORE_SP /* delay slot */ ;\ 1: /* user_mode: */ ;\ GET_CURRENT_THREAD_INFO ;\ tophys (r30,r10) ;\ l.lwz r1,(TI_KSP)(r30) ;\ /* fall through */ ;\ 2: /* kernel_mode: */ ;\ /* create new stack frame, save only needed gprs */ ;\ /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\ /* r12: temp, syscall indicator */ ;\ l.addi r1,r1,-(INT_FRAME_SIZE) ;\ /* r1 is KSP, r30 is __pa(KSP) */ ;\ tophys (r30,r1) ;\ l.sw PT_GPR12(r30),r12 ;\ /* r4 use for tmp before EA */ ;\ l.mfspr r12,r0,SPR_EPCR_BASE ;\ l.sw PT_PC(r30),r12 ;\ l.mfspr r12,r0,SPR_ESR_BASE ;\ l.sw PT_SR(r30),r12 ;\ /* save r30 */ ;\ EXCEPTION_T_LOAD_GPR30(r12) ;\ l.sw PT_GPR30(r30),r12 ;\ /* save r10 as was prior to exception */ ;\ EXCEPTION_T_LOAD_GPR10(r12) ;\ l.sw PT_GPR10(r30),r12 ;\ /* save PT_SP as was prior to exception */ ;\ EXCEPTION_T_LOAD_SP(r12) ;\ l.sw PT_SP(r30),r12 ;\ /* save exception r4, set r4 = EA */ ;\ l.sw PT_GPR4(r30),r4 ;\ l.mfspr r4,r0,SPR_EEAR_BASE ;\ /* r12 == 1 if we come from syscall */ ;\ CLEAR_GPR(r12) ;\ /* ----- turn on MMU ----- */ ;\ /* Carry DSX into exception SR */ ;\ l.mfspr r30,r0,SPR_SR ;\ l.andi r30,r30,SPR_SR_DSX ;\ l.ori r30,r30,(EXCEPTION_SR) ;\ l.mtspr r0,r30,SPR_ESR_BASE ;\ /* r30: EA address of handler */ ;\ LOAD_SYMBOL_2_GPR(r30,handler) ;\ l.mtspr r0,r30,SPR_EPCR_BASE ;\ l.rfe /* * this doesn't work * * * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION * #define UNHANDLED_EXCEPTION(handler) \ * l.ori r3,r0,0x1 ;\ * l.mtspr r0,r3,SPR_SR ;\ * l.movhi r3,hi(0xf0000100) ;\ * l.ori r3,r3,lo(0xf0000100) ;\ * l.jr r3 ;\ * l.nop 1 * * #endif */ /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just * a bit more carefull (if we have a PT_SP or current pointer * corruption) and set them up from 'current_set' * */ #define UNHANDLED_EXCEPTION(handler) \ EXCEPTION_T_STORE_GPR30 ;\ EXCEPTION_T_STORE_GPR10 ;\ EXCEPTION_T_STORE_SP ;\ /* temporary store r3, r9 into r1, r10 */ ;\ l.addi r1,r3,0x0 ;\ l.addi r10,r9,0x0 ;\ LOAD_SYMBOL_2_GPR(r9,_string_unhandled_exception) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ l.mfspr r3,r0,SPR_NPC ;\ l.jal _emergency_print_nr ;\ l.andi r3,r3,0x1f00 ;\ LOAD_SYMBOL_2_GPR(r9,_string_epc_prefix) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ l.jal _emergency_print_nr ;\ l.mfspr r3,r0,SPR_EPCR_BASE ;\ LOAD_SYMBOL_2_GPR(r9,_string_nl) ;\ tophys (r3,r9) ;\ l.jal _emergency_print ;\ l.nop ;\ /* end of printing */ ;\ l.addi r3,r1,0x0 ;\ l.addi r9,r10,0x0 ;\ /* extract current, ksp from current_set */ ;\ LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\ LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\ /* create new stack frame, save only needed gprs */ ;\ /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\ /* r12: temp, syscall indicator, r13 temp */ ;\ l.addi r1,r1,-(INT_FRAME_SIZE) ;\ /* r1 is KSP, r30 is __pa(KSP) */ ;\ tophys (r30,r1) ;\ l.sw PT_GPR12(r30),r12 ;\ l.mfspr r12,r0,SPR_EPCR_BASE ;\ l.sw PT_PC(r30),r12 ;\ l.mfspr r12,r0,SPR_ESR_BASE ;\ l.sw PT_SR(r30),r12 ;\ /* save r31 */ ;\ EXCEPTION_T_LOAD_GPR30(r12) ;\ l.sw PT_GPR30(r30),r12 ;\ /* save r10 as was prior to exception */ ;\ EXCEPTION_T_LOAD_GPR10(r12) ;\ l.sw PT_GPR10(r30),r12 ;\ /* save PT_SP as was prior to exception */ ;\ EXCEPTION_T_LOAD_SP(r12) ;\ l.sw PT_SP(r30),r12 ;\ l.sw PT_GPR13(r30),r13 ;\ /* --> */ ;\ /* save exception r4, set r4 = EA */ ;\ l.sw PT_GPR4(r30),r4 ;\ l.mfspr r4,r0,SPR_EEAR_BASE ;\ /* r12 == 1 if we come from syscall */ ;\ CLEAR_GPR(r12) ;\ /* ----- play a MMU trick ----- */ ;\ l.ori r30,r0,(EXCEPTION_SR) ;\ l.mtspr r0,r30,SPR_ESR_BASE ;\ /* r31: EA address of handler */ ;\ LOAD_SYMBOL_2_GPR(r30,handler) ;\ l.mtspr r0,r30,SPR_EPCR_BASE ;\ l.rfe /* =====================================================[ exceptions] === */ __HEAD /* ---[ 0x100: RESET exception ]----------------------------------------- */ .org 0x100 /* Jump to .init code at _start which lives in the .head section * and will be discarded after boot. */ LOAD_SYMBOL_2_GPR(r15, _start) tophys (r13,r15) /* MMU disabled */ l.jr r13 l.nop /* ---[ 0x200: BUS exception ]------------------------------------------- */ .org 0x200 _dispatch_bus_fault: EXCEPTION_HANDLE(_bus_fault_handler) /* ---[ 0x300: Data Page Fault exception ]------------------------------- */ .org 0x300 _dispatch_do_dpage_fault: // totaly disable timer interrupt // l.mtspr r0,r0,SPR_TTMR // DEBUG_TLB_PROBE(0x300) // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300) EXCEPTION_HANDLE(_data_page_fault_handler) /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ .org 0x400 _dispatch_do_ipage_fault: // totaly disable timer interrupt // l.mtspr r0,r0,SPR_TTMR // DEBUG_TLB_PROBE(0x400) // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400) EXCEPTION_HANDLE(_insn_page_fault_handler) /* ---[ 0x500: Timer exception ]----------------------------------------- */ .org 0x500 EXCEPTION_HANDLE(_timer_handler) /* ---[ 0x600: Alignment exception ]------------------------------------- */ .org 0x600 EXCEPTION_HANDLE(_alignment_handler) /* ---[ 0x700: Illegal insn exception ]---------------------------------- */ .org 0x700 EXCEPTION_HANDLE(_illegal_instruction_handler) /* ---[ 0x800: External interrupt exception ]---------------------------- */ .org 0x800 EXCEPTION_HANDLE(_external_irq_handler) /* ---[ 0x900: DTLB miss exception ]------------------------------------- */ .org 0x900 l.j boot_dtlb_miss_handler l.nop /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ .org 0xa00 l.j boot_itlb_miss_handler l.nop /* ---[ 0xb00: Range exception ]----------------------------------------- */ .org 0xb00 UNHANDLED_EXCEPTION(_vector_0xb00) /* ---[ 0xc00: Syscall exception ]--------------------------------------- */ .org 0xc00 EXCEPTION_HANDLE(_sys_call_handler) /* ---[ 0xd00: Floating point exception ]-------------------------------- */ .org 0xd00 EXCEPTION_HANDLE(_fpe_trap_handler) /* ---[ 0xe00: Trap exception ]------------------------------------------ */ .org 0xe00 // UNHANDLED_EXCEPTION(_vector_0xe00) EXCEPTION_HANDLE(_trap_handler) /* ---[ 0xf00: Reserved exception ]-------------------------------------- */ .org 0xf00 UNHANDLED_EXCEPTION(_vector_0xf00) /* ---[ 0x1000: Reserved exception ]------------------------------------- */ .org 0x1000 UNHANDLED_EXCEPTION(_vector_0x1000) /* ---[ 0x1100: Reserved exception ]------------------------------------- */ .org 0x1100 UNHANDLED_EXCEPTION(_vector_0x1100) /* ---[ 0x1200: Reserved exception ]------------------------------------- */ .org 0x1200 UNHANDLED_EXCEPTION(_vector_0x1200) /* ---[ 0x1300: Reserved exception ]------------------------------------- */ .org 0x1300 UNHANDLED_EXCEPTION(_vector_0x1300) /* ---[ 0x1400: Reserved exception ]------------------------------------- */ .org 0x1400 UNHANDLED_EXCEPTION(_vector_0x1400) /* ---[ 0x1500: Reserved exception ]------------------------------------- */ .org 0x1500 UNHANDLED_EXCEPTION(_vector_0x1500) /* ---[ 0x1600: Reserved exception ]------------------------------------- */ .org 0x1600 UNHANDLED_EXCEPTION(_vector_0x1600) /* ---[ 0x1700: Reserved exception ]------------------------------------- */ .org 0x1700 UNHANDLED_EXCEPTION(_vector_0x1700) /* ---[ 0x1800: Reserved exception ]------------------------------------- */ .org 0x1800 UNHANDLED_EXCEPTION(_vector_0x1800) /* ---[ 0x1900: Reserved exception ]------------------------------------- */ .org 0x1900 UNHANDLED_EXCEPTION(_vector_0x1900) /* ---[ 0x1a00: Reserved exception ]------------------------------------- */ .org 0x1a00 UNHANDLED_EXCEPTION(_vector_0x1a00) /* ---[ 0x1b00: Reserved exception ]------------------------------------- */ .org 0x1b00 UNHANDLED_EXCEPTION(_vector_0x1b00) /* ---[ 0x1c00: Reserved exception ]------------------------------------- */ .org 0x1c00 UNHANDLED_EXCEPTION(_vector_0x1c00) /* ---[ 0x1d00: Reserved exception ]------------------------------------- */ .org 0x1d00 UNHANDLED_EXCEPTION(_vector_0x1d00) /* ---[ 0x1e00: Reserved exception ]------------------------------------- */ .org 0x1e00 UNHANDLED_EXCEPTION(_vector_0x1e00)