/* SPDX-License-Identifier: GPL-2.0-or-later *//* * OPAL API definitions. * * Copyright 2011-2015 IBM Corp. */ #ifndef __OPAL_API_H#define __OPAL_API_H /****** OPAL APIs ******/ /* Return codes */#define OPAL_SUCCESS		0#define OPAL_PARAMETER		-1#define OPAL_BUSY		-2#define OPAL_PARTIAL		-3#define OPAL_CONSTRAINED	-4#define OPAL_CLOSED		-5#define OPAL_HARDWARE		-6#define OPAL_UNSUPPORTED	-7#define OPAL_PERMISSION		-8#define OPAL_NO_MEM		-9#define OPAL_RESOURCE		-10#define OPAL_INTERNAL_ERROR	-11#define OPAL_BUSY_EVENT		-12#define OPAL_HARDWARE_FROZEN	-13#define OPAL_WRONG_STATE	-14#define OPAL_ASYNC_COMPLETION	-15#define OPAL_EMPTY		-16#define OPAL_I2C_TIMEOUT	-17#define OPAL_I2C_INVALID_CMD	-18#define OPAL_I2C_LBUS_PARITY	-19#define OPAL_I2C_BKEND_OVERRUN	-20#define OPAL_I2C_BKEND_ACCESS	-21#define OPAL_I2C_ARBT_LOST	-22#define OPAL_I2C_NACK_RCVD	-23#define OPAL_I2C_STOP_ERR	-24#define OPAL_XIVE_PROVISIONING	-31#define OPAL_XIVE_FREE_ACTIVE	-32#define OPAL_TIMEOUT		-33 /* API Tokens (in r0) */#define OPAL_INVALID_CALL		       -1#define OPAL_TEST				0#define OPAL_CONSOLE_WRITE			1#define OPAL_CONSOLE_READ			2#define OPAL_RTC_READ				3#define OPAL_RTC_WRITE				4#define OPAL_CEC_POWER_DOWN			5#define OPAL_CEC_REBOOT				6#define OPAL_READ_NVRAM				7#define OPAL_WRITE_NVRAM			8#define OPAL_HANDLE_INTERRUPT			9#define OPAL_POLL_EVENTS			10#define OPAL_PCI_SET_HUB_TCE_MEMORY		11#define OPAL_PCI_SET_PHB_TCE_MEMORY		12#define OPAL_PCI_CONFIG_READ_BYTE		13#define OPAL_PCI_CONFIG_READ_HALF_WORD  	14#define OPAL_PCI_CONFIG_READ_WORD		15#define OPAL_PCI_CONFIG_WRITE_BYTE		16#define OPAL_PCI_CONFIG_WRITE_HALF_WORD		17#define OPAL_PCI_CONFIG_WRITE_WORD		18#define OPAL_SET_XIVE				19#define OPAL_GET_XIVE				20#define OPAL_GET_COMPLETION_TOKEN_STATUS	21 /* obsolete */#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER	22#define OPAL_PCI_EEH_FREEZE_STATUS		23#define OPAL_PCI_SHPC				24#define OPAL_CONSOLE_WRITE_BUFFER_SPACE		25#define OPAL_PCI_EEH_FREEZE_CLEAR		26#define OPAL_PCI_PHB_MMIO_ENABLE		27#define OPAL_PCI_SET_PHB_MEM_WINDOW		28#define OPAL_PCI_MAP_PE_MMIO_WINDOW		29#define OPAL_PCI_SET_PHB_TABLE_MEMORY		30#define OPAL_PCI_SET_PE				31#define OPAL_PCI_SET_PELTV			32#define OPAL_PCI_SET_MVE			33#define OPAL_PCI_SET_MVE_ENABLE			34#define OPAL_PCI_GET_XIVE_REISSUE		35#define OPAL_PCI_SET_XIVE_REISSUE		36#define OPAL_PCI_SET_XIVE_PE			37#define OPAL_GET_XIVE_SOURCE			38#define OPAL_GET_MSI_32				39#define OPAL_GET_MSI_64				40#define OPAL_START_CPU				41#define OPAL_QUERY_CPU_STATUS			42#define OPAL_WRITE_OPPANEL			43 /* unimplemented */#define OPAL_PCI_MAP_PE_DMA_WINDOW		44#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL		45#define OPAL_PCI_RESET				49#define OPAL_PCI_GET_HUB_DIAG_DATA		50#define OPAL_PCI_GET_PHB_DIAG_DATA		51#define OPAL_PCI_FENCE_PHB			52#define OPAL_PCI_REINIT				53#define OPAL_PCI_MASK_PE_ERROR			54#define OPAL_SET_SLOT_LED_STATUS		55#define OPAL_GET_EPOW_STATUS			56#define OPAL_SET_SYSTEM_ATTENTION_LED		57#define OPAL_RESERVED1				58#define OPAL_RESERVED2				59#define OPAL_PCI_NEXT_ERROR			60#define OPAL_PCI_EEH_FREEZE_STATUS2		61#define OPAL_PCI_POLL				62#define OPAL_PCI_MSI_EOI			63#define OPAL_PCI_GET_PHB_DIAG_DATA2		64#define OPAL_XSCOM_READ				65#define OPAL_XSCOM_WRITE			66#define OPAL_LPC_READ				67#define OPAL_LPC_WRITE				68#define OPAL_RETURN_CPU				69#define OPAL_REINIT_CPUS			70#define OPAL_ELOG_READ				71#define OPAL_ELOG_WRITE				72#define OPAL_ELOG_ACK				73#define OPAL_ELOG_RESEND			74#define OPAL_ELOG_SIZE				75#define OPAL_FLASH_VALIDATE			76#define OPAL_FLASH_MANAGE			77#define OPAL_FLASH_UPDATE			78#define OPAL_RESYNC_TIMEBASE			79#define OPAL_CHECK_TOKEN			80#define OPAL_DUMP_INIT				81#define OPAL_DUMP_INFO				82#define OPAL_DUMP_READ				83#define OPAL_DUMP_ACK				84#define OPAL_GET_MSG				85#define OPAL_CHECK_ASYNC_COMPLETION		86#define OPAL_SYNC_HOST_REBOOT			87#define OPAL_SENSOR_READ			88#define OPAL_GET_PARAM				89#define OPAL_SET_PARAM				90#define OPAL_DUMP_RESEND			91#define OPAL_ELOG_SEND				92	/* Deprecated */#define OPAL_PCI_SET_PHB_CAPI_MODE		93#define OPAL_DUMP_INFO2				94#define OPAL_WRITE_OPPANEL_ASYNC		95#define OPAL_PCI_ERR_INJECT			96#define OPAL_PCI_EEH_FREEZE_SET			97#define OPAL_HANDLE_HMI				98#define OPAL_CONFIG_CPU_IDLE_STATE		99#define OPAL_SLW_SET_REG			100#define OPAL_REGISTER_DUMP_REGION		101#define OPAL_UNREGISTER_DUMP_REGION		102#define OPAL_WRITE_TPO				103#define OPAL_READ_TPO				104#define OPAL_GET_DPO_STATUS			105#define OPAL_OLD_I2C_REQUEST			106	/* Deprecated */#define OPAL_IPMI_SEND				107#define OPAL_IPMI_RECV				108#define OPAL_I2C_REQUEST			109#define OPAL_FLASH_READ				110#define OPAL_FLASH_WRITE			111#define OPAL_FLASH_ERASE			112#define OPAL_PRD_MSG				113#define OPAL_LEDS_GET_INDICATOR			114#define OPAL_LEDS_SET_INDICATOR			115#define OPAL_CEC_REBOOT2			116#define OPAL_CONSOLE_FLUSH			117#define OPAL_GET_DEVICE_TREE			118#define OPAL_PCI_GET_PRESENCE_STATE		119#define OPAL_PCI_GET_POWER_STATE		120#define OPAL_PCI_SET_POWER_STATE		121#define OPAL_INT_GET_XIRR			122#define	OPAL_INT_SET_CPPR			123#define OPAL_INT_EOI				124#define OPAL_INT_SET_MFRR			125#define OPAL_PCI_TCE_KILL			126#define OPAL_NMMU_SET_PTCR			127#define OPAL_XIVE_RESET				128#define OPAL_XIVE_GET_IRQ_INFO			129#define OPAL_XIVE_GET_IRQ_CONFIG		130#define OPAL_XIVE_SET_IRQ_CONFIG		131#define OPAL_XIVE_GET_QUEUE_INFO		132#define OPAL_XIVE_SET_QUEUE_INFO		133#define OPAL_XIVE_DONATE_PAGE			134#define OPAL_XIVE_ALLOCATE_VP_BLOCK		135#define OPAL_XIVE_FREE_VP_BLOCK			136#define OPAL_XIVE_GET_VP_INFO			137#define OPAL_XIVE_SET_VP_INFO			138#define OPAL_XIVE_ALLOCATE_IRQ			139#define OPAL_XIVE_FREE_IRQ			140#define OPAL_XIVE_SYNC				141#define OPAL_XIVE_DUMP				142#define OPAL_XIVE_GET_QUEUE_STATE		143#define OPAL_XIVE_SET_QUEUE_STATE		144#define OPAL_SIGNAL_SYSTEM_RESET		145#define OPAL_NPU_INIT_CONTEXT			146#define OPAL_NPU_DESTROY_CONTEXT		147#define OPAL_NPU_MAP_LPAR			148#define OPAL_IMC_COUNTERS_INIT			149#define OPAL_IMC_COUNTERS_START			150#define OPAL_IMC_COUNTERS_STOP			151#define OPAL_GET_POWERCAP			152#define OPAL_SET_POWERCAP			153#define OPAL_GET_POWER_SHIFT_RATIO		154#define OPAL_SET_POWER_SHIFT_RATIO		155#define OPAL_SENSOR_GROUP_CLEAR			156#define OPAL_PCI_SET_P2P			157#define OPAL_QUIESCE				158#define OPAL_NPU_SPA_SETUP			159#define OPAL_NPU_SPA_CLEAR_CACHE		160#define OPAL_NPU_TL_SET				161#define OPAL_SENSOR_READ_U64			162#define OPAL_SENSOR_GROUP_ENABLE		163#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR		164#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR		165#define OPAL_HANDLE_HMI2			166#define	OPAL_NX_COPROC_INIT			167#define OPAL_XIVE_GET_VP_STATE			170#define OPAL_MPIPL_UPDATE			173#define OPAL_MPIPL_REGISTER_TAG			174#define OPAL_MPIPL_QUERY_TAG			175#define OPAL_SECVAR_GET				176#define OPAL_SECVAR_GET_NEXT			177#define OPAL_SECVAR_ENQUEUE_UPDATE		178#define OPAL_LAST				178 #define QUIESCE_HOLD			1 /* Spin all calls at entry */#define QUIESCE_REJECT			2 /* Fail all calls with OPAL_BUSY */#define QUIESCE_LOCK_BREAK		3 /* Set to ignore locks. */#define QUIESCE_RESUME			4 /* Un-quiesce */#define QUIESCE_RESUME_FAST_REBOOT	5 /* Un-quiesce, fast reboot */ /* Device tree flags */ /* * Flags set in power-mgmt nodes in device tree describing * idle states that are supported in the platform. */ #define OPAL_PM_TIMEBASE_STOP		0x00000002#define OPAL_PM_LOSE_HYP_CONTEXT	0x00002000#define OPAL_PM_LOSE_FULL_CONTEXT	0x00004000#define OPAL_PM_NAP_ENABLED		0x00010000#define OPAL_PM_SLEEP_ENABLED		0x00020000#define OPAL_PM_WINKLE_ENABLED		0x00040000#define OPAL_PM_SLEEP_ENABLED_ER1	0x00080000 /* with workaround */#define OPAL_PM_STOP_INST_FAST		0x00100000#define OPAL_PM_STOP_INST_DEEP		0x00200000 /* * OPAL_CONFIG_CPU_IDLE_STATE parameters */#define OPAL_CONFIG_IDLE_FASTSLEEP	1#define OPAL_CONFIG_IDLE_UNDO		0#define OPAL_CONFIG_IDLE_APPLY		1 #ifndef __ASSEMBLER__ /* Other enums */enum OpalFreezeState {	OPAL_EEH_STOPPED_NOT_FROZEN = 0,	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,	OPAL_EEH_STOPPED_DMA_FREEZE = 2,	OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,	OPAL_EEH_STOPPED_RESET = 4,	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6}; enum OpalEehFreezeActionToken {	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 	OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,	OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,	OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3}; enum OpalPciStatusToken {	OPAL_EEH_NO_ERROR	= 0,	OPAL_EEH_IOC_ERROR	= 1,	OPAL_EEH_PHB_ERROR	= 2,	OPAL_EEH_PE_ERROR	= 3,	OPAL_EEH_PE_MMIO_ERROR	= 4,	OPAL_EEH_PE_DMA_ERROR	= 5}; enum OpalPciErrorSeverity {	OPAL_EEH_SEV_NO_ERROR	= 0,	OPAL_EEH_SEV_IOC_DEAD	= 1,	OPAL_EEH_SEV_PHB_DEAD	= 2,	OPAL_EEH_SEV_PHB_FENCED	= 3,	OPAL_EEH_SEV_PE_ER	= 4,	OPAL_EEH_SEV_INF	= 5}; enum OpalErrinjectType {	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR	= 0,	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64	= 1,}; enum OpalErrinjectFunc {	/* IOA bus specific errors */	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR	= 0,	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA	= 1,	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR	= 2,	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA	= 3,	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR	= 4,	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA	= 5,	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR	= 6,	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA	= 7,	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR	= 8,	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA	= 9,	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR	= 10,	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA	= 11,	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR	= 12,	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA	= 13,	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER	= 14,	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET	= 15,	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR	= 16,	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA	= 17,	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER	= 18,	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET	= 19,}; enum OpalMmioWindowType {	OPAL_M32_WINDOW_TYPE = 1,	OPAL_M64_WINDOW_TYPE = 2,	OPAL_IO_WINDOW_TYPE  = 3}; enum OpalExceptionHandler {	OPAL_MACHINE_CHECK_HANDLER	    = 1,	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,	OPAL_SOFTPATCH_HANDLER		    = 3}; enum OpalPendingState {	OPAL_EVENT_OPAL_INTERNAL   = 0x1,	OPAL_EVENT_NVRAM	   = 0x2,	OPAL_EVENT_RTC		   = 0x4,	OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,	OPAL_EVENT_CONSOLE_INPUT   = 0x10,	OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,	OPAL_EVENT_ERROR_LOG	   = 0x40,	OPAL_EVENT_EPOW		   = 0x80,	OPAL_EVENT_LED_STATUS	   = 0x100,	OPAL_EVENT_PCI_ERROR	   = 0x200,	OPAL_EVENT_DUMP_AVAIL	   = 0x400,	OPAL_EVENT_MSG_PENDING	   = 0x800,}; enum OpalThreadStatus {	OPAL_THREAD_INACTIVE = 0x0,	OPAL_THREAD_STARTED = 0x1,	OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */}; enum OpalPciBusCompare {	OpalPciBusAny	= 0,	/* Any bus number match */	OpalPciBus3Bits	= 2,	/* Match top 3 bits of bus number */	OpalPciBus4Bits	= 3,	/* Match top 4 bits of bus number */	OpalPciBus5Bits	= 4,	/* Match top 5 bits of bus number */	OpalPciBus6Bits	= 5,	/* Match top 6 bits of bus number */	OpalPciBus7Bits	= 6,	/* Match top 7 bits of bus number */	OpalPciBusAll	= 7,	/* Match bus number exactly */}; enum OpalDeviceCompare {	OPAL_IGNORE_RID_DEVICE_NUMBER = 0,	OPAL_COMPARE_RID_DEVICE_NUMBER = 1}; enum OpalFuncCompare {	OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,	OPAL_COMPARE_RID_FUNCTION_NUMBER = 1}; enum OpalPeAction {	OPAL_UNMAP_PE = 0,	OPAL_MAP_PE = 1}; enum OpalPeltvAction {	OPAL_REMOVE_PE_FROM_DOMAIN = 0,	OPAL_ADD_PE_TO_DOMAIN = 1}; enum OpalMveEnableAction {	OPAL_DISABLE_MVE = 0,	OPAL_ENABLE_MVE = 1}; enum OpalM64Action {	OPAL_DISABLE_M64 = 0,	OPAL_ENABLE_M64_SPLIT = 1,	OPAL_ENABLE_M64_NON_SPLIT = 2}; enum OpalPciResetScope {	OPAL_RESET_PHB_COMPLETE		= 1,	OPAL_RESET_PCI_LINK		= 2,	OPAL_RESET_PHB_ERROR		= 3,	OPAL_RESET_PCI_HOT		= 4,	OPAL_RESET_PCI_FUNDAMENTAL	= 5,	OPAL_RESET_PCI_IODA_TABLE	= 6}; enum OpalPciReinitScope {	/*	 * Note: we chose values that do not overlap	 * OpalPciResetScope as OPAL v2 used the same	 * enum for both	 */	OPAL_REINIT_PCI_DEV = 1000}; enum OpalPciResetState {	OPAL_DEASSERT_RESET = 0,	OPAL_ASSERT_RESET   = 1}; enum OpalPciSlotPresence {	OPAL_PCI_SLOT_EMPTY	= 0,	OPAL_PCI_SLOT_PRESENT	= 1}; enum OpalPciSlotPower {	OPAL_PCI_SLOT_POWER_OFF	= 0,	OPAL_PCI_SLOT_POWER_ON	= 1,	OPAL_PCI_SLOT_OFFLINE	= 2,	OPAL_PCI_SLOT_ONLINE	= 3}; enum OpalSlotLedType {	OPAL_SLOT_LED_TYPE_ID = 0,	/* IDENTIFY LED */	OPAL_SLOT_LED_TYPE_FAULT = 1,	/* FAULT LED */	OPAL_SLOT_LED_TYPE_ATTN = 2,	/* System Attention LED */	OPAL_SLOT_LED_TYPE_MAX = 3}; enum OpalSlotLedState {	OPAL_SLOT_LED_STATE_OFF = 0,	/* LED is OFF */	OPAL_SLOT_LED_STATE_ON = 1	/* LED is ON */}; /* * Address cycle types for LPC accesses. These also correspond * to the content of the first cell of the "reg" property for * device nodes on the LPC bus */enum OpalLPCAddressType {	OPAL_LPC_MEM	= 0,	OPAL_LPC_IO	= 1,	OPAL_LPC_FW	= 2,}; enum opal_msg_type {	OPAL_MSG_ASYNC_COMP	= 0,	/* params[0] = token, params[1] = rc,					 * additional params function-specific					 */	OPAL_MSG_MEM_ERR	= 1,	OPAL_MSG_EPOW		= 2,	OPAL_MSG_SHUTDOWN	= 3,	/* params[0] = 1 reboot, 0 shutdown */	OPAL_MSG_HMI_EVT	= 4,	OPAL_MSG_DPO		= 5,	OPAL_MSG_PRD		= 6,	OPAL_MSG_OCC		= 7,	OPAL_MSG_PRD2		= 8,	OPAL_MSG_TYPE_MAX,}; struct opal_msg {	__be32 msg_type;	__be32 reserved;	__be64 params[8];}; /* System parameter permission */enum OpalSysparamPerm {	OPAL_SYSPARAM_READ  = 0x1,	OPAL_SYSPARAM_WRITE = 0x2,	OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),}; enum {	OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,}; struct opal_ipmi_msg {	uint8_t version;	uint8_t netfn;	uint8_t cmd;	uint8_t data[];}; /* FSP memory errors handling */enum OpalMemErr_Version {	OpalMemErr_V1 = 1,}; enum OpalMemErrType {	OPAL_MEM_ERR_TYPE_RESILIENCE	= 0,	OPAL_MEM_ERR_TYPE_DYN_DALLOC,}; /* Memory Reilience error type */

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