// SPDX-License-Identifier: GPL-2.0-or-later/* * Driver for OHCI 1394 controllers * * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> */ #include <linux/bitops.h>#include <linux/bug.h>#include <linux/compiler.h>#include <linux/delay.h>#include <linux/device.h>#include <linux/dma-mapping.h>#include <linux/firewire.h>#include <linux/firewire-constants.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/kernel.h>#include <linux/list.h>#include <linux/mm.h>#include <linux/module.h>#include <linux/moduleparam.h>#include <linux/mutex.h>#include <linux/pci.h>#include <linux/pci_ids.h>#include <linux/slab.h>#include <linux/spinlock.h>#include <linux/string.h>#include <linux/time.h>#include <linux/vmalloc.h>#include <linux/workqueue.h> #include <asm/byteorder.h>#include <asm/page.h> #ifdef CONFIG_PPC_PMAC#include <asm/pmac_feature.h>#endif #include "core.h"#include "ohci.h"#include "packet-header-definitions.h"#include "phy-packet-definitions.h" #include <trace/events/firewire.h> static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); #define CREATE_TRACE_POINTS#include <trace/events/firewire_ohci.h> #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) #define DESCRIPTOR_OUTPUT_MORE 0#define DESCRIPTOR_OUTPUT_LAST (1 << 12)#define DESCRIPTOR_INPUT_MORE (2 << 12)#define DESCRIPTOR_INPUT_LAST (3 << 12)#define DESCRIPTOR_STATUS (1 << 11)#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)#define DESCRIPTOR_PING (1 << 7)#define DESCRIPTOR_YY (1 << 6)#define DESCRIPTOR_NO_IRQ (0 << 4)#define DESCRIPTOR_IRQ_ERROR (1 << 4)#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)#define DESCRIPTOR_WAIT (3 << 0) #define DESCRIPTOR_CMD (0xf << 12) struct descriptor { __le16 req_count; __le16 control; __le32 data_address; __le32 branch_address; __le16 res_count; __le16 transfer_status;} __aligned(16); #define CONTROL_SET(regs) (regs)#define CONTROL_CLEAR(regs) ((regs) + 4)#define COMMAND_PTR(regs) ((regs) + 12)#define CONTEXT_MATCH(regs) ((regs) + 16) #define AR_BUFFER_SIZE (32*1024)#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)/* we need at least two pages for proper list management */#define AR_BUFFERS MAX(2, AR_BUFFERS_MIN) #define MAX_ASYNC_PAYLOAD 4096#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) struct ar_context { struct fw_ohci *ohci; struct page *pages[AR_BUFFERS]; void *buffer; dma_addr_t dma_addrs[AR_BUFFERS]; struct descriptor *descriptors; dma_addr_t descriptors_bus; void *pointer; unsigned int last_buffer_index; u32 regs; struct work_struct work;}; struct context; typedef int (*descriptor_callback_t)(struct context *ctx, struct descriptor *d, struct descriptor *last); /* * A buffer that contains a block of DMA-able coherent memory used for * storing a portion of a DMA descriptor program. */struct descriptor_buffer { struct list_head list; dma_addr_t buffer_bus; size_t buffer_size; size_t used; struct descriptor buffer[];}; struct context { struct fw_ohci *ohci; u32 regs; int total_allocation; u32 current_bus; bool running; /* * List of page-sized buffers for storing DMA descriptors. * Head of list contains buffers in use and tail of list contains * free buffers. */ struct list_head buffer_list; /* * Pointer to a buffer inside buffer_list that contains the tail * end of the current DMA program. */ struct descriptor_buffer *buffer_tail; /* * The descriptor containing the branch address of the first * descriptor that has not yet been filled by the device. */ struct descriptor *last; /* * The last descriptor block in the DMA program. It contains the branch * address that must be updated upon appending a new descriptor. */ struct descriptor *prev; int prev_z; descriptor_callback_t callback;}; struct at_context { struct context context; struct work_struct work; bool flushing;}; struct iso_context { struct fw_iso_context base; struct context context; unsigned long flushing_completions; u8 sync; u8 tags; union { struct { u16 last_timestamp; size_t header_length; void *header; } sc; struct { u32 buffer_bus; u16 completed; } mc; };}; #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) struct fw_ohci { struct fw_card card; __iomem char *registers; int node_id; int generation; int request_generation; /* for timestamping incoming requests */ unsigned quirks; unsigned int pri_req_max; u32 bus_time; bool bus_time_running; bool is_root; bool csr_state_setclear_abdicate; int n_ir; int n_it; /* * Spinlock for accessing fw_ohci data. Never call out of * this driver with this lock held. */ spinlock_t lock; struct mutex phy_reg_mutex; void *misc_buffer; dma_addr_t misc_buffer_bus; struct ar_context ar_request_ctx; struct ar_context ar_response_ctx; struct at_context at_request_ctx; struct at_context at_response_ctx; u32 it_context_support; u32 it_context_mask; /* unoccupied IT contexts */ struct iso_context *it_context_list; u64 ir_context_channels; /* unoccupied channels */ u32 ir_context_support; u32 ir_context_mask; /* unoccupied IR contexts */ struct iso_context *ir_context_list; u64 mc_channels; /* channels in use by the multichannel IR context */ bool mc_allocated; __be32 *config_rom; dma_addr_t config_rom_bus; __be32 *next_config_rom; dma_addr_t next_config_rom_bus; __be32 next_header; __le32 *self_id; dma_addr_t self_id_bus; u32 self_id_buffer[512];}; static inline struct fw_ohci *fw_ohci(struct fw_card *card){ return container_of(card, struct fw_ohci, card);} #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000#define IR_CONTEXT_BUFFER_FILL 0x80000000#define IR_CONTEXT_ISOCH_HEADER 0x40000000#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 #define CONTEXT_RUN 0x8000#define CONTEXT_WAKE 0x1000#define CONTEXT_DEAD 0x0800#define CONTEXT_ACTIVE 0x0400 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf#define OHCI1394_MAX_AT_RESP_RETRIES 0x2#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 #define OHCI1394_REGISTER_SIZE 0x800#define OHCI1394_PCI_HCI_Control 0x40#define SELF_ID_BUF_SIZE 0x800#define OHCI_VERSION_1_1 0x010010 static char ohci_driver_name[] = KBUILD_MODNAME; #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd#define PCI_DEVICE_ID_AGERE_FW643 0x5901#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025#define PCI_DEVICE_ID_VIA_VT630X 0x3044#define PCI_REV_ID_VIA_VT6306 0x46#define PCI_DEVICE_ID_VIA_VT6315 0x3403 #define QUIRK_CYCLE_TIMER 0x1#define QUIRK_RESET_PACKET 0x2#define QUIRK_BE_HEADERS 0x4#define QUIRK_NO_1394A 0x8#define QUIRK_NO_MSI 0x10#define QUIRK_TI_SLLZ059 0x20#define QUIRK_IR_WAKE 0x40 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia// ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register// (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not// clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register,// while it is probable due to detection of any type of PCIe error.#define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 #if IS_ENABLED(CONFIG_X86) static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci){ return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ);} #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev){ const struct pci_dev *pcie_to_pci_bridge; // Detect any type of AMD Ryzen machine. if (!cpu_feature_enabled(X86_FEATURE_ZEN)) return false; // Detect VIA VT6306/6307/6308. if (pdev->vendor != PCI_VENDOR_ID_VIA) return false; if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) return false; // Detect Asmedia ASM1083/1085. pcie_to_pci_bridge = pdev->bus->self; if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) return false; if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) return false; return true;} #else#define has_reboot_by_cycle_timer_read_quirk(ohci) false#define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false#endif /* In case of multiple matches in ohci_quirks[], only the first one is used. */static const struct { unsigned short vendor, device, revision, flags;} ohci_quirks[] = { {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, QUIRK_BE_HEADERS}, {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, QUIRK_NO_MSI}, {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, QUIRK_RESET_PACKET}, {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, QUIRK_RESET_PACKET}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},}; /* This overrides anything that was found in ohci_quirks[]. */static int param_quirks;module_param_named(quirks, param_quirks, int, 0644);MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) ", disable MSI = " __stringify(QUIRK_NO_MSI) ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) ")"); static bool param_remote_dma;module_param_named(remote_dma, param_remote_dma, bool, 0444);MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data){ writel(data, ohci->registers + offset);} static inline u32 reg_read(const struct fw_ohci *ohci, int offset){ return readl(ohci->registers + offset);} static inline void flush_writes(const struct fw_ohci *ohci){ /* Do a dummy read to flush writes. */ reg_read(ohci, OHCI1394_Version);} /* * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() * directly. Exceptions are intrinsically serialized contexts like pci_probe. */static int read_phy_reg(struct fw_ohci *ohci, int addr){ u32 val; int i; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); for (i = 0; i < 3 + 100; i++) { val = reg_read(ohci, OHCI1394_PhyControl); if (!~val) return -ENODEV; /* Card was ejected. */ if (val & OHCI1394_PhyControl_ReadDone) return OHCI1394_PhyControl_ReadData(val); /* * Try a few times without waiting. Sleeping is necessary * only when the link/PHY interface is busy. */ if (i >= 3) msleep(1); } ohci_err(ohci, "failed to read phy reg %d\n", addr); dump_stack(); return -EBUSY;} static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val){ int i; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Write(addr, val)); for (i = 0; i < 3 + 100; i++) { val = reg_read(ohci, OHCI1394_PhyControl); if (!~val) return -ENODEV; /* Card was ejected. */ if (!(val & OHCI1394_PhyControl_WritePending)) return 0; if (i >= 3) msleep(1); } ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); dump_stack(); return -EBUSY;} static int update_phy_reg(struct fw_ohci *ohci, int addr, int clear_bits, int set_bits){ int ret = read_phy_reg(ohci, addr); if (ret < 0) return ret; /* * The interrupt status bits are cleared by writing a one bit. * Avoid clearing them unless explicitly requested in set_bits. */ if (addr == 5) clear_bits |= PHY_INT_STATUS_BITS; return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);} static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr){ int ret; ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); if (ret < 0) return ret; Lines 1–500 of 3835. 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// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for OHCI 1394 controllers * * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> */ #include <linux/bitops.h> #include <linux/bug.h> #include <linux/compiler.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/firewire.h> #include <linux/firewire-constants.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/mm.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/mutex.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/string.h> #include <linux/time.h> #include <linux/vmalloc.h> #include <linux/workqueue.h> #include <asm/byteorder.h> #include <asm/page.h> #ifdef CONFIG_PPC_PMAC #include <asm/pmac_feature.h> #endif #include "core.h" #include "ohci.h" #include "packet-header-definitions.h" #include "phy-packet-definitions.h" #include <trace/events/firewire.h> static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk); #define CREATE_TRACE_POINTS #include <trace/events/firewire_ohci.h> #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) #define DESCRIPTOR_OUTPUT_MORE 0 #define DESCRIPTOR_OUTPUT_LAST (1 << 12) #define DESCRIPTOR_INPUT_MORE (2 << 12) #define DESCRIPTOR_INPUT_LAST (3 << 12) #define DESCRIPTOR_STATUS (1 << 11) #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) #define DESCRIPTOR_PING (1 << 7) #define DESCRIPTOR_YY (1 << 6) #define DESCRIPTOR_NO_IRQ (0 << 4) #define DESCRIPTOR_IRQ_ERROR (1 << 4) #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) #define DESCRIPTOR_WAIT (3 << 0) #define DESCRIPTOR_CMD (0xf << 12) struct descriptor { __le16 req_count; __le16 control; __le32 data_address; __le32 branch_address; __le16 res_count; __le16 transfer_status; } __aligned(16); #define CONTROL_SET(regs) (regs) #define CONTROL_CLEAR(regs) ((regs) + 4) #define COMMAND_PTR(regs) ((regs) + 12) #define CONTEXT_MATCH(regs) ((regs) + 16) #define AR_BUFFER_SIZE (32*1024) #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) /* we need at least two pages for proper list management */ #define AR_BUFFERS MAX(2, AR_BUFFERS_MIN) #define MAX_ASYNC_PAYLOAD 4096 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) struct ar_context { struct fw_ohci *ohci; struct page *pages[AR_BUFFERS]; void *buffer; dma_addr_t dma_addrs[AR_BUFFERS]; struct descriptor *descriptors; dma_addr_t descriptors_bus; void *pointer; unsigned int last_buffer_index; u32 regs; struct work_struct work; }; struct context; typedef int (*descriptor_callback_t)(struct context *ctx, struct descriptor *d, struct descriptor *last); /* * A buffer that contains a block of DMA-able coherent memory used for * storing a portion of a DMA descriptor program. */ struct descriptor_buffer { struct list_head list; dma_addr_t buffer_bus; size_t buffer_size; size_t used; struct descriptor buffer[]; }; struct context { struct fw_ohci *ohci; u32 regs; int total_allocation; u32 current_bus; bool running; /* * List of page-sized buffers for storing DMA descriptors. * Head of list contains buffers in use and tail of list contains * free buffers. */ struct list_head buffer_list; /* * Pointer to a buffer inside buffer_list that contains the tail * end of the current DMA program. */ struct descriptor_buffer *buffer_tail; /* * The descriptor containing the branch address of the first * descriptor that has not yet been filled by the device. */ struct descriptor *last; /* * The last descriptor block in the DMA program. It contains the branch * address that must be updated upon appending a new descriptor. */ struct descriptor *prev; int prev_z; descriptor_callback_t callback; }; struct at_context { struct context context; struct work_struct work; bool flushing; }; struct iso_context { struct fw_iso_context base; struct context context; unsigned long flushing_completions; u8 sync; u8 tags; union { struct { u16 last_timestamp; size_t header_length; void *header; } sc; struct { u32 buffer_bus; u16 completed; } mc; }; }; #define CONFIG_ROM_SIZE (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM) struct fw_ohci { struct fw_card card; __iomem char *registers; int node_id; int generation; int request_generation; /* for timestamping incoming requests */ unsigned quirks; unsigned int pri_req_max; u32 bus_time; bool bus_time_running; bool is_root; bool csr_state_setclear_abdicate; int n_ir; int n_it; /* * Spinlock for accessing fw_ohci data. Never call out of * this driver with this lock held. */ spinlock_t lock; struct mutex phy_reg_mutex; void *misc_buffer; dma_addr_t misc_buffer_bus; struct ar_context ar_request_ctx; struct ar_context ar_response_ctx; struct at_context at_request_ctx; struct at_context at_response_ctx; u32 it_context_support; u32 it_context_mask; /* unoccupied IT contexts */ struct iso_context *it_context_list; u64 ir_context_channels; /* unoccupied channels */ u32 ir_context_support; u32 ir_context_mask; /* unoccupied IR contexts */ struct iso_context *ir_context_list; u64 mc_channels; /* channels in use by the multichannel IR context */ bool mc_allocated; __be32 *config_rom; dma_addr_t config_rom_bus; __be32 *next_config_rom; dma_addr_t next_config_rom_bus; __be32 next_header; __le32 *self_id; dma_addr_t self_id_bus; u32 self_id_buffer[512]; }; static inline struct fw_ohci *fw_ohci(struct fw_card *card) { return container_of(card, struct fw_ohci, card); } #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 #define IR_CONTEXT_BUFFER_FILL 0x80000000 #define IR_CONTEXT_ISOCH_HEADER 0x40000000 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 #define CONTEXT_RUN 0x8000 #define CONTEXT_WAKE 0x1000 #define CONTEXT_DEAD 0x0800 #define CONTEXT_ACTIVE 0x0400 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 #define OHCI1394_REGISTER_SIZE 0x800 #define OHCI1394_PCI_HCI_Control 0x40 #define SELF_ID_BUF_SIZE 0x800 #define OHCI_VERSION_1_1 0x010010 static char ohci_driver_name[] = KBUILD_MODNAME; #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd #define PCI_DEVICE_ID_AGERE_FW643 0x5901 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 #define PCI_DEVICE_ID_VIA_VT630X 0x3044 #define PCI_REV_ID_VIA_VT6306 0x46 #define PCI_DEVICE_ID_VIA_VT6315 0x3403 #define QUIRK_CYCLE_TIMER 0x1 #define QUIRK_RESET_PACKET 0x2 #define QUIRK_BE_HEADERS 0x4 #define QUIRK_NO_1394A 0x8 #define QUIRK_NO_MSI 0x10 #define QUIRK_TI_SLLZ059 0x20 #define QUIRK_IR_WAKE 0x40 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, // while it is probable due to detection of any type of PCIe error. #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 #if IS_ENABLED(CONFIG_X86) static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) { return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); } #define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) { const struct pci_dev *pcie_to_pci_bridge; // Detect any type of AMD Ryzen machine. if (!cpu_feature_enabled(X86_FEATURE_ZEN)) return false; // Detect VIA VT6306/6307/6308. if (pdev->vendor != PCI_VENDOR_ID_VIA) return false; if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) return false; // Detect Asmedia ASM1083/1085. pcie_to_pci_bridge = pdev->bus->self; if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) return false; if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) return false; return true; } #else #define has_reboot_by_cycle_timer_read_quirk(ohci) false #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false #endif /* In case of multiple matches in ohci_quirks[], only the first one is used. */ static const struct { unsigned short vendor, device, revision, flags; } ohci_quirks[] = { {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, QUIRK_BE_HEADERS}, {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, QUIRK_NO_MSI}, {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, QUIRK_RESET_PACKET}, {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, QUIRK_RESET_PACKET}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, QUIRK_NO_MSI}, {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, }; /* This overrides anything that was found in ohci_quirks[]. */ static int param_quirks; module_param_named(quirks, param_quirks, int, 0644); MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) ", disable MSI = " __stringify(QUIRK_NO_MSI) ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) ")"); static bool param_remote_dma; module_param_named(remote_dma, param_remote_dma, bool, 0444); MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) { writel(data, ohci->registers + offset); } static inline u32 reg_read(const struct fw_ohci *ohci, int offset) { return readl(ohci->registers + offset); } static inline void flush_writes(const struct fw_ohci *ohci) { /* Do a dummy read to flush writes. */ reg_read(ohci, OHCI1394_Version); } /* * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() * directly. Exceptions are intrinsically serialized contexts like pci_probe. */ static int read_phy_reg(struct fw_ohci *ohci, int addr) { u32 val; int i; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); for (i = 0; i < 3 + 100; i++) { val = reg_read(ohci, OHCI1394_PhyControl); if (!~val) return -ENODEV; /* Card was ejected. */ if (val & OHCI1394_PhyControl_ReadDone) return OHCI1394_PhyControl_ReadData(val); /* * Try a few times without waiting. Sleeping is necessary * only when the link/PHY interface is busy. */ if (i >= 3) msleep(1); } ohci_err(ohci, "failed to read phy reg %d\n", addr); dump_stack(); return -EBUSY; } static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) { int i; reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Write(addr, val)); for (i = 0; i < 3 + 100; i++) { val = reg_read(ohci, OHCI1394_PhyControl); if (!~val) return -ENODEV; /* Card was ejected. */ if (!(val & OHCI1394_PhyControl_WritePending)) return 0; if (i >= 3) msleep(1); } ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); dump_stack(); return -EBUSY; } static int update_phy_reg(struct fw_ohci *ohci, int addr, int clear_bits, int set_bits) { int ret = read_phy_reg(ohci, addr); if (ret < 0) return ret; /* * The interrupt status bits are cleared by writing a one bit. * Avoid clearing them unless explicitly requested in set_bits. */ if (addr == 5) clear_bits |= PHY_INT_STATUS_BITS; return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); } static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) { int ret; ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); if (ret < 0) return ret;