// SPDX-License-Identifier: GPL-2.0+/* * drivers/net/phy/micrel.c * * Driver for Micrel PHYs * * Author: David J. Choi * * Copyright (c) 2010-2013 Micrel, Inc. * Copyright (c) 2014 Johan Hovold <johan@kernel.org> * * Support : Micrel Phys: * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 * ksz8021, ksz8031, ksz8051, * ksz8081, ksz8091, * ksz8061, * Switch : ksz8873, ksz886x * ksz9477, lan8804 */ #include <linux/bitfield.h>#include <linux/ethtool_netlink.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/phy.h>#include <linux/micrel_phy.h>#include <linux/of.h>#include <linux/clk.h>#include <linux/delay.h>#include <linux/ptp_clock_kernel.h>#include <linux/ptp_clock.h>#include <linux/ptp_classify.h>#include <linux/net_tstamp.h>#include <linux/gpio/consumer.h> #include "phylib.h" /* Operation Mode Strap Override */#define MII_KSZPHY_OMSO 0x16#define KSZPHY_OMSO_FACTORY_TEST BIT(15)#define KSZPHY_OMSO_B_CAST_OFF BIT(9)#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)#define KSZPHY_OMSO_MII_OVERRIDE BIT(0) /* general Interrupt control/status reg in vendor specific block. */#define MII_KSZPHY_INTCS 0x1B#define KSZPHY_INTCS_JABBER BIT(15)#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)#define KSZPHY_INTCS_PARELLEL BIT(12)#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)#define KSZPHY_INTCS_LINK_DOWN BIT(10)#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)#define KSZPHY_INTCS_LINK_UP BIT(8)#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ KSZPHY_INTCS_LINK_DOWN)#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ KSZPHY_INTCS_LINK_UP_STATUS) /* LinkMD Control/Status */#define KSZ8081_LMD 0x1d#define KSZ8081_LMD_ENABLE_TEST BIT(15)#define KSZ8081_LMD_STAT_NORMAL 0#define KSZ8081_LMD_STAT_OPEN 1#define KSZ8081_LMD_STAT_SHORT 2#define KSZ8081_LMD_STAT_FAIL 3#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)/* Short cable (<10 meter) has been detected by LinkMD */#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0) #define KSZ9x31_LMD 0x12#define KSZ9x31_LMD_VCT_EN BIT(15)#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)#define KSZ9x31_LMD_VCT_SEL_RESULT 0#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)#define KSZ9x31_LMD_VCT_ST_NORMAL 0#define KSZ9x31_LMD_VCT_ST_OPEN 1#define KSZ9x31_LMD_VCT_ST_SHORT 2#define KSZ9x31_LMD_VCT_ST_FAIL 3#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0) #define KSZPHY_WIRE_PAIR_MASK 0x3 #define LAN8814_CABLE_DIAG 0x12#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)#define LAN8814_PAIR_BIT_SHIFT 12 /* KSZ9x31 remote loopback register */#define KSZ9x31_REMOTE_LOOPBACK 0x11/* This is an undocumented bit of the KSZ9131RNX. * It was reported by NXP in cooperation with Micrel. */#define KSZ9x31_REMOTE_LOOPBACK_KEEP_PREAMBLE BIT(2)#define KSZ9x31_REMOTE_LOOPBACK_EN BIT(8) #define LAN8814_SKUS 0xB #define LAN8814_WIRE_PAIR_MASK 0xF /* Lan8814 general Interrupt control/status reg in GPHY specific block. */#define LAN8814_INTC 0x18#define LAN8814_INTS 0x1B #define LAN8814_INT_FLF BIT(15)#define LAN8814_INT_LINK_DOWN BIT(2)#define LAN8814_INT_LINK_UP BIT(0)#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\ LAN8814_INT_LINK_DOWN) #define LAN8814_INTR_CTRL_REG 0x34#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0) #define LAN8814_EEE_STATE 0x38#define LAN8814_EEE_STATE_MASK2P5P BIT(10) #define LAN8814_PD_CONTROLS 0x9d#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles. * The value is calculated as following: (1/1000000)/((2^-32)/4) */#define LAN8814_1PPM_FORMAT 17179 /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 8 clock cycles. * The value is calculated as following: (1/1000000)/((2^-32)/8) */#define LAN8841_1PPM_FORMAT 34360 #define PTP_RX_VERSION 0x0248#define PTP_TX_VERSION 0x0288#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0)) #define PTP_RX_MOD 0x024F#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)#define PTP_RX_TIMESTAMP_EN 0x024D#define PTP_TX_TIMESTAMP_EN 0x028D #define PTP_TIMESTAMP_EN_SYNC_ BIT(0)#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)#define PTP_TIMESTAMP_EN_PDRES_ BIT(3) #define PTP_TX_PARSE_L2_ADDR_EN 0x0284#define PTP_RX_PARSE_L2_ADDR_EN 0x0244 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285#define PTP_RX_PARSE_IP_ADDR_EN 0x0245#define LTC_HARD_RESET 0x023F#define LTC_HARD_RESET_ BIT(0) #define TSU_HARD_RESET 0x02C1#define TSU_HARD_RESET_ BIT(0) #define PTP_CMD_CTL 0x0200#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6) #define PTP_COMMON_INT_ENA 0x0204#define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2) #define PTP_CLOCK_SET_SEC_HI 0x0205#define PTP_CLOCK_SET_SEC_MID 0x0206#define PTP_CLOCK_SET_SEC_LO 0x0207#define PTP_CLOCK_SET_NS_HI 0x0208#define PTP_CLOCK_SET_NS_LO 0x0209 #define PTP_CLOCK_READ_SEC_HI 0x0229#define PTP_CLOCK_READ_SEC_MID 0x022A#define PTP_CLOCK_READ_SEC_LO 0x022B#define PTP_CLOCK_READ_NS_HI 0x022C#define PTP_CLOCK_READ_NS_LO 0x022D #define PTP_GPIO_SEL 0x0230#define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8)#define PTP_GPIO_CAP_MAP_LO 0x0232 #define PTP_GPIO_CAP_EN 0x0233#define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio)#define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8) #define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235#define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236#define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237#define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238#define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239#define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A#define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B#define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C #define PTP_GPIO_CAP_STS 0x023D#define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio)#define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8) #define PTP_OPERATING_MODE 0x0241#define PTP_OPERATING_MODE_STANDALONE_ BIT(0) #define PTP_TX_MOD 0x028F#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) #define PTP_RX_PARSE_CONFIG 0x0242#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2) #define PTP_TX_PARSE_CONFIG 0x0282#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2) #define PTP_CLOCK_RATE_ADJ_HI 0x020C#define PTP_CLOCK_RATE_ADJ_LO 0x020D#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15) #define PTP_LTC_STEP_ADJ_HI 0x0212#define PTP_LTC_STEP_ADJ_LO 0x0213#define PTP_LTC_STEP_ADJ_DIR_ BIT(15) #define LAN8814_INTR_STS_REG 0x0033#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3) #define PTP_CAP_INFO 0x022A#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f) #define PTP_TX_EGRESS_SEC_HI 0x0296#define PTP_TX_EGRESS_SEC_LO 0x0297#define PTP_TX_EGRESS_NS_HI 0x0294#define PTP_TX_EGRESS_NS_LO 0x0295#define PTP_TX_MSG_HEADER2 0x0299 #define PTP_RX_INGRESS_SEC_HI 0x0256#define PTP_RX_INGRESS_SEC_LO 0x0257#define PTP_RX_INGRESS_NS_HI 0x0254#define PTP_RX_INGRESS_NS_LO 0x0255#define PTP_RX_MSG_HEADER2 0x0259 #define PTP_TSU_INT_EN 0x0200#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0) #define PTP_TSU_INT_STS 0x0201#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0) #define LAN8814_LED_CTRL_1 0x0#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)#define LAN8814_LED_CTRL_2 0x1#define LAN8814_LED_CTRL_2_LED1_COM_DIS BIT(8) /* PHY Control 1 */#define MII_KSZPHY_CTRL_1 0x1e#define KSZ8081_CTRL1_MDIX_STAT BIT(4) /* PHY Control 2 / PHY Control (if no PHY Control 1) */#define MII_KSZPHY_CTRL_2 0x1f#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 /* Vendor-specific Clause 22 register, virtualized by KSZ87xx embedded PHYs DSA driver */#define MII_KSZ87XX_SHORT_CABLE 0x1a#define MII_KSZ87XX_LPF_BW 0x1b#define MII_KSZ87XX_EQ_INIT 0x1c /* bitmap of PHY register to set interrupt mode */#define KSZ8081_CTRL2_HP_MDIX BIT(15)#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)#define KSZ8081_CTRL2_FORCE_LINK BIT(11)#define KSZ8081_CTRL2_POWER_SAVING BIT(10)#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)#define KSZPHY_RMII_REF_CLK_SEL BIT(7) /* Write/read to/from extended registers */#define MII_KSZPHY_EXTREG 0x0b#define KSZPHY_EXTREG_WRITE 0x8000 #define MII_KSZPHY_EXTREG_WRITE 0x0c#define MII_KSZPHY_EXTREG_READ 0x0d /* Extended registers */#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 #define PS_TO_REG 200#define FIFO_SIZE 8 #define LAN8814_PTP_GPIO_NUM 24#define LAN8814_PTP_PEROUT_NUM 2#define LAN8814_PTP_EXTTS_NUM 3 #define LAN8814_BUFFER_TIME 2 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0 #define LAN8814_GPIO_EN1 0x20#define LAN8814_GPIO_EN2 0x21#define LAN8814_GPIO_DIR1 0x22#define LAN8814_GPIO_DIR2 0x23#define LAN8814_GPIO_BUF1 0x24#define LAN8814_GPIO_BUF2 0x25 #define LAN8814_GPIO_EN_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)#define LAN8814_GPIO_EN_BIT(pin) BIT(pin)#define LAN8814_GPIO_DIR_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)#define LAN8814_GPIO_DIR_BIT(pin) BIT(pin)#define LAN8814_GPIO_BUF_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)#define LAN8814_GPIO_BUF_BIT(pin) BIT(pin) #define LAN8814_EVENT_A 0#define LAN8814_EVENT_B 1 #define LAN8814_PTP_GENERAL_CONFIG 0x0201#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \ ((event) ? GENMASK(11, 8) : GENMASK(7, 4))#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \ (((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))#define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \ ((event) ? BIT(2) : BIT(0))#define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \ ((event) ? BIT(3) : BIT(1)) #define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215)#define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216)#define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217)#define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218) #define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219)#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A)#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B)#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C) /* Delay used to get the second part from the LTC */#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC) #define LAN8842_REV_8832 0x8832 #define LAN8814_REV_LAN8814 0x8814#define LAN8814_REV_LAN8818 0x8818 struct kszphy_hw_stat { const char *string; u8 reg; u8 bits;}; static struct kszphy_hw_stat kszphy_hw_stats[] = { { "phy_receive_errors", 21, 16}, { "phy_idle_errors", 10, 8 },}; struct kszphy_type { u32 led_mode_reg; u16 interrupt_level_mask; u16 cable_diag_reg; unsigned long pair_mask; u16 disable_dll_tx_bit; u16 disable_dll_rx_bit; u16 disable_dll_mask; bool has_broadcast_disable; bool has_nand_tree_disable; bool has_rmii_ref_clk_sel;}; /* Shared structure between the PHYs of the same package. */struct lan8814_shared_priv { struct phy_device *phydev; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_clock_info; struct ptp_pin_desc *pin_config; /* Lock for ptp_clock */ struct mutex shared_lock;}; struct lan8814_ptp_rx_ts { struct list_head list; u32 seconds; u32 nsec; u16 seq_id;}; struct kszphy_ptp_priv { struct mii_timestamper mii_ts; struct phy_device *phydev; struct sk_buff_head tx_queue; struct sk_buff_head rx_queue; struct list_head rx_ts_list; /* Lock for Rx ts fifo */ spinlock_t rx_ts_lock; int hwts_tx_type; enum hwtstamp_rx_filters rx_filter; int layer; int version; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_clock_info; /* Lock for ptp_clock */ struct mutex ptp_lock; struct ptp_pin_desc *pin_config; s64 seconds; /* Lock for accessing seconds */ spinlock_t seconds_lock;}; struct kszphy_phy_stats { u64 rx_err_pkt_cnt;}; struct kszphy_priv { struct kszphy_ptp_priv ptp_priv; const struct kszphy_type *type; struct clk *clk; int led_mode; u16 vct_ctrl1000; bool rmii_ref_clk_sel; bool rmii_ref_clk_sel_val; bool clk_enable; bool is_ptp_available; u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; struct kszphy_phy_stats phy_stats;}; struct lan8842_phy_stats { u64 rx_packets; u64 rx_errors; u64 tx_packets; u64 tx_errors;}; struct lan8842_priv { struct lan8842_phy_stats phy_stats; struct kszphy_ptp_priv ptp_priv; u16 rev;}; struct lanphy_reg_data { int page; u16 addr; u16 val;}; static const struct kszphy_type lan8814_type = { .led_mode_reg = ~LAN8814_LED_CTRL_1, .cable_diag_reg = LAN8814_CABLE_DIAG, .pair_mask = LAN8814_WIRE_PAIR_MASK,}; Lines 1–500 of 7139. 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// SPDX-License-Identifier: GPL-2.0+ /* * drivers/net/phy/micrel.c * * Driver for Micrel PHYs * * Author: David J. Choi * * Copyright (c) 2010-2013 Micrel, Inc. * Copyright (c) 2014 Johan Hovold <johan@kernel.org> * * Support : Micrel Phys: * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 * ksz8021, ksz8031, ksz8051, * ksz8081, ksz8091, * ksz8061, * Switch : ksz8873, ksz886x * ksz9477, lan8804 */ #include <linux/bitfield.h> #include <linux/ethtool_netlink.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/phy.h> #include <linux/micrel_phy.h> #include <linux/of.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/ptp_clock_kernel.h> #include <linux/ptp_clock.h> #include <linux/ptp_classify.h> #include <linux/net_tstamp.h> #include <linux/gpio/consumer.h> #include "phylib.h" /* Operation Mode Strap Override */ #define MII_KSZPHY_OMSO 0x16 #define KSZPHY_OMSO_FACTORY_TEST BIT(15) #define KSZPHY_OMSO_B_CAST_OFF BIT(9) #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) /* general Interrupt control/status reg in vendor specific block. */ #define MII_KSZPHY_INTCS 0x1B #define KSZPHY_INTCS_JABBER BIT(15) #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) #define KSZPHY_INTCS_PARELLEL BIT(12) #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) #define KSZPHY_INTCS_LINK_DOWN BIT(10) #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) #define KSZPHY_INTCS_LINK_UP BIT(8) #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ KSZPHY_INTCS_LINK_DOWN) #define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2) #define KSZPHY_INTCS_LINK_UP_STATUS BIT(0) #define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\ KSZPHY_INTCS_LINK_UP_STATUS) /* LinkMD Control/Status */ #define KSZ8081_LMD 0x1d #define KSZ8081_LMD_ENABLE_TEST BIT(15) #define KSZ8081_LMD_STAT_NORMAL 0 #define KSZ8081_LMD_STAT_OPEN 1 #define KSZ8081_LMD_STAT_SHORT 2 #define KSZ8081_LMD_STAT_FAIL 3 #define KSZ8081_LMD_STAT_MASK GENMASK(14, 13) /* Short cable (<10 meter) has been detected by LinkMD */ #define KSZ8081_LMD_SHORT_INDICATOR BIT(12) #define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0) #define KSZ9x31_LMD 0x12 #define KSZ9x31_LMD_VCT_EN BIT(15) #define KSZ9x31_LMD_VCT_DIS_TX BIT(14) #define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12) #define KSZ9x31_LMD_VCT_SEL_RESULT 0 #define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10) #define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11) #define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10) #define KSZ9x31_LMD_VCT_ST_NORMAL 0 #define KSZ9x31_LMD_VCT_ST_OPEN 1 #define KSZ9x31_LMD_VCT_ST_SHORT 2 #define KSZ9x31_LMD_VCT_ST_FAIL 3 #define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8) #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7) #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6) #define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5) #define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4) #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2) #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0) #define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0) #define KSZPHY_WIRE_PAIR_MASK 0x3 #define LAN8814_CABLE_DIAG 0x12 #define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8) #define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0) #define LAN8814_PAIR_BIT_SHIFT 12 /* KSZ9x31 remote loopback register */ #define KSZ9x31_REMOTE_LOOPBACK 0x11 /* This is an undocumented bit of the KSZ9131RNX. * It was reported by NXP in cooperation with Micrel. */ #define KSZ9x31_REMOTE_LOOPBACK_KEEP_PREAMBLE BIT(2) #define KSZ9x31_REMOTE_LOOPBACK_EN BIT(8) #define LAN8814_SKUS 0xB #define LAN8814_WIRE_PAIR_MASK 0xF /* Lan8814 general Interrupt control/status reg in GPHY specific block. */ #define LAN8814_INTC 0x18 #define LAN8814_INTS 0x1B #define LAN8814_INT_FLF BIT(15) #define LAN8814_INT_LINK_DOWN BIT(2) #define LAN8814_INT_LINK_UP BIT(0) #define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\ LAN8814_INT_LINK_DOWN) #define LAN8814_INTR_CTRL_REG 0x34 #define LAN8814_INTR_CTRL_REG_POLARITY BIT(1) #define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0) #define LAN8814_EEE_STATE 0x38 #define LAN8814_EEE_STATE_MASK2P5P BIT(10) #define LAN8814_PD_CONTROLS 0x9d #define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0) #define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 4 clock cycles. * The value is calculated as following: (1/1000000)/((2^-32)/4) */ #define LAN8814_1PPM_FORMAT 17179 /* Represents 1ppm adjustment in 2^32 format with * each nsec contains 8 clock cycles. * The value is calculated as following: (1/1000000)/((2^-32)/8) */ #define LAN8841_1PPM_FORMAT 34360 #define PTP_RX_VERSION 0x0248 #define PTP_TX_VERSION 0x0288 #define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8) #define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0)) #define PTP_RX_MOD 0x024F #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) #define PTP_RX_TIMESTAMP_EN 0x024D #define PTP_TX_TIMESTAMP_EN 0x028D #define PTP_TIMESTAMP_EN_SYNC_ BIT(0) #define PTP_TIMESTAMP_EN_DREQ_ BIT(1) #define PTP_TIMESTAMP_EN_PDREQ_ BIT(2) #define PTP_TIMESTAMP_EN_PDRES_ BIT(3) #define PTP_TX_PARSE_L2_ADDR_EN 0x0284 #define PTP_RX_PARSE_L2_ADDR_EN 0x0244 #define PTP_TX_PARSE_IP_ADDR_EN 0x0285 #define PTP_RX_PARSE_IP_ADDR_EN 0x0245 #define LTC_HARD_RESET 0x023F #define LTC_HARD_RESET_ BIT(0) #define TSU_HARD_RESET 0x02C1 #define TSU_HARD_RESET_ BIT(0) #define PTP_CMD_CTL 0x0200 #define PTP_CMD_CTL_PTP_DISABLE_ BIT(0) #define PTP_CMD_CTL_PTP_ENABLE_ BIT(1) #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5) #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6) #define PTP_COMMON_INT_ENA 0x0204 #define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2) #define PTP_CLOCK_SET_SEC_HI 0x0205 #define PTP_CLOCK_SET_SEC_MID 0x0206 #define PTP_CLOCK_SET_SEC_LO 0x0207 #define PTP_CLOCK_SET_NS_HI 0x0208 #define PTP_CLOCK_SET_NS_LO 0x0209 #define PTP_CLOCK_READ_SEC_HI 0x0229 #define PTP_CLOCK_READ_SEC_MID 0x022A #define PTP_CLOCK_READ_SEC_LO 0x022B #define PTP_CLOCK_READ_NS_HI 0x022C #define PTP_CLOCK_READ_NS_LO 0x022D #define PTP_GPIO_SEL 0x0230 #define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8) #define PTP_GPIO_CAP_MAP_LO 0x0232 #define PTP_GPIO_CAP_EN 0x0233 #define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio) #define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8) #define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235 #define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236 #define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237 #define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238 #define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239 #define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A #define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B #define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C #define PTP_GPIO_CAP_STS 0x023D #define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio) #define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8) #define PTP_OPERATING_MODE 0x0241 #define PTP_OPERATING_MODE_STANDALONE_ BIT(0) #define PTP_TX_MOD 0x028F #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12) #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3) #define PTP_RX_PARSE_CONFIG 0x0242 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0) #define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1) #define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2) #define PTP_TX_PARSE_CONFIG 0x0282 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0) #define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1) #define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2) #define PTP_CLOCK_RATE_ADJ_HI 0x020C #define PTP_CLOCK_RATE_ADJ_LO 0x020D #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15) #define PTP_LTC_STEP_ADJ_HI 0x0212 #define PTP_LTC_STEP_ADJ_LO 0x0213 #define PTP_LTC_STEP_ADJ_DIR_ BIT(15) #define LAN8814_INTR_STS_REG 0x0033 #define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0) #define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1) #define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2) #define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3) #define PTP_CAP_INFO 0x022A #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8) #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f) #define PTP_TX_EGRESS_SEC_HI 0x0296 #define PTP_TX_EGRESS_SEC_LO 0x0297 #define PTP_TX_EGRESS_NS_HI 0x0294 #define PTP_TX_EGRESS_NS_LO 0x0295 #define PTP_TX_MSG_HEADER2 0x0299 #define PTP_RX_INGRESS_SEC_HI 0x0256 #define PTP_RX_INGRESS_SEC_LO 0x0257 #define PTP_RX_INGRESS_NS_HI 0x0254 #define PTP_RX_INGRESS_NS_LO 0x0255 #define PTP_RX_MSG_HEADER2 0x0259 #define PTP_TSU_INT_EN 0x0200 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3) #define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2) #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1) #define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0) #define PTP_TSU_INT_STS 0x0201 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3) #define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2) #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1) #define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0) #define LAN8814_LED_CTRL_1 0x0 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6) #define LAN8814_LED_CTRL_2 0x1 #define LAN8814_LED_CTRL_2_LED1_COM_DIS BIT(8) /* PHY Control 1 */ #define MII_KSZPHY_CTRL_1 0x1e #define KSZ8081_CTRL1_MDIX_STAT BIT(4) /* PHY Control 2 / PHY Control (if no PHY Control 1) */ #define MII_KSZPHY_CTRL_2 0x1f #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 /* Vendor-specific Clause 22 register, virtualized by KSZ87xx embedded PHYs DSA driver */ #define MII_KSZ87XX_SHORT_CABLE 0x1a #define MII_KSZ87XX_LPF_BW 0x1b #define MII_KSZ87XX_EQ_INIT 0x1c /* bitmap of PHY register to set interrupt mode */ #define KSZ8081_CTRL2_HP_MDIX BIT(15) #define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14) #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13) #define KSZ8081_CTRL2_FORCE_LINK BIT(11) #define KSZ8081_CTRL2_POWER_SAVING BIT(10) #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) #define KSZPHY_RMII_REF_CLK_SEL BIT(7) /* Write/read to/from extended registers */ #define MII_KSZPHY_EXTREG 0x0b #define KSZPHY_EXTREG_WRITE 0x8000 #define MII_KSZPHY_EXTREG_WRITE 0x0c #define MII_KSZPHY_EXTREG_READ 0x0d /* Extended registers */ #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 #define PS_TO_REG 200 #define FIFO_SIZE 8 #define LAN8814_PTP_GPIO_NUM 24 #define LAN8814_PTP_PEROUT_NUM 2 #define LAN8814_PTP_EXTTS_NUM 3 #define LAN8814_BUFFER_TIME 2 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0 #define LAN8814_GPIO_EN1 0x20 #define LAN8814_GPIO_EN2 0x21 #define LAN8814_GPIO_DIR1 0x22 #define LAN8814_GPIO_DIR2 0x23 #define LAN8814_GPIO_BUF1 0x24 #define LAN8814_GPIO_BUF2 0x25 #define LAN8814_GPIO_EN_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2) #define LAN8814_GPIO_EN_BIT(pin) BIT(pin) #define LAN8814_GPIO_DIR_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2) #define LAN8814_GPIO_DIR_BIT(pin) BIT(pin) #define LAN8814_GPIO_BUF_ADDR(pin) \ ((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2) #define LAN8814_GPIO_BUF_BIT(pin) BIT(pin) #define LAN8814_EVENT_A 0 #define LAN8814_EVENT_B 1 #define LAN8814_PTP_GENERAL_CONFIG 0x0201 #define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \ ((event) ? GENMASK(11, 8) : GENMASK(7, 4)) #define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \ (((value) & GENMASK(3, 0)) << (4 + ((event) << 2))) #define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \ ((event) ? BIT(2) : BIT(0)) #define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \ ((event) ? BIT(3) : BIT(1)) #define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215) #define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216) #define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217) #define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218) #define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219) #define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A) #define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B) #define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C) /* Delay used to get the second part from the LTC */ #define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC) #define LAN8842_REV_8832 0x8832 #define LAN8814_REV_LAN8814 0x8814 #define LAN8814_REV_LAN8818 0x8818 struct kszphy_hw_stat { const char *string; u8 reg; u8 bits; }; static struct kszphy_hw_stat kszphy_hw_stats[] = { { "phy_receive_errors", 21, 16}, { "phy_idle_errors", 10, 8 }, }; struct kszphy_type { u32 led_mode_reg; u16 interrupt_level_mask; u16 cable_diag_reg; unsigned long pair_mask; u16 disable_dll_tx_bit; u16 disable_dll_rx_bit; u16 disable_dll_mask; bool has_broadcast_disable; bool has_nand_tree_disable; bool has_rmii_ref_clk_sel; }; /* Shared structure between the PHYs of the same package. */ struct lan8814_shared_priv { struct phy_device *phydev; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_clock_info; struct ptp_pin_desc *pin_config; /* Lock for ptp_clock */ struct mutex shared_lock; }; struct lan8814_ptp_rx_ts { struct list_head list; u32 seconds; u32 nsec; u16 seq_id; }; struct kszphy_ptp_priv { struct mii_timestamper mii_ts; struct phy_device *phydev; struct sk_buff_head tx_queue; struct sk_buff_head rx_queue; struct list_head rx_ts_list; /* Lock for Rx ts fifo */ spinlock_t rx_ts_lock; int hwts_tx_type; enum hwtstamp_rx_filters rx_filter; int layer; int version; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_clock_info; /* Lock for ptp_clock */ struct mutex ptp_lock; struct ptp_pin_desc *pin_config; s64 seconds; /* Lock for accessing seconds */ spinlock_t seconds_lock; }; struct kszphy_phy_stats { u64 rx_err_pkt_cnt; }; struct kszphy_priv { struct kszphy_ptp_priv ptp_priv; const struct kszphy_type *type; struct clk *clk; int led_mode; u16 vct_ctrl1000; bool rmii_ref_clk_sel; bool rmii_ref_clk_sel_val; bool clk_enable; bool is_ptp_available; u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; struct kszphy_phy_stats phy_stats; }; struct lan8842_phy_stats { u64 rx_packets; u64 rx_errors; u64 tx_packets; u64 tx_errors; }; struct lan8842_priv { struct lan8842_phy_stats phy_stats; struct kszphy_ptp_priv ptp_priv; u16 rev; }; struct lanphy_reg_data { int page; u16 addr; u16 val; }; static const struct kszphy_type lan8814_type = { .led_mode_reg = ~LAN8814_LED_CTRL_1, .cable_diag_reg = LAN8814_CABLE_DIAG, .pair_mask = LAN8814_WIRE_PAIR_MASK, };