// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)/* * Copyright (C) 2004-2016 Synopsys, Inc. */ #include <linux/kernel.h>#include <linux/module.h>#include <linux/of.h>#include <linux/usb/of.h>#include <linux/pci_ids.h>#include <linux/pci.h> #include "core.h" #define PCI_PRODUCT_ID_HAPS_HSOTG	0xabc0#define PCI_DEVICE_ID_LOONGSON_DWC2	0x7a04 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->host_rx_fifo_size = 774;	p->max_transfer_size = 65535;	p->max_packet_count = 511;	p->ahbcfg = 0x10;} static void dwc2_set_his_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->host_rx_fifo_size = 512;	p->host_nperio_tx_fifo_size = 512;	p->host_perio_tx_fifo_size = 512;	p->max_transfer_size = 65535;	p->max_packet_count = 511;	p->host_channels = 16;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 8;	p->i2c_enable = false;	p->reload_ctl = false;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<		GAHBCFG_HBSTLEN_SHIFT;	p->change_speed_quirk = true;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;} static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 16;	p->activate_ingenic_overcurrent_detection =		!device_property_read_bool(hsotg->dev, "disable-over-current");} static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->phy_utmi_width = 8;	p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL;} static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->host_channels = 16;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 16;	p->activate_ingenic_overcurrent_detection =		!device_property_read_bool(hsotg->dev, "disable-over-current");} static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->host_rx_fifo_size = 1024;	p->host_nperio_tx_fifo_size = 1024;	p->host_perio_tx_fifo_size = 1024;	p->host_channels = 16;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 16;	p->activate_ingenic_overcurrent_detection =		!device_property_read_bool(hsotg->dev, "disable-over-current");} static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	p->no_clock_gating = true;	p->phy_utmi_width = 8;} static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	p->no_clock_gating = true;} static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->host_rx_fifo_size = 525;	p->host_nperio_tx_fifo_size = 128;	p->host_perio_tx_fifo_size = 256;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<		GAHBCFG_HBSTLEN_SHIFT;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	p->lpm = false;	p->lpm_clock_gating = false;	p->besl = false;	p->hird_threshold_en = false;	p->no_clock_gating = true;} static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;} static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->host_rx_fifo_size = 288;	p->host_nperio_tx_fifo_size = 128;	p->host_perio_tx_fifo_size = 96;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<		GAHBCFG_HBSTLEN_SHIFT;} static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->host_rx_fifo_size = 288;	p->host_nperio_tx_fifo_size = 128;	p->host_perio_tx_fifo_size = 136;} static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->host_rx_fifo_size = 512;	p->host_nperio_tx_fifo_size = 500;	p->host_perio_tx_fifo_size = 500;	p->host_channels = 16;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<		GAHBCFG_HBSTLEN_SHIFT;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;} static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->lpm = false;	p->lpm_clock_gating = false;	p->besl = false;	p->hird_threshold_en = false;} static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->host_rx_fifo_size = 192;	p->host_nperio_tx_fifo_size = 128;	p->host_perio_tx_fifo_size = 128;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 8;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT;	p->lpm = false;	p->lpm_clock_gating = false;	p->besl = false;	p->hird_threshold_en = false;} static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;} static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->host_dma = false;	p->g_dma = false;	p->speed = DWC2_SPEED_PARAM_HIGH;	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;	p->phy_utmi_width = 16;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;	p->lpm = false;	p->lpm_clock_gating = false;	p->besl = false;	p->hird_threshold_en = false;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;} static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->speed = DWC2_SPEED_PARAM_FULL;	p->host_rx_fifo_size = 128;	p->host_nperio_tx_fifo_size = 96;	p->host_perio_tx_fifo_size = 96;	p->max_packet_count = 256;	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;	p->i2c_enable = false;	p->activate_stm_fs_transceiver = true;} static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->host_rx_fifo_size = 622;	p->host_nperio_tx_fifo_size = 128;	p->host_perio_tx_fifo_size = 256;} static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->otg_caps.otg_rev = 0x200;	p->speed = DWC2_SPEED_PARAM_FULL;	p->host_rx_fifo_size = 128;	p->host_nperio_tx_fifo_size = 96;	p->host_perio_tx_fifo_size = 96;	p->max_packet_count = 256;	p->phy_type = DWC2_PHY_TYPE_PARAM_FS;	p->i2c_enable = false;	p->activate_stm_fs_transceiver = true;	p->activate_stm_id_vb_detection = true;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	p->host_support_fs_ls_low_power = true;	p->host_ls_low_power_phy_clk = true;} static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->otg_caps.hnp_support = false;	p->otg_caps.srp_support = false;	p->otg_caps.otg_rev = 0x200;	p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");	p->host_rx_fifo_size = 440;	p->host_nperio_tx_fifo_size = 256;	p->host_perio_tx_fifo_size = 256;	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;	p->lpm = false;	p->lpm_clock_gating = false;	p->besl = false;	p->hird_threshold_en = false;} const struct of_device_id dwc2_of_match_table[] = {	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },	{ .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },	{ .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },	{ .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },	{ .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },	{ .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },	{ .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },	{ .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },	{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },	{ .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },	{ .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },	{ .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },	{ .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },	{ .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },	{ .compatible = "snps,dwc2" },	{ .compatible = "samsung,s3c6400-hsotg",	  .data = dwc2_set_s3c6400_params },	{ .compatible = "amlogic,meson8-usb",	  .data = dwc2_set_amlogic_params },	{ .compatible = "amlogic,meson8b-usb",	  .data = dwc2_set_amlogic_params },	{ .compatible = "amlogic,meson-gxbb-usb",	  .data = dwc2_set_amlogic_params },	{ .compatible = "amlogic,meson-g12a-usb",	  .data = dwc2_set_amlogic_g12a_params },	{ .compatible = "amlogic,meson-a1-usb",	  .data = dwc2_set_amlogic_a1_params },	{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },	{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },	{ .compatible = "sophgo,cv1800b-usb",	  .data = dwc2_set_cv1800_params },	{ .compatible = "st,stm32f4x9-fsotg",	  .data = dwc2_set_stm32f4x9_fsotg_params },	{ .compatible = "st,stm32f4x9-hsotg" },	{ .compatible = "st,stm32f7-hsotg",	  .data = dwc2_set_stm32f7_hsotg_params },	{ .compatible = "st,stm32mp15-fsotg",	  .data = dwc2_set_stm32mp15_fsotg_params },	{ .compatible = "st,stm32mp15-hsotg",	  .data = dwc2_set_stm32mp15_hsotg_params },	{ .compatible = "intel,socfpga-agilex-hsotg",	  .data = dwc2_set_socfpga_agilex_params },	{},};MODULE_DEVICE_TABLE(of, dwc2_of_match_table); const struct acpi_device_id dwc2_acpi_match[] = {	/* This ID refers to the same USB IP as of_device_id brcm,bcm2835-usb */	{ "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },	{ },};MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); const struct pci_device_id dwc2_pci_ids[] = {	{		PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG),	},	{		PCI_DEVICE(PCI_VENDOR_ID_STMICRO,			   PCI_DEVICE_ID_STMICRO_USB_OTG),	},	{		PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2),		.driver_data = (unsigned long)dwc2_set_loongson_params,	},	{ /* end: all zeroes */ }};MODULE_DEVICE_TABLE(pci, dwc2_pci_ids);EXPORT_SYMBOL_GPL(dwc2_pci_ids); static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg){	switch (hsotg->hw_params.op_mode) {	case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:		hsotg->params.otg_caps.hnp_support = true;		hsotg->params.otg_caps.srp_support = true;		break;	case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:	case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:	case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:		hsotg->params.otg_caps.hnp_support = false;		hsotg->params.otg_caps.srp_support = true;		break;	default:		hsotg->params.otg_caps.hnp_support = false;		hsotg->params.otg_caps.srp_support = false;		break;	}} static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg){	int val;	u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 	val = DWC2_PHY_TYPE_PARAM_FS;	if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {		if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||		    hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)			val = DWC2_PHY_TYPE_PARAM_UTMI;		else			val = DWC2_PHY_TYPE_PARAM_ULPI;	} 	if (dwc2_is_fs_iot(hsotg))		hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 	hsotg->params.phy_type = val;} static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg){	int val; 	val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?		DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 	if (dwc2_is_fs_iot(hsotg))		val = DWC2_SPEED_PARAM_FULL; 	if (dwc2_is_hs_iot(hsotg))		val = DWC2_SPEED_PARAM_HIGH; 	hsotg->params.speed = val;} static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg){	int val; 	val = (hsotg->hw_params.utmi_phy_data_width ==	       GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 	if (hsotg->phy) {		/*		 * If using the generic PHY framework, check if the PHY bus		 * width is 8-bit and set the phyif appropriately.		 */		if (phy_get_bus_width(hsotg->phy) == 8)			val = 8;	} 	hsotg->params.phy_utmi_width = val;} static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params;	int depth_average;	int fifo_count;	int i; 	fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 	memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));	depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);	for (i = 1; i <= fifo_count; i++)		p->g_tx_fifo_size[i] = depth_average;} static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg){	int val; 	if (hsotg->hw_params.hibernation)		val = DWC2_POWER_DOWN_PARAM_HIBERNATION;	else if (hsotg->hw_params.power_optimized)		val = DWC2_POWER_DOWN_PARAM_PARTIAL;	else		val = DWC2_POWER_DOWN_PARAM_NONE; 	hsotg->params.power_down = val;} static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg){	struct dwc2_core_params *p = &hsotg->params; 	p->lpm = hsotg->hw_params.lpm_mode;	if (p->lpm) {		p->lpm_clock_gating = true;		p->besl = true;		p->hird_threshold_en = true;		p->hird_threshold = 4;	} else {		p->lpm_clock_gating = false;		p->besl = false;		p->hird_threshold_en = false;	}} /** * dwc2_set_default_params() - Set all core parameters to their

Lines 1–500 of 1083. Load more