/* * OMAP Dual-Mode Timers * * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Tarun Kanti DebBarma <tarun.kanti@ti.com> * Thara Gopinath <thara@ti.com> * * Platform device conversion and hwmod support. * * Copyright (C) 2005 Nokia Corporation * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com> * PWM and clock framwork support by Timo Teras. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * You should have received a copy of the  GNU General Public License along * with this program; if not, write  to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/delay.h>#include <linux/io.h>#include <linux/platform_device.h> #ifndef __CLOCKSOURCE_DMTIMER_H#define __CLOCKSOURCE_DMTIMER_H /* clock sources */#define OMAP_TIMER_SRC_SYS_CLK			0x00#define OMAP_TIMER_SRC_32_KHZ			0x01#define OMAP_TIMER_SRC_EXT_CLK			0x02 /* timer interrupt enable bits */#define OMAP_TIMER_INT_CAPTURE			(1 << 2)#define OMAP_TIMER_INT_OVERFLOW			(1 << 1)#define OMAP_TIMER_INT_MATCH			(1 << 0) /* trigger types */#define OMAP_TIMER_TRIGGER_NONE			0x00#define OMAP_TIMER_TRIGGER_OVERFLOW		0x01#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE	0x02 /* timer capabilities used in hwmod database */#define OMAP_TIMER_SECURE				0x80000000#define OMAP_TIMER_ALWON				0x40000000#define OMAP_TIMER_HAS_PWM				0x20000000#define OMAP_TIMER_NEEDS_RESET				0x10000000#define OMAP_TIMER_HAS_DSP_IRQ				0x08000000 struct omap_dm_timer {}; u32 omap_dm_timer_modify_idlect_mask(u32 inputmask); /* * Do not use the defines below, they are not needed. They should be only * used by dmtimer.c and sys_timer related code. */ /* * The interrupt registers are different between v1 and v2 ip. * These registers are offsets from timer->iobase. */#define OMAP_TIMER_ID_OFFSET		0x00#define OMAP_TIMER_OCP_CFG_OFFSET	0x10 #define OMAP_TIMER_V1_SYS_STAT_OFFSET	0x14#define OMAP_TIMER_V1_STAT_OFFSET	0x18#define OMAP_TIMER_V1_INT_EN_OFFSET	0x1c #define OMAP_TIMER_V2_IRQSTATUS_RAW	0x24#define OMAP_TIMER_V2_IRQSTATUS		0x28#define OMAP_TIMER_V2_IRQENABLE_SET	0x2c#define OMAP_TIMER_V2_IRQENABLE_CLR	0x30 /* * The functional registers have a different base on v1 and v2 ip. * These registers are offsets from timer->func_base. The func_base * is samae as io_base for v1 and io_base + 0x14 for v2 ip. * */#define OMAP_TIMER_V2_FUNC_OFFSET		0x14 #define _OMAP_TIMER_WAKEUP_EN_OFFSET	0x20#define _OMAP_TIMER_CTRL_OFFSET		0x24#define		OMAP_TIMER_CTRL_GPOCFG		(1 << 14)#define		OMAP_TIMER_CTRL_CAPTMODE	(1 << 13)#define		OMAP_TIMER_CTRL_PT		(1 << 12)#define		OMAP_TIMER_CTRL_TCM_LOWTOHIGH	(0x1 << 8)#define		OMAP_TIMER_CTRL_TCM_HIGHTOLOW	(0x2 << 8)#define		OMAP_TIMER_CTRL_TCM_BOTHEDGES	(0x3 << 8)#define		OMAP_TIMER_CTRL_SCPWM		(1 << 7)#define		OMAP_TIMER_CTRL_CE		(1 << 6) /* compare enable */#define		OMAP_TIMER_CTRL_PRE		(1 << 5) /* prescaler enable */#define		OMAP_TIMER_CTRL_PTV_SHIFT	2 /* prescaler value shift */#define		OMAP_TIMER_CTRL_POSTED		(1 << 2)#define		OMAP_TIMER_CTRL_AR		(1 << 1) /* auto-reload enable */#define		OMAP_TIMER_CTRL_ST		(1 << 0) /* start timer */#define _OMAP_TIMER_COUNTER_OFFSET	0x28#define _OMAP_TIMER_LOAD_OFFSET		0x2c#define _OMAP_TIMER_TRIGGER_OFFSET	0x30#define _OMAP_TIMER_WRITE_PEND_OFFSET	0x34#define		WP_NONE			0	/* no write pending bit */#define		WP_TCLR			(1 << 0)#define		WP_TCRR			(1 << 1)#define		WP_TLDR			(1 << 2)#define		WP_TTGR			(1 << 3)#define		WP_TMAR			(1 << 4)#define		WP_TPIR			(1 << 5)#define		WP_TNIR			(1 << 6)#define		WP_TCVR			(1 << 7)#define		WP_TOCR			(1 << 8)#define		WP_TOWR			(1 << 9)#define _OMAP_TIMER_MATCH_OFFSET	0x38#define _OMAP_TIMER_CAPTURE_OFFSET	0x3c#define _OMAP_TIMER_IF_CTRL_OFFSET	0x40#define _OMAP_TIMER_CAPTURE2_OFFSET		0x44	/* TCAR2, 34xx only */#define _OMAP_TIMER_TICK_POS_OFFSET		0x48	/* TPIR, 34xx only */#define _OMAP_TIMER_TICK_NEG_OFFSET		0x4c	/* TNIR, 34xx only */#define _OMAP_TIMER_TICK_COUNT_OFFSET		0x50	/* TCVR, 34xx only */#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET	0x54	/* TOCR, 34xx only */#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET	0x58	/* TOWR, 34xx only */ #endif /* __CLOCKSOURCE_DMTIMER_H */