/* SPDX-License-Identifier: GPL-2.0 *//* * Type definitions for the Microsoft hypervisor. */#ifndef _HV_HVGDK_MINI_H#define _HV_HVGDK_MINI_H #include <linux/types.h>#include <linux/bits.h> struct hv_u128 { u64 low_part; u64 high_part;} __packed; /* NOTE: when adding below, update hv_result_to_string() */#define HV_STATUS_SUCCESS 0x0#define HV_STATUS_INVALID_HYPERCALL_CODE 0x2#define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3#define HV_STATUS_INVALID_ALIGNMENT 0x4#define HV_STATUS_INVALID_PARAMETER 0x5#define HV_STATUS_ACCESS_DENIED 0x6#define HV_STATUS_INVALID_PARTITION_STATE 0x7#define HV_STATUS_OPERATION_DENIED 0x8#define HV_STATUS_UNKNOWN_PROPERTY 0x9#define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA#define HV_STATUS_INSUFFICIENT_MEMORY 0xB#define HV_STATUS_INVALID_PARTITION_ID 0xD#define HV_STATUS_INVALID_VP_INDEX 0xE#define HV_STATUS_NOT_FOUND 0x10#define HV_STATUS_INVALID_PORT_ID 0x11#define HV_STATUS_INVALID_CONNECTION_ID 0x12#define HV_STATUS_INSUFFICIENT_BUFFERS 0x13#define HV_STATUS_NOT_ACKNOWLEDGED 0x14#define HV_STATUS_INVALID_VP_STATE 0x15#define HV_STATUS_NO_RESOURCES 0x1D#define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20#define HV_STATUS_INVALID_LP_INDEX 0x41#define HV_STATUS_INVALID_REGISTER_VALUE 0x50#define HV_STATUS_OPERATION_FAILED 0x71#define HV_STATUS_INSUFFICIENT_ROOT_MEMORY 0x73#define HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY 0x75#define HV_STATUS_TIME_OUT 0x78#define HV_STATUS_CALL_PENDING 0x79#define HV_STATUS_INSUFFICIENT_CONTIGUOUS_ROOT_MEMORY 0x83#define HV_STATUS_VTL_ALREADY_ENABLED 0x86 /* * The Hyper-V TimeRefCount register and the TSC * page provide a guest VM clock with 100ns tick rate */#define HV_CLOCK_HZ (NSEC_PER_SEC / 100) #define HV_HYP_PAGE_SHIFT 12#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))#define HV_HYP_LARGE_PAGE_SHIFT 21 #define HV_PARTITION_ID_INVALID ((u64)0)#define HV_PARTITION_ID_SELF ((u64)-1) /* Hyper-V specific model specific registers (MSRs) */ #if defined(CONFIG_X86)/* HV_X64_SYNTHETIC_MSR */#define HV_X64_MSR_GUEST_OS_ID 0x40000000#define HV_X64_MSR_HYPERCALL 0x40000001#define HV_X64_MSR_VP_INDEX 0x40000002#define HV_X64_MSR_RESET 0x40000003#define HV_X64_MSR_VP_RUNTIME 0x40000010#define HV_X64_MSR_TIME_REF_COUNT 0x40000020#define HV_X64_MSR_REFERENCE_TSC 0x40000021#define HV_X64_MSR_TSC_FREQUENCY 0x40000022#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 /* Define the virtual APIC registers */#define HV_X64_MSR_EOI 0x40000070#define HV_X64_MSR_ICR 0x40000071#define HV_X64_MSR_TPR 0x40000072#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 /* Define synthetic interrupt controller model specific registers. */#define HV_X64_MSR_SCONTROL 0x40000080#define HV_X64_MSR_SVERSION 0x40000081#define HV_X64_MSR_SIEFP 0x40000082#define HV_X64_MSR_SIMP 0x40000083#define HV_X64_MSR_EOM 0x40000084#define HV_X64_MSR_SIRBP 0x40000085#define HV_X64_MSR_SINT0 0x40000090#define HV_X64_MSR_SINT1 0x40000091#define HV_X64_MSR_SINT2 0x40000092#define HV_X64_MSR_SINT3 0x40000093#define HV_X64_MSR_SINT4 0x40000094#define HV_X64_MSR_SINT5 0x40000095#define HV_X64_MSR_SINT6 0x40000096#define HV_X64_MSR_SINT7 0x40000097#define HV_X64_MSR_SINT8 0x40000098#define HV_X64_MSR_SINT9 0x40000099#define HV_X64_MSR_SINT10 0x4000009A#define HV_X64_MSR_SINT11 0x4000009B#define HV_X64_MSR_SINT12 0x4000009C#define HV_X64_MSR_SINT13 0x4000009D#define HV_X64_MSR_SINT14 0x4000009E#define HV_X64_MSR_SINT15 0x4000009F /* Define synthetic interrupt controller model specific registers for nested hypervisor */#define HV_X64_MSR_NESTED_SCONTROL 0x40001080#define HV_X64_MSR_NESTED_SVERSION 0x40001081#define HV_X64_MSR_NESTED_SIEFP 0x40001082#define HV_X64_MSR_NESTED_SIMP 0x40001083#define HV_X64_MSR_NESTED_EOM 0x40001084#define HV_X64_MSR_NESTED_SINT0 0x40001090 /* * Synthetic Timer MSRs. Four timers per vcpu. */#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0#define HV_X64_MSR_STIMER0_COUNT 0x400000B1#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2#define HV_X64_MSR_STIMER1_COUNT 0x400000B3#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4#define HV_X64_MSR_STIMER2_COUNT 0x400000B5#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6#define HV_X64_MSR_STIMER3_COUNT 0x400000B7 /* Hyper-V guest idle MSR */#define HV_X64_MSR_GUEST_IDLE 0x400000F0 /* Hyper-V guest crash notification MSR's */#define HV_X64_MSR_CRASH_P0 0x40000100#define HV_X64_MSR_CRASH_P1 0x40000101#define HV_X64_MSR_CRASH_P2 0x40000102#define HV_X64_MSR_CRASH_P3 0x40000103#define HV_X64_MSR_CRASH_P4 0x40000104#define HV_X64_MSR_CRASH_CTL 0x40000105 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) #define HV_X64_MSR_CRASH_PARAMS \ (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) #define HV_IPI_LOW_VECTOR 0x10#define HV_IPI_HIGH_VECTOR 0xff #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) /* Hyper-V Enlightened VMCS version mask in nested features CPUID */#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 /* Number of XMM registers used in hypercall input/output */#define HV_HYPERCALL_MAX_XMM_REGISTERS 6 struct hv_reenlightenment_control { u64 vector : 8; u64 reserved1 : 8; u64 enabled : 1; u64 reserved2 : 15; u64 target_vp : 32;} __packed; struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ u64 inprogress : 1; u64 reserved : 63;} __packed; struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ u64 enabled : 1; u64 reserved : 63;} __packed; /* TSC emulation after migration */#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) #endif /* CONFIG_X86 */ struct hv_output_get_partition_id { u64 partition_id;} __packed; /* HV_CRASH_CTL_REG_CONTENTS */#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) union hv_reference_tsc_msr { u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 pfn : 52; } __packed;}; /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */#define HV_MAX_SPARSE_VCPU_BANKS (64)/* The number of vCPUs in one sparse bank */#define HV_VCPUS_PER_SPARSE_BANK (64) /* * Some of Hyper-V structs do not use hv_vpset where linux uses them. * * struct hv_vpset is usually used as part of hypercall input. The portion * that counts as "fixed size input header" vs. "variable size input header" * varies per hypercall. See comments at relevant hypercall call sites as to * how the "valid_bank_mask" field should be accounted. */struct hv_vpset { /* HV_VP_SET */ u64 format; u64 valid_bank_mask; u64 bank_contents[];} __packed; /* * Version info reported by hypervisor * Changed to a union for convenience */union hv_hypervisor_version_info { struct { u32 build_number; u32 minor_version : 16; u32 major_version : 16; u32 service_pack; u32 service_number : 24; u32 service_branch : 8; }; struct { u32 eax; u32 ebx; u32 ecx; u32 edx; };}; /* HV_CPUID_FUNCTION */#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000#define HYPERV_CPUID_INTERFACE 0x40000001#define HYPERV_CPUID_VERSION 0x40000002#define HYPERV_CPUID_FEATURES 0x40000003#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005#define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A#define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081#define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082/* Support for the extended IOAPIC RTE format */#define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2)#define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3) #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000#define HYPERV_CPUID_MIN 0x40000005#define HYPERV_CPUID_MAX 0x4000ffff /* * HV_X64_HYPERVISOR_FEATURES (EAX), or * HV_PARTITION_PRIVILEGE_MASK [31-0] */#define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)#define HV_MSR_SYNIC_AVAILABLE BIT(2)#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)#define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4)#define HV_MSR_HYPERCALL_AVAILABLE BIT(5)#define HV_MSR_VP_INDEX_AVAILABLE BIT(6)#define HV_MSR_RESET_AVAILABLE BIT(7)#define HV_MSR_STAT_PAGES_AVAILABLE BIT(8)#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)#define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10)#define HV_ACCESS_FREQUENCY_MSRS BIT(11)#define HV_ACCESS_REENLIGHTENMENT BIT(13)#define HV_ACCESS_TSC_INVARIANT BIT(15) /* * HV_X64_HYPERVISOR_FEATURES (EBX), or * HV_PARTITION_PRIVILEGE_MASK [63-32] */#define HV_CREATE_PARTITIONS BIT(0)#define HV_ACCESS_PARTITION_ID BIT(1)#define HV_ACCESS_MEMORY_POOL BIT(2)#define HV_ADJUST_MESSAGE_BUFFERS BIT(3)#define HV_POST_MESSAGES BIT(4)#define HV_SIGNAL_EVENTS BIT(5)#define HV_CREATE_PORT BIT(6)#define HV_CONNECT_PORT BIT(7)#define HV_ACCESS_STATS BIT(8)#define HV_DEBUGGING BIT(11)#define HV_CPU_MANAGEMENT BIT(12)#define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20)#define HV_ISOLATION BIT(22) #if defined(CONFIG_X86)/* HV_X64_HYPERVISOR_FEATURES (EDX) */#define HV_X64_MWAIT_AVAILABLE BIT(0)#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1)#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2)#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3)#define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4)#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5)#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8)#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10)#define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11)#define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14)/* * Support for returning hypercall output block via XMM * registers is available */#define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15)/* stimer Direct Mode is available */#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) /* * Implementation recommendations. Indicates which behaviors the hypervisor * recommends the OS implement for optimal performance. * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. *//* HV_X64_ENLIGHTENMENT_INFORMATION */#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0)#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1)#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2)#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3)#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4)#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5)#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9)#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10)#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11)#define HV_X64_HYPERV_NESTED BIT(12)#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14)#define HV_X64_USE_MMIO_HYPERCALLS BIT(21) /* * CPU management features identification. * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. */#define HV_X64_START_LOGICAL_PROCESSOR BIT(0)#define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1)#define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2)#define HV_X64_RESERVED_IDENTITY_BIT BIT(31) /* * Virtual processor will never share a physical core with another virtual * processor, except for virtual processors that are reported as sibling SMT * threads. */#define HV_X64_NO_NONARCH_CORESHARING BIT(18) /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */#define HV_X64_NESTED_DIRECT_FLUSH BIT(17)#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)#define HV_X64_NESTED_MSR_BITMAP BIT(19) /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */#define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) /* * This is specific to AMD and specifies that enlightened TLB flush is * supported. If guest opts in to this feature, ASID invalidations only * flushes gva -> hpa mapping entries. To flush the TLB entries derived * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace * or HvFlushGuestPhysicalAddressList). */#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */#define HV_PARAVISOR_PRESENT BIT(0) /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */#define HV_ISOLATION_TYPE GENMASK(3, 0)#define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5)#define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) /* HYPERV_CPUID_FEATURES.ECX bits. */#define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9)#define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) enum hv_isolation_type { HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ HV_ISOLATION_TYPE_VBS = 1, HV_ISOLATION_TYPE_SNP = 2, HV_ISOLATION_TYPE_TDX = 3}; union hv_x64_msr_hypercall_contents { u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 guest_physical_address : 52; } __packed;};#endif /* CONFIG_X86 */ #if defined(CONFIG_ARM64)#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8)#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13)#endif /* CONFIG_ARM64 */ #if defined(CONFIG_X86)#define HV_MAXIMUM_PROCESSORS 2048#elif defined(CONFIG_ARM64) /* CONFIG_X86 */#define HV_MAXIMUM_PROCESSORS 320#endif /* CONFIG_ARM64 */ #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1)#define HV_VP_INDEX_SELF ((u32)-2)#define HV_ANY_VP ((u32)-1) union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 pfn : 52; } __packed;}; /* Declare the various hypercall operations. *//* HV_CALL_CODE */#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003#define HVCALL_GET_LOGICAL_PROCESSOR_RUN_TIME 0x0004#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008#define HVCALL_SEND_IPI 0x000b#define HVCALL_ENABLE_VP_VTL 0x000f#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014#define HVCALL_SEND_IPI_EX 0x0015#define HVCALL_CREATE_PARTITION 0x0040#define HVCALL_INITIALIZE_PARTITION 0x0041#define HVCALL_FINALIZE_PARTITION 0x0042#define HVCALL_DELETE_PARTITION 0x0043#define HVCALL_GET_PARTITION_PROPERTY 0x0044#define HVCALL_SET_PARTITION_PROPERTY 0x0045#define HVCALL_GET_PARTITION_ID 0x0046#define HVCALL_DEPOSIT_MEMORY 0x0048#define HVCALL_WITHDRAW_MEMORY 0x0049#define HVCALL_MAP_GPA_PAGES 0x004b#define HVCALL_UNMAP_GPA_PAGES 0x004c#define HVCALL_INSTALL_INTERCEPT 0x004d#define HVCALL_CREATE_VP 0x004e#define HVCALL_DELETE_VP 0x004f#define HVCALL_GET_VP_REGISTERS 0x0050#define HVCALL_SET_VP_REGISTERS 0x0051#define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052#define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056#define HVCALL_DELETE_PORT 0x0058#define HVCALL_DISCONNECT_PORT 0x005b#define HVCALL_POST_MESSAGE 0x005c#define HVCALL_SIGNAL_EVENT 0x005d#define HVCALL_POST_DEBUG_DATA 0x0069#define HVCALL_RETRIEVE_DEBUG_DATA 0x006a#define HVCALL_RESET_DEBUG_SESSION 0x006b#define HVCALL_MAP_STATS_PAGE 0x006c#define HVCALL_UNMAP_STATS_PAGE 0x006d#define HVCALL_SET_SYSTEM_PROPERTY 0x006f#define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076#define HVCALL_GET_SYSTEM_PROPERTY 0x007b#define HVCALL_MAP_DEVICE_INTERRUPT 0x007c#define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d#define HVCALL_RETARGET_INTERRUPT 0x007e#define HVCALL_NOTIFY_PARTITION_EVENT 0x0087#define HVCALL_ENTER_SLEEP_STATE 0x0084#define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b#define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091#define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094#define HVCALL_CREATE_PORT 0x0095#define HVCALL_CONNECT_PORT 0x0096#define HVCALL_START_VP 0x0099#define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0#define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0#define HVCALL_POST_MESSAGE_DIRECT 0x00c1#define HVCALL_DISPATCH_VP 0x00c2#define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9#define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7#define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8#define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db#define HVCALL_MAP_VP_STATE_PAGE 0x00e1#define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2#define HVCALL_GET_VP_STATE 0x00e3#define HVCALL_SET_VP_STATE 0x00e4#define HVCALL_GET_VP_CPUID_VALUES 0x00f4Lines 1–500 of 1543. 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/* SPDX-License-Identifier: GPL-2.0 */ /* * Type definitions for the Microsoft hypervisor. */ #ifndef _HV_HVGDK_MINI_H #define _HV_HVGDK_MINI_H #include <linux/types.h> #include <linux/bits.h> struct hv_u128 { u64 low_part; u64 high_part; } __packed; /* NOTE: when adding below, update hv_result_to_string() */ #define HV_STATUS_SUCCESS 0x0 #define HV_STATUS_INVALID_HYPERCALL_CODE 0x2 #define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3 #define HV_STATUS_INVALID_ALIGNMENT 0x4 #define HV_STATUS_INVALID_PARAMETER 0x5 #define HV_STATUS_ACCESS_DENIED 0x6 #define HV_STATUS_INVALID_PARTITION_STATE 0x7 #define HV_STATUS_OPERATION_DENIED 0x8 #define HV_STATUS_UNKNOWN_PROPERTY 0x9 #define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA #define HV_STATUS_INSUFFICIENT_MEMORY 0xB #define HV_STATUS_INVALID_PARTITION_ID 0xD #define HV_STATUS_INVALID_VP_INDEX 0xE #define HV_STATUS_NOT_FOUND 0x10 #define HV_STATUS_INVALID_PORT_ID 0x11 #define HV_STATUS_INVALID_CONNECTION_ID 0x12 #define HV_STATUS_INSUFFICIENT_BUFFERS 0x13 #define HV_STATUS_NOT_ACKNOWLEDGED 0x14 #define HV_STATUS_INVALID_VP_STATE 0x15 #define HV_STATUS_NO_RESOURCES 0x1D #define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20 #define HV_STATUS_INVALID_LP_INDEX 0x41 #define HV_STATUS_INVALID_REGISTER_VALUE 0x50 #define HV_STATUS_OPERATION_FAILED 0x71 #define HV_STATUS_INSUFFICIENT_ROOT_MEMORY 0x73 #define HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY 0x75 #define HV_STATUS_TIME_OUT 0x78 #define HV_STATUS_CALL_PENDING 0x79 #define HV_STATUS_INSUFFICIENT_CONTIGUOUS_ROOT_MEMORY 0x83 #define HV_STATUS_VTL_ALREADY_ENABLED 0x86 /* * The Hyper-V TimeRefCount register and the TSC * page provide a guest VM clock with 100ns tick rate */ #define HV_CLOCK_HZ (NSEC_PER_SEC / 100) #define HV_HYP_PAGE_SHIFT 12 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT) #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1)) #define HV_HYP_LARGE_PAGE_SHIFT 21 #define HV_PARTITION_ID_INVALID ((u64)0) #define HV_PARTITION_ID_SELF ((u64)-1) /* Hyper-V specific model specific registers (MSRs) */ #if defined(CONFIG_X86) /* HV_X64_SYNTHETIC_MSR */ #define HV_X64_MSR_GUEST_OS_ID 0x40000000 #define HV_X64_MSR_HYPERCALL 0x40000001 #define HV_X64_MSR_VP_INDEX 0x40000002 #define HV_X64_MSR_RESET 0x40000003 #define HV_X64_MSR_VP_RUNTIME 0x40000010 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 /* Define the virtual APIC registers */ #define HV_X64_MSR_EOI 0x40000070 #define HV_X64_MSR_ICR 0x40000071 #define HV_X64_MSR_TPR 0x40000072 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 /* Define synthetic interrupt controller model specific registers. */ #define HV_X64_MSR_SCONTROL 0x40000080 #define HV_X64_MSR_SVERSION 0x40000081 #define HV_X64_MSR_SIEFP 0x40000082 #define HV_X64_MSR_SIMP 0x40000083 #define HV_X64_MSR_EOM 0x40000084 #define HV_X64_MSR_SIRBP 0x40000085 #define HV_X64_MSR_SINT0 0x40000090 #define HV_X64_MSR_SINT1 0x40000091 #define HV_X64_MSR_SINT2 0x40000092 #define HV_X64_MSR_SINT3 0x40000093 #define HV_X64_MSR_SINT4 0x40000094 #define HV_X64_MSR_SINT5 0x40000095 #define HV_X64_MSR_SINT6 0x40000096 #define HV_X64_MSR_SINT7 0x40000097 #define HV_X64_MSR_SINT8 0x40000098 #define HV_X64_MSR_SINT9 0x40000099 #define HV_X64_MSR_SINT10 0x4000009A #define HV_X64_MSR_SINT11 0x4000009B #define HV_X64_MSR_SINT12 0x4000009C #define HV_X64_MSR_SINT13 0x4000009D #define HV_X64_MSR_SINT14 0x4000009E #define HV_X64_MSR_SINT15 0x4000009F /* Define synthetic interrupt controller model specific registers for nested hypervisor */ #define HV_X64_MSR_NESTED_SCONTROL 0x40001080 #define HV_X64_MSR_NESTED_SVERSION 0x40001081 #define HV_X64_MSR_NESTED_SIEFP 0x40001082 #define HV_X64_MSR_NESTED_SIMP 0x40001083 #define HV_X64_MSR_NESTED_EOM 0x40001084 #define HV_X64_MSR_NESTED_SINT0 0x40001090 /* * Synthetic Timer MSRs. Four timers per vcpu. */ #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 /* Hyper-V guest idle MSR */ #define HV_X64_MSR_GUEST_IDLE 0x400000F0 /* Hyper-V guest crash notification MSR's */ #define HV_X64_MSR_CRASH_P0 0x40000100 #define HV_X64_MSR_CRASH_P1 0x40000101 #define HV_X64_MSR_CRASH_P2 0x40000102 #define HV_X64_MSR_CRASH_P3 0x40000103 #define HV_X64_MSR_CRASH_P4 0x40000104 #define HV_X64_MSR_CRASH_CTL 0x40000105 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) #define HV_X64_MSR_CRASH_PARAMS \ (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) #define HV_IPI_LOW_VECTOR 0x10 #define HV_IPI_HIGH_VECTOR 0xff #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 /* Number of XMM registers used in hypercall input/output */ #define HV_HYPERCALL_MAX_XMM_REGISTERS 6 struct hv_reenlightenment_control { u64 vector : 8; u64 reserved1 : 8; u64 enabled : 1; u64 reserved2 : 15; u64 target_vp : 32; } __packed; struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */ u64 inprogress : 1; u64 reserved : 63; } __packed; struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */ u64 enabled : 1; u64 reserved : 63; } __packed; /* TSC emulation after migration */ #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 #define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0) #endif /* CONFIG_X86 */ struct hv_output_get_partition_id { u64 partition_id; } __packed; /* HV_CRASH_CTL_REG_CONTENTS */ #define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62) #define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63) union hv_reference_tsc_msr { u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 pfn : 52; } __packed; }; /* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */ #define HV_MAX_SPARSE_VCPU_BANKS (64) /* The number of vCPUs in one sparse bank */ #define HV_VCPUS_PER_SPARSE_BANK (64) /* * Some of Hyper-V structs do not use hv_vpset where linux uses them. * * struct hv_vpset is usually used as part of hypercall input. The portion * that counts as "fixed size input header" vs. "variable size input header" * varies per hypercall. See comments at relevant hypercall call sites as to * how the "valid_bank_mask" field should be accounted. */ struct hv_vpset { /* HV_VP_SET */ u64 format; u64 valid_bank_mask; u64 bank_contents[]; } __packed; /* * Version info reported by hypervisor * Changed to a union for convenience */ union hv_hypervisor_version_info { struct { u32 build_number; u32 minor_version : 16; u32 major_version : 16; u32 service_pack; u32 service_number : 24; u32 service_branch : 8; }; struct { u32 eax; u32 ebx; u32 ecx; u32 edx; }; }; /* HV_CPUID_FUNCTION */ #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 #define HYPERV_CPUID_INTERFACE 0x40000001 #define HYPERV_CPUID_VERSION 0x40000002 #define HYPERV_CPUID_FEATURES 0x40000003 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A #define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C #define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081 #define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */ #define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082 /* Support for the extended IOAPIC RTE format */ #define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2) #define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3) #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 #define HYPERV_CPUID_MIN 0x40000005 #define HYPERV_CPUID_MAX 0x4000ffff /* * HV_X64_HYPERVISOR_FEATURES (EAX), or * HV_PARTITION_PRIVILEGE_MASK [31-0] */ #define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0) #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1) #define HV_MSR_SYNIC_AVAILABLE BIT(2) #define HV_MSR_SYNTIMER_AVAILABLE BIT(3) #define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4) #define HV_MSR_HYPERCALL_AVAILABLE BIT(5) #define HV_MSR_VP_INDEX_AVAILABLE BIT(6) #define HV_MSR_RESET_AVAILABLE BIT(7) #define HV_MSR_STAT_PAGES_AVAILABLE BIT(8) #define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9) #define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10) #define HV_ACCESS_FREQUENCY_MSRS BIT(11) #define HV_ACCESS_REENLIGHTENMENT BIT(13) #define HV_ACCESS_TSC_INVARIANT BIT(15) /* * HV_X64_HYPERVISOR_FEATURES (EBX), or * HV_PARTITION_PRIVILEGE_MASK [63-32] */ #define HV_CREATE_PARTITIONS BIT(0) #define HV_ACCESS_PARTITION_ID BIT(1) #define HV_ACCESS_MEMORY_POOL BIT(2) #define HV_ADJUST_MESSAGE_BUFFERS BIT(3) #define HV_POST_MESSAGES BIT(4) #define HV_SIGNAL_EVENTS BIT(5) #define HV_CREATE_PORT BIT(6) #define HV_CONNECT_PORT BIT(7) #define HV_ACCESS_STATS BIT(8) #define HV_DEBUGGING BIT(11) #define HV_CPU_MANAGEMENT BIT(12) #define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20) #define HV_ISOLATION BIT(22) #if defined(CONFIG_X86) /* HV_X64_HYPERVISOR_FEATURES (EDX) */ #define HV_X64_MWAIT_AVAILABLE BIT(0) #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4) #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) #define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14) /* * Support for returning hypercall output block via XMM * registers is available */ #define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15) /* stimer Direct Mode is available */ #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) /* * Implementation recommendations. Indicates which behaviors the hypervisor * recommends the OS implement for optimal performance. * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. */ /* HV_X64_ENLIGHTENMENT_INFORMATION */ #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) #define HV_X64_HYPERV_NESTED BIT(12) #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) #define HV_X64_USE_MMIO_HYPERCALLS BIT(21) /* * CPU management features identification. * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits. */ #define HV_X64_START_LOGICAL_PROCESSOR BIT(0) #define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1) #define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2) #define HV_X64_RESERVED_IDENTITY_BIT BIT(31) /* * Virtual processor will never share a physical core with another virtual * processor, except for virtual processors that are reported as sibling SMT * threads. */ #define HV_X64_NO_NONARCH_CORESHARING BIT(18) /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) #define HV_X64_NESTED_MSR_BITMAP BIT(19) /* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */ #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0) /* * This is specific to AMD and specifies that enlightened TLB flush is * supported. If guest opts in to this feature, ASID invalidations only * flushes gva -> hpa mapping entries. To flush the TLB entries derived * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace * or HvFlushGuestPhysicalAddressList). */ #define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22) /* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */ #define HV_PARAVISOR_PRESENT BIT(0) /* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */ #define HV_ISOLATION_TYPE GENMASK(3, 0) #define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5) #define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6) /* HYPERV_CPUID_FEATURES.ECX bits. */ #define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9) #define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10) enum hv_isolation_type { HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */ HV_ISOLATION_TYPE_VBS = 1, HV_ISOLATION_TYPE_SNP = 2, HV_ISOLATION_TYPE_TDX = 3 }; union hv_x64_msr_hypercall_contents { u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 guest_physical_address : 52; } __packed; }; #endif /* CONFIG_X86 */ #if defined(CONFIG_ARM64) #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8) #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13) #endif /* CONFIG_ARM64 */ #if defined(CONFIG_X86) #define HV_MAXIMUM_PROCESSORS 2048 #elif defined(CONFIG_ARM64) /* CONFIG_X86 */ #define HV_MAXIMUM_PROCESSORS 320 #endif /* CONFIG_ARM64 */ #define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1) #define HV_VP_INDEX_SELF ((u32)-2) #define HV_ANY_VP ((u32)-1) union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */ u64 as_uint64; struct { u64 enable : 1; u64 reserved : 11; u64 pfn : 52; } __packed; }; /* Declare the various hypercall operations. */ /* HV_CALL_CODE */ #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003 #define HVCALL_GET_LOGICAL_PROCESSOR_RUN_TIME 0x0004 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008 #define HVCALL_SEND_IPI 0x000b #define HVCALL_ENABLE_VP_VTL 0x000f #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014 #define HVCALL_SEND_IPI_EX 0x0015 #define HVCALL_CREATE_PARTITION 0x0040 #define HVCALL_INITIALIZE_PARTITION 0x0041 #define HVCALL_FINALIZE_PARTITION 0x0042 #define HVCALL_DELETE_PARTITION 0x0043 #define HVCALL_GET_PARTITION_PROPERTY 0x0044 #define HVCALL_SET_PARTITION_PROPERTY 0x0045 #define HVCALL_GET_PARTITION_ID 0x0046 #define HVCALL_DEPOSIT_MEMORY 0x0048 #define HVCALL_WITHDRAW_MEMORY 0x0049 #define HVCALL_MAP_GPA_PAGES 0x004b #define HVCALL_UNMAP_GPA_PAGES 0x004c #define HVCALL_INSTALL_INTERCEPT 0x004d #define HVCALL_CREATE_VP 0x004e #define HVCALL_DELETE_VP 0x004f #define HVCALL_GET_VP_REGISTERS 0x0050 #define HVCALL_SET_VP_REGISTERS 0x0051 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052 #define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056 #define HVCALL_DELETE_PORT 0x0058 #define HVCALL_DISCONNECT_PORT 0x005b #define HVCALL_POST_MESSAGE 0x005c #define HVCALL_SIGNAL_EVENT 0x005d #define HVCALL_POST_DEBUG_DATA 0x0069 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a #define HVCALL_RESET_DEBUG_SESSION 0x006b #define HVCALL_MAP_STATS_PAGE 0x006c #define HVCALL_UNMAP_STATS_PAGE 0x006d #define HVCALL_SET_SYSTEM_PROPERTY 0x006f #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076 #define HVCALL_GET_SYSTEM_PROPERTY 0x007b #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d #define HVCALL_RETARGET_INTERRUPT 0x007e #define HVCALL_NOTIFY_PARTITION_EVENT 0x0087 #define HVCALL_ENTER_SLEEP_STATE 0x0084 #define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094 #define HVCALL_CREATE_PORT 0x0095 #define HVCALL_CONNECT_PORT 0x0096 #define HVCALL_START_VP 0x0099 #define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0 #define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0 #define HVCALL_POST_MESSAGE_DIRECT 0x00c1 #define HVCALL_DISPATCH_VP 0x00c2 #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db #define HVCALL_MAP_VP_STATE_PAGE 0x00e1 #define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2 #define HVCALL_GET_VP_STATE 0x00e3 #define HVCALL_SET_VP_STATE 0x00e4 #define HVCALL_GET_VP_CPUID_VALUES 0x00f4