/* SPDX-License-Identifier: GPL-2.0-only *//* * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@kernel.org> * * Info: * Contains standard defines and IDs for NAND flash devices * * Changelog: * See git changelog. */#ifndef __LINUX_MTD_RAWNAND_H#define __LINUX_MTD_RAWNAND_H #include <linux/mtd/mtd.h>#include <linux/mtd/nand.h>#include <linux/mtd/flashchip.h>#include <linux/mtd/bbm.h>#include <linux/mtd/jedec.h>#include <linux/mtd/onfi.h>#include <linux/mutex.h>#include <linux/of.h>#include <linux/types.h> struct nand_chip;struct gpio_desc; /* The maximum number of NAND chips in an array */#define NAND_MAX_CHIPS 8 /* * Constants for hardware specific CLE/ALE/NCE function * * These are bits which can be or'ed to set/clear multiple * bits in one go. *//* Select the chip by setting nCE to low */#define NAND_NCE 0x01/* Select the command latch by setting CLE to high */#define NAND_CLE 0x02/* Select the address latch by setting ALE to high */#define NAND_ALE 0x04 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)#define NAND_CTRL_CHANGE 0x80 /* * Standard NAND flash commands */#define NAND_CMD_READ0 0#define NAND_CMD_READ1 1#define NAND_CMD_RNDOUT 5#define NAND_CMD_PAGEPROG 0x10#define NAND_CMD_READOOB 0x50#define NAND_CMD_ERASE1 0x60#define NAND_CMD_STATUS 0x70#define NAND_CMD_SEQIN 0x80#define NAND_CMD_RNDIN 0x85#define NAND_CMD_READID 0x90#define NAND_CMD_ERASE2 0xd0#define NAND_CMD_PARAM 0xec#define NAND_CMD_GET_FEATURES 0xee#define NAND_CMD_SET_FEATURES 0xef#define NAND_CMD_RESET 0xff /* Extended commands for large page devices */#define NAND_CMD_READSTART 0x30#define NAND_CMD_READCACHESEQ 0x31#define NAND_CMD_READCACHEEND 0x3f#define NAND_CMD_RNDOUTSTART 0xE0#define NAND_CMD_CACHEDPROG 0x15 #define NAND_CMD_NONE -1 /* Status bits */#define NAND_STATUS_FAIL 0x01#define NAND_STATUS_FAIL_N1 0x02#define NAND_STATUS_TRUE_READY 0x20#define NAND_STATUS_READY 0x40#define NAND_STATUS_WP 0x80 #define NAND_DATA_IFACE_CHECK_ONLY -1 /* * Constants for Hardware ECC *//* Reset Hardware ECC for read */#define NAND_ECC_READ 0/* Reset Hardware ECC for write */#define NAND_ECC_WRITE 1/* Enable Hardware ECC before syndrome is read back from flash */#define NAND_ECC_READSYN 2 /* * Enable generic NAND 'page erased' check. This check is only done when * ecc.correct() returns -EBADMSG. * Set this flag if your implementation does not fix bitflips in erased * pages and you want to rely on the default implementation. */#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) /* * Option constants for bizarre disfunctionality and real * features. */ /* Buswidth is 16 bit */#define NAND_BUSWIDTH_16 BIT(1) /* * When using software implementation of Hamming, we can specify which byte * ordering should be used. */#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) /* Chip has cache program function */#define NAND_CACHEPRG BIT(3)/* Options valid for Samsung large page devices */#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG /* * Chip requires ready check on read (for auto-incremented sequential read). * True only for small page devices; large page devices do not support * autoincrement. */#define NAND_NEED_READRDY BIT(8) /* Chip does not allow subpage writes */#define NAND_NO_SUBPAGE_WRITE BIT(9) /* Device is one of 'new' xD cards that expose fake nand command set */#define NAND_BROKEN_XD BIT(10) /* Device behaves just like nand, but is readonly */#define NAND_ROM BIT(11) /* Device supports subpage reads */#define NAND_SUBPAGE_READ BIT(12)/* Macros to identify the above */#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) /* * Some MLC NANDs need data scrambling to limit bitflips caused by repeated * patterns. */#define NAND_NEED_SCRAMBLING BIT(13) /* Device needs 3rd row address cycle */#define NAND_ROW_ADDR_3 BIT(14) /* Non chip related options *//* This option skips the bbt scan during initialization. */#define NAND_SKIP_BBTSCAN BIT(16)/* Chip may not exist, so silence any errors in scan */#define NAND_SCAN_SILENT_NODEV BIT(18) /* * Autodetect nand buswidth with readid/onfi. * This suppose the driver will configure the hardware in 8 bits mode * when calling nand_scan_ident, and update its configuration * before calling nand_scan_tail. */#define NAND_BUSWIDTH_AUTO BIT(19) /* * This option could be defined by controller drivers to protect against * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers */#define NAND_USES_DMA BIT(20) /* * In case your controller is implementing ->legacy.cmd_ctrl() and is relying * on the default ->cmdfunc() implementation, you may want to let the core * handle the tCCS delay which is required when a column change (RNDIN or * RNDOUT) is requested. * If your controller already takes care of this delay, you don't need to set * this flag. */#define NAND_WAIT_TCCS BIT(21) /* * Whether the NAND chip is a boot medium. Drivers might use this information * to select ECC algorithms supported by the boot ROM or similar restrictions. */#define NAND_IS_BOOT_MEDIUM BIT(22) /* * Do not try to tweak the timings at runtime. This is needed when the * controller initializes the timings on itself or when it relies on * configuration done by the bootloader. */#define NAND_KEEP_TIMINGS BIT(23) /* * There are different places where the manufacturer stores the factory bad * block markers. * * Position within the block: Each of these pages needs to be checked for a * bad block marking pattern. */#define NAND_BBM_FIRSTPAGE BIT(24)#define NAND_BBM_SECONDPAGE BIT(25)#define NAND_BBM_LASTPAGE BIT(26) /* * Some controllers with pipelined ECC engines override the BBM marker with * data or ECC bytes, thus making bad block detection through bad block marker * impossible. Let's flag those chips so the core knows it shouldn't check the * BBM and consider all blocks good. */#define NAND_NO_BBM_QUIRK BIT(27) /* Cell info constants */#define NAND_CI_CHIPNR_MSK 0x03#define NAND_CI_CELLTYPE_MSK 0x0C#define NAND_CI_CELLTYPE_SHIFT 2 /* Position within the OOB data of the page */#define NAND_BBM_POS_SMALL 5#define NAND_BBM_POS_LARGE 0 /** * struct nand_parameters - NAND generic parameters from the parameter page * @model: Model name * @supports_set_get_features: The NAND chip supports setting/getting features * @supports_read_cache: The NAND chip supports read cache operations * @set_feature_list: Bitmap of features that can be set * @get_feature_list: Bitmap of features that can be get * @onfi: ONFI specific parameters */struct nand_parameters { /* Generic parameters */ const char *model; bool supports_set_get_features; bool supports_read_cache; DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); /* ONFI parameters */ struct onfi_params *onfi;}; /* The maximum expected count of bytes in the NAND ID sequence */#define NAND_MAX_ID_LEN 8 /** * struct nand_id - NAND id structure * @data: buffer containing the id bytes. * @len: ID length. */struct nand_id { u8 data[NAND_MAX_ID_LEN]; int len;}; /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step * @strengths: array of supported strengths * @nstrengths: number of supported strengths */struct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths;}; /** * struct nand_ecc_caps - capability of ECC engine * @stepinfos: array of ECC step information * @nstepinfos: number of ECC step information * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step */struct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength);}; /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \static const int __name##_strengths[] = { __VA_ARGS__ }; \static const struct nand_ecc_step_info __name##_stepinfo = { \ .stepsize = __step, \ .strengths = __name##_strengths, \ .nstrengths = ARRAY_SIZE(__name##_strengths), \}; \static const struct nand_ecc_caps __name = { \ .stepinfos = &__name##_stepinfo, \ .nstepinfos = 1, \ .calc_ecc_bytes = __calc, \} /** * struct nand_ecc_ctrl - Control structure for ECC * @engine_type: ECC engine type * @placement: OOB bytes placement * @algo: ECC algorithm * @steps: number of ECC steps per page * @size: data bytes per ECC step * @bytes: ECC bytes per step * @strength: max number of correctible bits per ECC step * @total: total number of ECC bytes per page * @prepad: padding information for syndrome based ECC generators * @postpad: padding information for syndrome based ECC generators * @options: ECC specific options (see NAND_ECC_XXX flags defined above) * @calc_buf: buffer for calculated ECC, size is oobsize. * @code_buf: buffer for ECC read from flash, size is oobsize. * @hwctl: function to control hardware ECC generator. Must only * be provided if an hardware ECC is available * @calculate: function for ECC calculation or readback from ECC hardware * @correct: function for ECC correction, matching to ECC generator (sw/hw). * Should return a positive number representing the number of * corrected bitflips, -EBADMSG if the number of bitflips exceed * ECC strength, or any other error code if the error is not * directly related to correction. * If -EBADMSG is returned the input buffers should be left * untouched. * @read_page_raw: function to read a raw page without ECC. This function * should hide the specific layout used by the ECC * controller and always return contiguous in-band and * out-of-band data even if they're not stored * contiguously on the NAND chip (e.g. * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and * out-of-band data). * @write_page_raw: function to write a raw page without ECC. This function * should hide the specific layout used by the ECC * controller and consider the passed data as contiguous * in-band and out-of-band data. ECC controller is * responsible for doing the appropriate transformations * to adapt to its specific layout (e.g. * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and * out-of-band data). * @read_page: function to read a page according to the ECC generator * requirements; returns maximum number of bitflips corrected in * any single ECC step, -EIO hw error * @read_subpage: function to read parts of the page covered by ECC; * returns same as read_page() * @write_subpage: function to write parts of the page covered by ECC. * @write_page: function to write a page according to the ECC generator * requirements. * @write_oob_raw: function to write chip OOB data without ECC * @read_oob_raw: function to read chip OOB data without ECC * @read_oob: function to read chip OOB data * @write_oob: function to write chip OOB data */struct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page);}; /** * struct nand_sdr_timings - SDR NAND chip timings * * This struct defines the timing requirements of a SDR NAND chip. * These information can be found in every NAND datasheets and the timings * meaning are described in the ONFI specifications: * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf * (chapter 4.15 Timing Parameters) * * All these timings are expressed in picoseconds. * * @tBERS_max: Block erase time * @tCCS_min: Change column setup time * @tPROG_max: Page program time * @tR_max: Page read time * @tALH_min: ALE hold time * @tADL_min: ALE to data loading time * @tALS_min: ALE setup time * @tAR_min: ALE to RE# delay * @tCEA_max: CE# access time * @tCEH_min: CE# high hold time * @tCH_min: CE# hold time * @tCHZ_max: CE# high to output hi-Z * @tCLH_min: CLE hold time * @tCLR_min: CLE to RE# delay * @tCLS_min: CLE setup time * @tCOH_min: CE# high to output hold * @tCS_min: CE# setup time * @tDH_min: Data hold time * @tDS_min: Data setup time * @tFEAT_max: Busy time for Set Features and Get Features * @tIR_min: Output hi-Z to RE# low * @tITC_max: Interface and Timing Mode Change time * @tRC_min: RE# cycle time * @tREA_max: RE# access time * @tREH_min: RE# high hold time * @tRHOH_min: RE# high to output hold * @tRHW_min: RE# high to WE# low * @tRHZ_max: RE# high to output hi-Z * @tRLOH_min: RE# low to output hold * @tRP_min: RE# pulse width * @tRR_min: Ready to RE# low (data only) * @tRST_max: Device reset time, measured from the falling edge of R/B# to the * rising edge of R/B#. * @tWB_max: WE# high to SR[6] low * @tWC_min: WE# cycle time * @tWH_min: WE# high hold time * @tWHR_min: WE# high to RE# low * @tWP_min: WE# pulse width * @tWW_min: WP# transition to WE# low */struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min;}; /** * struct nand_nvddr_timings - NV-DDR NAND chip timings * * This struct defines the timing requirements of a NV-DDR NAND data interface. * These information can be found in every NAND datasheets and the timings * meaning are described in the ONFI specifications: * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf * (chapter 4.18.2 NV-DDR) * * All these timings are expressed in picoseconds. * * @tBERS_max: Block erase time * @tCCS_min: Change column setup time * @tPROG_max: Page program time * @tR_max: Page read time * @tAC_min: Access window of DQ[7:0] from CLK * @tAC_max: Access window of DQ[7:0] from CLK * @tADL_min: ALE to data loading time * @tCAD_min: Command, Address, Data delay * @tCAH_min: Command/Address DQ hold time * @tCALH_min: W/R_n, CLE and ALE hold time * @tCALS_min: W/R_n, CLE and ALE setup timeLines 1–500 of 1640. Load more
/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> * Steven J. Hill <sjhill@realitydiluted.com> * Thomas Gleixner <tglx@kernel.org> * * Info: * Contains standard defines and IDs for NAND flash devices * * Changelog: * See git changelog. */ #ifndef __LINUX_MTD_RAWNAND_H #define __LINUX_MTD_RAWNAND_H #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/flashchip.h> #include <linux/mtd/bbm.h> #include <linux/mtd/jedec.h> #include <linux/mtd/onfi.h> #include <linux/mutex.h> #include <linux/of.h> #include <linux/types.h> struct nand_chip; struct gpio_desc; /* The maximum number of NAND chips in an array */ #define NAND_MAX_CHIPS 8 /* * Constants for hardware specific CLE/ALE/NCE function * * These are bits which can be or'ed to set/clear multiple * bits in one go. */ /* Select the chip by setting nCE to low */ #define NAND_NCE 0x01 /* Select the command latch by setting CLE to high */ #define NAND_CLE 0x02 /* Select the address latch by setting ALE to high */ #define NAND_ALE 0x04 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) #define NAND_CTRL_CHANGE 0x80 /* * Standard NAND flash commands */ #define NAND_CMD_READ0 0 #define NAND_CMD_READ1 1 #define NAND_CMD_RNDOUT 5 #define NAND_CMD_PAGEPROG 0x10 #define NAND_CMD_READOOB 0x50 #define NAND_CMD_ERASE1 0x60 #define NAND_CMD_STATUS 0x70 #define NAND_CMD_SEQIN 0x80 #define NAND_CMD_RNDIN 0x85 #define NAND_CMD_READID 0x90 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_PARAM 0xec #define NAND_CMD_GET_FEATURES 0xee #define NAND_CMD_SET_FEATURES 0xef #define NAND_CMD_RESET 0xff /* Extended commands for large page devices */ #define NAND_CMD_READSTART 0x30 #define NAND_CMD_READCACHESEQ 0x31 #define NAND_CMD_READCACHEEND 0x3f #define NAND_CMD_RNDOUTSTART 0xE0 #define NAND_CMD_CACHEDPROG 0x15 #define NAND_CMD_NONE -1 /* Status bits */ #define NAND_STATUS_FAIL 0x01 #define NAND_STATUS_FAIL_N1 0x02 #define NAND_STATUS_TRUE_READY 0x20 #define NAND_STATUS_READY 0x40 #define NAND_STATUS_WP 0x80 #define NAND_DATA_IFACE_CHECK_ONLY -1 /* * Constants for Hardware ECC */ /* Reset Hardware ECC for read */ #define NAND_ECC_READ 0 /* Reset Hardware ECC for write */ #define NAND_ECC_WRITE 1 /* Enable Hardware ECC before syndrome is read back from flash */ #define NAND_ECC_READSYN 2 /* * Enable generic NAND 'page erased' check. This check is only done when * ecc.correct() returns -EBADMSG. * Set this flag if your implementation does not fix bitflips in erased * pages and you want to rely on the default implementation. */ #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) /* * Option constants for bizarre disfunctionality and real * features. */ /* Buswidth is 16 bit */ #define NAND_BUSWIDTH_16 BIT(1) /* * When using software implementation of Hamming, we can specify which byte * ordering should be used. */ #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) /* Chip has cache program function */ #define NAND_CACHEPRG BIT(3) /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG /* * Chip requires ready check on read (for auto-incremented sequential read). * True only for small page devices; large page devices do not support * autoincrement. */ #define NAND_NEED_READRDY BIT(8) /* Chip does not allow subpage writes */ #define NAND_NO_SUBPAGE_WRITE BIT(9) /* Device is one of 'new' xD cards that expose fake nand command set */ #define NAND_BROKEN_XD BIT(10) /* Device behaves just like nand, but is readonly */ #define NAND_ROM BIT(11) /* Device supports subpage reads */ #define NAND_SUBPAGE_READ BIT(12) /* Macros to identify the above */ #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) /* * Some MLC NANDs need data scrambling to limit bitflips caused by repeated * patterns. */ #define NAND_NEED_SCRAMBLING BIT(13) /* Device needs 3rd row address cycle */ #define NAND_ROW_ADDR_3 BIT(14) /* Non chip related options */ /* This option skips the bbt scan during initialization. */ #define NAND_SKIP_BBTSCAN BIT(16) /* Chip may not exist, so silence any errors in scan */ #define NAND_SCAN_SILENT_NODEV BIT(18) /* * Autodetect nand buswidth with readid/onfi. * This suppose the driver will configure the hardware in 8 bits mode * when calling nand_scan_ident, and update its configuration * before calling nand_scan_tail. */ #define NAND_BUSWIDTH_AUTO BIT(19) /* * This option could be defined by controller drivers to protect against * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers */ #define NAND_USES_DMA BIT(20) /* * In case your controller is implementing ->legacy.cmd_ctrl() and is relying * on the default ->cmdfunc() implementation, you may want to let the core * handle the tCCS delay which is required when a column change (RNDIN or * RNDOUT) is requested. * If your controller already takes care of this delay, you don't need to set * this flag. */ #define NAND_WAIT_TCCS BIT(21) /* * Whether the NAND chip is a boot medium. Drivers might use this information * to select ECC algorithms supported by the boot ROM or similar restrictions. */ #define NAND_IS_BOOT_MEDIUM BIT(22) /* * Do not try to tweak the timings at runtime. This is needed when the * controller initializes the timings on itself or when it relies on * configuration done by the bootloader. */ #define NAND_KEEP_TIMINGS BIT(23) /* * There are different places where the manufacturer stores the factory bad * block markers. * * Position within the block: Each of these pages needs to be checked for a * bad block marking pattern. */ #define NAND_BBM_FIRSTPAGE BIT(24) #define NAND_BBM_SECONDPAGE BIT(25) #define NAND_BBM_LASTPAGE BIT(26) /* * Some controllers with pipelined ECC engines override the BBM marker with * data or ECC bytes, thus making bad block detection through bad block marker * impossible. Let's flag those chips so the core knows it shouldn't check the * BBM and consider all blocks good. */ #define NAND_NO_BBM_QUIRK BIT(27) /* Cell info constants */ #define NAND_CI_CHIPNR_MSK 0x03 #define NAND_CI_CELLTYPE_MSK 0x0C #define NAND_CI_CELLTYPE_SHIFT 2 /* Position within the OOB data of the page */ #define NAND_BBM_POS_SMALL 5 #define NAND_BBM_POS_LARGE 0 /** * struct nand_parameters - NAND generic parameters from the parameter page * @model: Model name * @supports_set_get_features: The NAND chip supports setting/getting features * @supports_read_cache: The NAND chip supports read cache operations * @set_feature_list: Bitmap of features that can be set * @get_feature_list: Bitmap of features that can be get * @onfi: ONFI specific parameters */ struct nand_parameters { /* Generic parameters */ const char *model; bool supports_set_get_features; bool supports_read_cache; DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); /* ONFI parameters */ struct onfi_params *onfi; }; /* The maximum expected count of bytes in the NAND ID sequence */ #define NAND_MAX_ID_LEN 8 /** * struct nand_id - NAND id structure * @data: buffer containing the id bytes. * @len: ID length. */ struct nand_id { u8 data[NAND_MAX_ID_LEN]; int len; }; /** * struct nand_ecc_step_info - ECC step information of ECC engine * @stepsize: data bytes per ECC step * @strengths: array of supported strengths * @nstrengths: number of supported strengths */ struct nand_ecc_step_info { int stepsize; const int *strengths; int nstrengths; }; /** * struct nand_ecc_caps - capability of ECC engine * @stepinfos: array of ECC step information * @nstepinfos: number of ECC step information * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step */ struct nand_ecc_caps { const struct nand_ecc_step_info *stepinfos; int nstepinfos; int (*calc_ecc_bytes)(int step_size, int strength); }; /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ static const int __name##_strengths[] = { __VA_ARGS__ }; \ static const struct nand_ecc_step_info __name##_stepinfo = { \ .stepsize = __step, \ .strengths = __name##_strengths, \ .nstrengths = ARRAY_SIZE(__name##_strengths), \ }; \ static const struct nand_ecc_caps __name = { \ .stepinfos = &__name##_stepinfo, \ .nstepinfos = 1, \ .calc_ecc_bytes = __calc, \ } /** * struct nand_ecc_ctrl - Control structure for ECC * @engine_type: ECC engine type * @placement: OOB bytes placement * @algo: ECC algorithm * @steps: number of ECC steps per page * @size: data bytes per ECC step * @bytes: ECC bytes per step * @strength: max number of correctible bits per ECC step * @total: total number of ECC bytes per page * @prepad: padding information for syndrome based ECC generators * @postpad: padding information for syndrome based ECC generators * @options: ECC specific options (see NAND_ECC_XXX flags defined above) * @calc_buf: buffer for calculated ECC, size is oobsize. * @code_buf: buffer for ECC read from flash, size is oobsize. * @hwctl: function to control hardware ECC generator. Must only * be provided if an hardware ECC is available * @calculate: function for ECC calculation or readback from ECC hardware * @correct: function for ECC correction, matching to ECC generator (sw/hw). * Should return a positive number representing the number of * corrected bitflips, -EBADMSG if the number of bitflips exceed * ECC strength, or any other error code if the error is not * directly related to correction. * If -EBADMSG is returned the input buffers should be left * untouched. * @read_page_raw: function to read a raw page without ECC. This function * should hide the specific layout used by the ECC * controller and always return contiguous in-band and * out-of-band data even if they're not stored * contiguously on the NAND chip (e.g. * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and * out-of-band data). * @write_page_raw: function to write a raw page without ECC. This function * should hide the specific layout used by the ECC * controller and consider the passed data as contiguous * in-band and out-of-band data. ECC controller is * responsible for doing the appropriate transformations * to adapt to its specific layout (e.g. * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and * out-of-band data). * @read_page: function to read a page according to the ECC generator * requirements; returns maximum number of bitflips corrected in * any single ECC step, -EIO hw error * @read_subpage: function to read parts of the page covered by ECC; * returns same as read_page() * @write_subpage: function to write parts of the page covered by ECC. * @write_page: function to write a page according to the ECC generator * requirements. * @write_oob_raw: function to write chip OOB data without ECC * @read_oob_raw: function to read chip OOB data without ECC * @read_oob: function to read chip OOB data * @write_oob: function to write chip OOB data */ struct nand_ecc_ctrl { enum nand_ecc_engine_type engine_type; enum nand_ecc_placement placement; enum nand_ecc_algo algo; int steps; int size; int bytes; int total; int strength; int prepad; int postpad; unsigned int options; u8 *calc_buf; u8 *code_buf; void (*hwctl)(struct nand_chip *chip, int mode); int (*calculate)(struct nand_chip *chip, const uint8_t *dat, uint8_t *ecc_code); int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*read_page)(struct nand_chip *chip, uint8_t *buf, int oob_required, int page); int (*read_subpage)(struct nand_chip *chip, uint32_t offs, uint32_t len, uint8_t *buf, int page); int (*write_subpage)(struct nand_chip *chip, uint32_t offset, uint32_t data_len, const uint8_t *data_buf, int oob_required, int page); int (*write_page)(struct nand_chip *chip, const uint8_t *buf, int oob_required, int page); int (*write_oob_raw)(struct nand_chip *chip, int page); int (*read_oob_raw)(struct nand_chip *chip, int page); int (*read_oob)(struct nand_chip *chip, int page); int (*write_oob)(struct nand_chip *chip, int page); }; /** * struct nand_sdr_timings - SDR NAND chip timings * * This struct defines the timing requirements of a SDR NAND chip. * These information can be found in every NAND datasheets and the timings * meaning are described in the ONFI specifications: * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf * (chapter 4.15 Timing Parameters) * * All these timings are expressed in picoseconds. * * @tBERS_max: Block erase time * @tCCS_min: Change column setup time * @tPROG_max: Page program time * @tR_max: Page read time * @tALH_min: ALE hold time * @tADL_min: ALE to data loading time * @tALS_min: ALE setup time * @tAR_min: ALE to RE# delay * @tCEA_max: CE# access time * @tCEH_min: CE# high hold time * @tCH_min: CE# hold time * @tCHZ_max: CE# high to output hi-Z * @tCLH_min: CLE hold time * @tCLR_min: CLE to RE# delay * @tCLS_min: CLE setup time * @tCOH_min: CE# high to output hold * @tCS_min: CE# setup time * @tDH_min: Data hold time * @tDS_min: Data setup time * @tFEAT_max: Busy time for Set Features and Get Features * @tIR_min: Output hi-Z to RE# low * @tITC_max: Interface and Timing Mode Change time * @tRC_min: RE# cycle time * @tREA_max: RE# access time * @tREH_min: RE# high hold time * @tRHOH_min: RE# high to output hold * @tRHW_min: RE# high to WE# low * @tRHZ_max: RE# high to output hi-Z * @tRLOH_min: RE# low to output hold * @tRP_min: RE# pulse width * @tRR_min: Ready to RE# low (data only) * @tRST_max: Device reset time, measured from the falling edge of R/B# to the * rising edge of R/B#. * @tWB_max: WE# high to SR[6] low * @tWC_min: WE# cycle time * @tWH_min: WE# high hold time * @tWHR_min: WE# high to RE# low * @tWP_min: WE# pulse width * @tWW_min: WP# transition to WE# low */ struct nand_sdr_timings { u64 tBERS_max; u32 tCCS_min; u64 tPROG_max; u64 tR_max; u32 tALH_min; u32 tADL_min; u32 tALS_min; u32 tAR_min; u32 tCEA_max; u32 tCEH_min; u32 tCH_min; u32 tCHZ_max; u32 tCLH_min; u32 tCLR_min; u32 tCLS_min; u32 tCOH_min; u32 tCS_min; u32 tDH_min; u32 tDS_min; u32 tFEAT_max; u32 tIR_min; u32 tITC_max; u32 tRC_min; u32 tREA_max; u32 tREH_min; u32 tRHOH_min; u32 tRHW_min; u32 tRHZ_max; u32 tRLOH_min; u32 tRP_min; u32 tRR_min; u64 tRST_max; u32 tWB_max; u32 tWC_min; u32 tWH_min; u32 tWHR_min; u32 tWP_min; u32 tWW_min; }; /** * struct nand_nvddr_timings - NV-DDR NAND chip timings * * This struct defines the timing requirements of a NV-DDR NAND data interface. * These information can be found in every NAND datasheets and the timings * meaning are described in the ONFI specifications: * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf * (chapter 4.18.2 NV-DDR) * * All these timings are expressed in picoseconds. * * @tBERS_max: Block erase time * @tCCS_min: Change column setup time * @tPROG_max: Page program time * @tR_max: Page read time * @tAC_min: Access window of DQ[7:0] from CLK * @tAC_max: Access window of DQ[7:0] from CLK * @tADL_min: ALE to data loading time * @tCAD_min: Command, Address, Data delay * @tCAH_min: Command/Address DQ hold time * @tCALH_min: W/R_n, CLE and ALE hold time * @tCALS_min: W/R_n, CLE and ALE setup time