// SPDX-License-Identifier: GPL-2.0-only/* * HD-audio controller helpers */ #include <linux/kernel.h>#include <linux/delay.h>#include <linux/export.h>#include <sound/core.h>#include <sound/hdaudio.h>#include <sound/hda_register.h>#include "local.h" /* clear CORB read pointer properly */static void azx_clear_corbrp(struct hdac_bus *bus){ int timeout; for (timeout = 1000; timeout > 0; timeout--) { if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) break; udelay(1); } if (timeout <= 0) dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", snd_hdac_chip_readw(bus, CORBRP)); snd_hdac_chip_writew(bus, CORBRP, 0); for (timeout = 1000; timeout > 0; timeout--) { if (snd_hdac_chip_readw(bus, CORBRP) == 0) break; udelay(1); } if (timeout <= 0) dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", snd_hdac_chip_readw(bus, CORBRP));} /** * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers * @bus: HD-audio core bus */void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus){ WARN_ON_ONCE(!bus->rb.area); guard(spinlock_irq)(&bus->reg_lock); /* CORB set up */ bus->corb.addr = bus->rb.addr; bus->corb.buf = (__le32 *)bus->rb.area; snd_hdac_chip_writel(bus, CORBLBASE, (u32)(bus->corb.addr + bus->addr_offset)); snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr + bus->addr_offset)); /* set the corb size to 256 entries (ULI requires explicitly) */ snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); /* set the corb write pointer to 0 */ snd_hdac_chip_writew(bus, CORBWP, 0); /* reset the corb hw read pointer */ snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); if (!bus->corbrp_self_clear) azx_clear_corbrp(bus); /* enable corb dma */ if (!bus->use_pio_for_commands) snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); /* RIRB set up */ bus->rirb.addr = bus->rb.addr + 2048; bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); bus->rirb.wp = bus->rirb.rp = 0; memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); snd_hdac_chip_writel(bus, RIRBLBASE, (u32)(bus->rirb.addr + bus->addr_offset)); snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr + bus->addr_offset)); /* set the rirb size to 256 entries (ULI requires explicitly) */ snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); /* reset the rirb hw write pointer */ snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); /* set N=1, get RIRB response interrupt for new entry */ snd_hdac_chip_writew(bus, RINTCNT, 1); /* enable rirb dma and response irq */ if (bus->not_use_interrupts) snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN); else snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); /* Accept unsolicited responses */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);}EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); /* wait for cmd dmas till they are stopped */static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus){ unsigned long timeout; timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) && time_before(jiffies, timeout)) udelay(10); timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) && time_before(jiffies, timeout)) udelay(10);} /** * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers * @bus: HD-audio core bus */void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus){ scoped_guard(spinlock_irq, &bus->reg_lock) { /* disable ringbuffer DMAs */ snd_hdac_chip_writeb(bus, RIRBCTL, 0); snd_hdac_chip_writeb(bus, CORBCTL, 0); } hdac_wait_for_cmd_dmas(bus); guard(spinlock_irq)(&bus->reg_lock); /* disable unsolicited responses */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);}EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); static unsigned int azx_command_addr(u32 cmd){ unsigned int addr = cmd >> 28; if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) addr = 0; return addr;} /* receive an Immediate Response with PIO */static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus, unsigned int addr){ int timeout = 50; while (timeout--) { /* check IRV bit */ if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) { /* reuse rirb.res as the response return value */ bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR); return 0; } udelay(1); } dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n", snd_hdac_chip_readw(bus, IRS)); bus->rirb.res[addr] = -1; return -EIO;} /** * snd_hdac_bus_send_cmd_pio - send a command verb via Immediate Command * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val){ unsigned int addr = azx_command_addr(val); int timeout = 50; guard(spinlock_irq)(&bus->reg_lock); while (timeout--) { /* check ICB bit */ if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) { /* Clear IRV bit */ snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID); snd_hdac_chip_writel(bus, IC, val); /* Set ICB bit */ snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY); return snd_hdac_bus_wait_for_pio_response(bus, addr); } udelay(1); } dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n", snd_hdac_chip_readw(bus, IRS), val); return -EIO;} /** * snd_hdac_bus_get_response_pio - receive a response via Immediate Response * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus, unsigned int addr, unsigned int *res){ if (res) *res = bus->rirb.res[addr]; return 0;} /** * snd_hdac_bus_send_cmd_corb - send a command verb via CORB * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val){ unsigned int addr = azx_command_addr(val); unsigned int wp, rp; guard(spinlock_irq)(&bus->reg_lock); bus->last_cmd[azx_command_addr(val)] = val; /* add command to corb */ wp = snd_hdac_chip_readw(bus, CORBWP); if (wp == 0xffff) { /* something wrong, controller likely turned to D3 */ return -EIO; } wp++; wp %= AZX_MAX_CORB_ENTRIES; rp = snd_hdac_chip_readw(bus, CORBRP); if (wp == rp) { /* oops, it's full */ return -EAGAIN; } bus->rirb.cmds[addr]++; bus->corb.buf[wp] = cpu_to_le32(val); snd_hdac_chip_writew(bus, CORBWP, wp); return 0;} #define AZX_RIRB_EX_UNSOL_EV (1<<4) /** * snd_hdac_bus_update_rirb - retrieve RIRB entries * @bus: HD-audio core bus * * Usually called from interrupt handler. * The caller needs bus->reg_lock spinlock before calling this. */void snd_hdac_bus_update_rirb(struct hdac_bus *bus){ unsigned int rp, wp; unsigned int addr; u32 res, res_ex; wp = snd_hdac_chip_readw(bus, RIRBWP); if (wp == 0xffff) { /* something wrong, controller likely turned to D3 */ return; } if (wp == bus->rirb.wp) return; bus->rirb.wp = wp; while (bus->rirb.rp != wp) { bus->rirb.rp++; bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); res = le32_to_cpu(bus->rirb.buf[rp]); addr = res_ex & 0xf; if (addr >= HDA_MAX_CODECS) { dev_err(bus->dev, "spurious response %#x:%#x, rp = %d, wp = %d", res, res_ex, bus->rirb.rp, wp); snd_BUG(); } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) snd_hdac_bus_queue_event(bus, res, res_ex); else if (bus->rirb.cmds[addr]) { bus->rirb.res[addr] = res; bus->rirb.cmds[addr]--; if (!bus->rirb.cmds[addr] && waitqueue_active(&bus->rirb_wq)) wake_up(&bus->rirb_wq); } else { dev_err_ratelimited(bus->dev, "spurious response %#x:%#x, last cmd=%#08x\n", res, res_ex, bus->last_cmd[addr]); } }}EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); /** * snd_hdac_bus_get_response_rirb - receive a response via RIRB * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus, unsigned int addr, unsigned int *res){ unsigned long timeout; unsigned long loopcounter; wait_queue_entry_t wait; bool warned = false; init_wait_entry(&wait, 0); timeout = jiffies + msecs_to_jiffies(1000); for (loopcounter = 0;; loopcounter++) { scoped_guard(spinlock_irq, &bus->reg_lock) { if (!bus->polling_mode) prepare_to_wait(&bus->rirb_wq, &wait, TASK_UNINTERRUPTIBLE); if (bus->polling_mode) snd_hdac_bus_update_rirb(bus); if (!bus->rirb.cmds[addr]) { if (res) *res = bus->rirb.res[addr]; /* the last value */ if (!bus->polling_mode) finish_wait(&bus->rirb_wq, &wait); return 0; } } if (time_after(jiffies, timeout)) break;#define LOOP_COUNT_MAX 3000 if (!bus->polling_mode) { schedule_timeout(msecs_to_jiffies(2)); } else if (bus->needs_damn_long_delay || loopcounter > LOOP_COUNT_MAX) { if (loopcounter > LOOP_COUNT_MAX && !warned) { dev_dbg_ratelimited(bus->dev, "too slow response, last cmd=%#08x\n", bus->last_cmd[addr]); warned = true; } msleep(2); /* temporary workaround */ } else { udelay(10); cond_resched(); } } if (!bus->polling_mode) finish_wait(&bus->rirb_wq, &wait); return -EIO;} /** * snd_hdac_bus_send_cmd - send a command verb via CORB or PIO * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val){ if (bus->use_pio_for_commands) return snd_hdac_bus_send_cmd_pio(bus, val); return snd_hdac_bus_send_cmd_corb(bus, val);}EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); /** * snd_hdac_bus_get_response - receive a response via RIRB or PIO * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, unsigned int *res){ if (bus->use_pio_for_commands) return snd_hdac_bus_get_response_pio(bus, addr, res); return snd_hdac_bus_get_response_rirb(bus, addr, res);}EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); #define HDAC_MAX_CAPS 10/** * snd_hdac_bus_parse_capabilities - parse capability structure * @bus: the pointer to bus object * * Returns 0 if successful, or a negative error code. */int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus){ unsigned int cur_cap; unsigned int offset; unsigned int counter = 0; offset = snd_hdac_chip_readw(bus, LLCH); /* Lets walk the linked capabilities list */ do { cur_cap = _snd_hdac_chip_readl(bus, offset); dev_dbg(bus->dev, "Capability version: 0x%x\n", (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); if (cur_cap == -1) { dev_dbg(bus->dev, "Invalid capability reg read\n"); break; } switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { case AZX_ML_CAP_ID: dev_dbg(bus->dev, "Found ML capability\n"); bus->mlcap = bus->remap_addr + offset; break; case AZX_GTS_CAP_ID: dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); bus->gtscap = bus->remap_addr + offset; break; case AZX_PP_CAP_ID: /* PP capability found, the Audio DSP is present */ dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); bus->ppcap = bus->remap_addr + offset; break; case AZX_SPB_CAP_ID: /* SPIB capability found, handler function */ dev_dbg(bus->dev, "Found SPB capability\n"); bus->spbcap = bus->remap_addr + offset; break; case AZX_DRSM_CAP_ID: /* DMA resume capability found, handler function */ dev_dbg(bus->dev, "Found DRSM capability\n"); bus->drsmcap = bus->remap_addr + offset; break; default: dev_err(bus->dev, "Unknown capability %d\n", cur_cap); cur_cap = 0; break; } counter++; if (counter > HDAC_MAX_CAPS) { dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); break; } /* read the offset of next capability */ offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; } while (offset); return 0;}EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); /* * Lowlevel interface */ /** * snd_hdac_bus_enter_link_reset - enter link reset * @bus: HD-audio core bus * * Enter to the link reset state. */void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus){ unsigned long timeout; /* reset controller */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && time_before(jiffies, timeout)) usleep_range(500, 1000);Lines 1–500 of 789. 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// SPDX-License-Identifier: GPL-2.0-only /* * HD-audio controller helpers */ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/export.h> #include <sound/core.h> #include <sound/hdaudio.h> #include <sound/hda_register.h> #include "local.h" /* clear CORB read pointer properly */ static void azx_clear_corbrp(struct hdac_bus *bus) { int timeout; for (timeout = 1000; timeout > 0; timeout--) { if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) break; udelay(1); } if (timeout <= 0) dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", snd_hdac_chip_readw(bus, CORBRP)); snd_hdac_chip_writew(bus, CORBRP, 0); for (timeout = 1000; timeout > 0; timeout--) { if (snd_hdac_chip_readw(bus, CORBRP) == 0) break; udelay(1); } if (timeout <= 0) dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", snd_hdac_chip_readw(bus, CORBRP)); } /** * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers * @bus: HD-audio core bus */ void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) { WARN_ON_ONCE(!bus->rb.area); guard(spinlock_irq)(&bus->reg_lock); /* CORB set up */ bus->corb.addr = bus->rb.addr; bus->corb.buf = (__le32 *)bus->rb.area; snd_hdac_chip_writel(bus, CORBLBASE, (u32)(bus->corb.addr + bus->addr_offset)); snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr + bus->addr_offset)); /* set the corb size to 256 entries (ULI requires explicitly) */ snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); /* set the corb write pointer to 0 */ snd_hdac_chip_writew(bus, CORBWP, 0); /* reset the corb hw read pointer */ snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); if (!bus->corbrp_self_clear) azx_clear_corbrp(bus); /* enable corb dma */ if (!bus->use_pio_for_commands) snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); /* RIRB set up */ bus->rirb.addr = bus->rb.addr + 2048; bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); bus->rirb.wp = bus->rirb.rp = 0; memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); snd_hdac_chip_writel(bus, RIRBLBASE, (u32)(bus->rirb.addr + bus->addr_offset)); snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr + bus->addr_offset)); /* set the rirb size to 256 entries (ULI requires explicitly) */ snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); /* reset the rirb hw write pointer */ snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); /* set N=1, get RIRB response interrupt for new entry */ snd_hdac_chip_writew(bus, RINTCNT, 1); /* enable rirb dma and response irq */ if (bus->not_use_interrupts) snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN); else snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); /* Accept unsolicited responses */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); } EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); /* wait for cmd dmas till they are stopped */ static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) { unsigned long timeout; timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) && time_before(jiffies, timeout)) udelay(10); timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) && time_before(jiffies, timeout)) udelay(10); } /** * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers * @bus: HD-audio core bus */ void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) { scoped_guard(spinlock_irq, &bus->reg_lock) { /* disable ringbuffer DMAs */ snd_hdac_chip_writeb(bus, RIRBCTL, 0); snd_hdac_chip_writeb(bus, CORBCTL, 0); } hdac_wait_for_cmd_dmas(bus); guard(spinlock_irq)(&bus->reg_lock); /* disable unsolicited responses */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); } EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); static unsigned int azx_command_addr(u32 cmd) { unsigned int addr = cmd >> 28; if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) addr = 0; return addr; } /* receive an Immediate Response with PIO */ static int snd_hdac_bus_wait_for_pio_response(struct hdac_bus *bus, unsigned int addr) { int timeout = 50; while (timeout--) { /* check IRV bit */ if (snd_hdac_chip_readw(bus, IRS) & AZX_IRS_VALID) { /* reuse rirb.res as the response return value */ bus->rirb.res[addr] = snd_hdac_chip_readl(bus, IR); return 0; } udelay(1); } dev_dbg_ratelimited(bus->dev, "get_response_pio timeout: IRS=%#x\n", snd_hdac_chip_readw(bus, IRS)); bus->rirb.res[addr] = -1; return -EIO; } /** * snd_hdac_bus_send_cmd_pio - send a command verb via Immediate Command * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */ static int snd_hdac_bus_send_cmd_pio(struct hdac_bus *bus, unsigned int val) { unsigned int addr = azx_command_addr(val); int timeout = 50; guard(spinlock_irq)(&bus->reg_lock); while (timeout--) { /* check ICB bit */ if (!((snd_hdac_chip_readw(bus, IRS) & AZX_IRS_BUSY))) { /* Clear IRV bit */ snd_hdac_chip_updatew(bus, IRS, AZX_IRS_VALID, AZX_IRS_VALID); snd_hdac_chip_writel(bus, IC, val); /* Set ICB bit */ snd_hdac_chip_updatew(bus, IRS, AZX_IRS_BUSY, AZX_IRS_BUSY); return snd_hdac_bus_wait_for_pio_response(bus, addr); } udelay(1); } dev_dbg_ratelimited(bus->dev, "send_cmd_pio timeout: IRS=%#x, val=%#x\n", snd_hdac_chip_readw(bus, IRS), val); return -EIO; } /** * snd_hdac_bus_get_response_pio - receive a response via Immediate Response * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */ static int snd_hdac_bus_get_response_pio(struct hdac_bus *bus, unsigned int addr, unsigned int *res) { if (res) *res = bus->rirb.res[addr]; return 0; } /** * snd_hdac_bus_send_cmd_corb - send a command verb via CORB * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */ static int snd_hdac_bus_send_cmd_corb(struct hdac_bus *bus, unsigned int val) { unsigned int addr = azx_command_addr(val); unsigned int wp, rp; guard(spinlock_irq)(&bus->reg_lock); bus->last_cmd[azx_command_addr(val)] = val; /* add command to corb */ wp = snd_hdac_chip_readw(bus, CORBWP); if (wp == 0xffff) { /* something wrong, controller likely turned to D3 */ return -EIO; } wp++; wp %= AZX_MAX_CORB_ENTRIES; rp = snd_hdac_chip_readw(bus, CORBRP); if (wp == rp) { /* oops, it's full */ return -EAGAIN; } bus->rirb.cmds[addr]++; bus->corb.buf[wp] = cpu_to_le32(val); snd_hdac_chip_writew(bus, CORBWP, wp); return 0; } #define AZX_RIRB_EX_UNSOL_EV (1<<4) /** * snd_hdac_bus_update_rirb - retrieve RIRB entries * @bus: HD-audio core bus * * Usually called from interrupt handler. * The caller needs bus->reg_lock spinlock before calling this. */ void snd_hdac_bus_update_rirb(struct hdac_bus *bus) { unsigned int rp, wp; unsigned int addr; u32 res, res_ex; wp = snd_hdac_chip_readw(bus, RIRBWP); if (wp == 0xffff) { /* something wrong, controller likely turned to D3 */ return; } if (wp == bus->rirb.wp) return; bus->rirb.wp = wp; while (bus->rirb.rp != wp) { bus->rirb.rp++; bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); res = le32_to_cpu(bus->rirb.buf[rp]); addr = res_ex & 0xf; if (addr >= HDA_MAX_CODECS) { dev_err(bus->dev, "spurious response %#x:%#x, rp = %d, wp = %d", res, res_ex, bus->rirb.rp, wp); snd_BUG(); } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) snd_hdac_bus_queue_event(bus, res, res_ex); else if (bus->rirb.cmds[addr]) { bus->rirb.res[addr] = res; bus->rirb.cmds[addr]--; if (!bus->rirb.cmds[addr] && waitqueue_active(&bus->rirb_wq)) wake_up(&bus->rirb_wq); } else { dev_err_ratelimited(bus->dev, "spurious response %#x:%#x, last cmd=%#08x\n", res, res_ex, bus->last_cmd[addr]); } } } EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); /** * snd_hdac_bus_get_response_rirb - receive a response via RIRB * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */ static int snd_hdac_bus_get_response_rirb(struct hdac_bus *bus, unsigned int addr, unsigned int *res) { unsigned long timeout; unsigned long loopcounter; wait_queue_entry_t wait; bool warned = false; init_wait_entry(&wait, 0); timeout = jiffies + msecs_to_jiffies(1000); for (loopcounter = 0;; loopcounter++) { scoped_guard(spinlock_irq, &bus->reg_lock) { if (!bus->polling_mode) prepare_to_wait(&bus->rirb_wq, &wait, TASK_UNINTERRUPTIBLE); if (bus->polling_mode) snd_hdac_bus_update_rirb(bus); if (!bus->rirb.cmds[addr]) { if (res) *res = bus->rirb.res[addr]; /* the last value */ if (!bus->polling_mode) finish_wait(&bus->rirb_wq, &wait); return 0; } } if (time_after(jiffies, timeout)) break; #define LOOP_COUNT_MAX 3000 if (!bus->polling_mode) { schedule_timeout(msecs_to_jiffies(2)); } else if (bus->needs_damn_long_delay || loopcounter > LOOP_COUNT_MAX) { if (loopcounter > LOOP_COUNT_MAX && !warned) { dev_dbg_ratelimited(bus->dev, "too slow response, last cmd=%#08x\n", bus->last_cmd[addr]); warned = true; } msleep(2); /* temporary workaround */ } else { udelay(10); cond_resched(); } } if (!bus->polling_mode) finish_wait(&bus->rirb_wq, &wait); return -EIO; } /** * snd_hdac_bus_send_cmd - send a command verb via CORB or PIO * @bus: HD-audio core bus * @val: encoded verb value to send * * Returns zero for success or a negative error code. */ int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) { if (bus->use_pio_for_commands) return snd_hdac_bus_send_cmd_pio(bus, val); return snd_hdac_bus_send_cmd_corb(bus, val); } EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); /** * snd_hdac_bus_get_response - receive a response via RIRB or PIO * @bus: HD-audio core bus * @addr: codec address * @res: pointer to store the value, NULL when not needed * * Returns zero if a value is read, or a negative error code. */ int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, unsigned int *res) { if (bus->use_pio_for_commands) return snd_hdac_bus_get_response_pio(bus, addr, res); return snd_hdac_bus_get_response_rirb(bus, addr, res); } EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); #define HDAC_MAX_CAPS 10 /** * snd_hdac_bus_parse_capabilities - parse capability structure * @bus: the pointer to bus object * * Returns 0 if successful, or a negative error code. */ int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) { unsigned int cur_cap; unsigned int offset; unsigned int counter = 0; offset = snd_hdac_chip_readw(bus, LLCH); /* Lets walk the linked capabilities list */ do { cur_cap = _snd_hdac_chip_readl(bus, offset); dev_dbg(bus->dev, "Capability version: 0x%x\n", (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); if (cur_cap == -1) { dev_dbg(bus->dev, "Invalid capability reg read\n"); break; } switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { case AZX_ML_CAP_ID: dev_dbg(bus->dev, "Found ML capability\n"); bus->mlcap = bus->remap_addr + offset; break; case AZX_GTS_CAP_ID: dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); bus->gtscap = bus->remap_addr + offset; break; case AZX_PP_CAP_ID: /* PP capability found, the Audio DSP is present */ dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); bus->ppcap = bus->remap_addr + offset; break; case AZX_SPB_CAP_ID: /* SPIB capability found, handler function */ dev_dbg(bus->dev, "Found SPB capability\n"); bus->spbcap = bus->remap_addr + offset; break; case AZX_DRSM_CAP_ID: /* DMA resume capability found, handler function */ dev_dbg(bus->dev, "Found DRSM capability\n"); bus->drsmcap = bus->remap_addr + offset; break; default: dev_err(bus->dev, "Unknown capability %d\n", cur_cap); cur_cap = 0; break; } counter++; if (counter > HDAC_MAX_CAPS) { dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); break; } /* read the offset of next capability */ offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; } while (offset); return 0; } EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); /* * Lowlevel interface */ /** * snd_hdac_bus_enter_link_reset - enter link reset * @bus: HD-audio core bus * * Enter to the link reset state. */ void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) { unsigned long timeout; /* reset controller */ snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); timeout = jiffies + msecs_to_jiffies(100); while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && time_before(jiffies, timeout)) usleep_range(500, 1000);