// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)//// Copyright(c) 2022 Intel Corporation//// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>// /* * Hardware interface for audio DSP on Meteorlake. */ #include <linux/debugfs.h>#include <linux/firmware.h>#include <linux/string_choices.h>#include <sound/sof/ipc4/header.h>#include <trace/events/sof_intel.h>#include "../ipc4-priv.h"#include "../ops.h"#include "hda.h"#include "hda-ipc.h"#include "../sof-audio.h"#include "mtl.h"#include "telemetry.h" static const struct snd_sof_debugfs_map mtl_dsp_debugfs[] = {	{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},	{"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},	{"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},	{"fw_regs", HDA_DSP_BAR,  MTL_SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},}; static void mtl_ipc_host_done(struct snd_sof_dev *sdev){	/*	 * clear busy interrupt to tell dsp controller this interrupt has been accepted,	 * not trigger it again	 */	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDR,				       MTL_DSP_REG_HFIPCXTDR_BUSY, MTL_DSP_REG_HFIPCXTDR_BUSY);	/*	 * clear busy bit to ack dsp the msg has been processed and send reply msg to dsp	 */	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXTDA,				       MTL_DSP_REG_HFIPCXTDA_BUSY, 0);} static void mtl_ipc_dsp_done(struct snd_sof_dev *sdev){	/*	 * set DONE bit - tell DSP we have received the reply msg from DSP, and processed it,	 * don't send more reply to host	 */	snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDA,				       MTL_DSP_REG_HFIPCXIDA_DONE, MTL_DSP_REG_HFIPCXIDA_DONE); 	/* unmask Done interrupt */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXCTL,				MTL_DSP_REG_HFIPCXCTL_DONE, MTL_DSP_REG_HFIPCXCTL_DONE);} /* Check if an IPC IRQ occurred */bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev){	u32 irq_status;	u32 hfintipptr; 	if (sdev->dspless_mode_selected)		return false; 	/* read Interrupt IP Pointer */	hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;	irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 	trace_sof_intel_hda_irq_ipc_check(sdev, irq_status); 	if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_IPC))		return true; 	return false;}EXPORT_SYMBOL_NS(mtl_dsp_check_ipc_irq, "SND_SOC_SOF_INTEL_MTL"); /* Check if an SDW IRQ occurred */static bool mtl_dsp_check_sdw_irq(struct snd_sof_dev *sdev){	u32 irq_status;	u32 hfintipptr; 	/* read Interrupt IP Pointer */	hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK;	irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, hfintipptr + MTL_DSP_IRQSTS); 	if (irq_status != U32_MAX && (irq_status & MTL_DSP_IRQSTS_SDW))		return true; 	return false;} static int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg){	struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;	struct sof_ipc4_msg *msg_data = msg->msg_data; 	if (hda_ipc4_tx_is_busy(sdev)) {		hdev->delayed_ipc_tx_msg = msg;		return 0;	} 	hdev->delayed_ipc_tx_msg = NULL; 	/* send the message via mailbox */	if (msg_data->data_size)		sof_mailbox_write(sdev, sdev->host_box.offset, msg_data->data_ptr,				  msg_data->data_size); 	snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDDY,			  msg_data->extension);	snd_sof_dsp_write(sdev, HDA_DSP_BAR, MTL_DSP_REG_HFIPCXIDR,			  msg_data->primary | MTL_DSP_REG_HFIPCXIDR_BUSY); 	hda_dsp_ipc4_schedule_d0i3_work(hdev, msg); 	return 0;} void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev){	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;	const struct sof_intel_dsp_desc *chip = hda->desc; 	if (sdev->dspless_mode_selected)		return; 	/* enable IPC DONE and BUSY interrupts */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,				MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE,				MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE);} void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev){	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;	const struct sof_intel_dsp_desc *chip = hda->desc; 	if (sdev->dspless_mode_selected)		return; 	/* disable IPC DONE and BUSY interrupts */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,				MTL_DSP_REG_HFIPCXCTL_BUSY | MTL_DSP_REG_HFIPCXCTL_DONE, 0);}EXPORT_SYMBOL_NS(mtl_disable_ipc_interrupts, "SND_SOC_SOF_INTEL_MTL"); static void mtl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable){	u32 hipcie;	u32 mask;	u32 val;	int ret; 	if (sdev->dspless_mode_selected)		return; 	/* Enable/Disable SoundWire interrupt */	mask = MTL_DSP_REG_HfSNDWIE_IE_MASK;	if (enable)		val = mask;	else		val = 0; 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, mask, val); 	/* check if operation was successful */	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfSNDWIE, hipcie,					    (hipcie & mask) == val,					    HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0)		dev_err(sdev->dev, "failed to set SoundWire IPC interrupt %s\n",			str_enable_disable(enable));} int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable){	u32 hfintipptr;	u32 irqinten;	u32 hipcie;	u32 mask;	u32 val;	int ret; 	if (sdev->dspless_mode_selected)		return 0; 	/* read Interrupt IP Pointer */	hfintipptr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFINTIPPTR) & MTL_HFINTIPPTR_PTR_MASK; 	/* Enable/Disable Host IPC and SOUNDWIRE */	mask = MTL_IRQ_INTEN_L_HOST_IPC_MASK | MTL_IRQ_INTEN_L_SOUNDWIRE_MASK;	if (enable)		val = mask;	else		val = 0; 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, hfintipptr, mask, val); 	/* check if operation was successful */	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, hfintipptr, irqinten,					    (irqinten & mask) == val,					    HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0) {		dev_err(sdev->dev, "failed to %s Host IPC and/or SOUNDWIRE\n",			str_enable_disable(enable));		return ret;	} 	/* Enable/Disable Host IPC interrupt*/	mask = MTL_DSP_REG_HfHIPCIE_IE_MASK;	if (enable)		val = mask;	else		val = 0; 	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, mask, val); 	/* check if operation was successful */	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP_REG_HfHIPCIE, hipcie,					    (hipcie & mask) == val,					    HDA_DSP_REG_POLL_INTERVAL_US, HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0) {		dev_err(sdev->dev, "failed to set Host IPC interrupt %s\n",			str_enable_disable(enable));		return ret;	} 	return ret;}EXPORT_SYMBOL_NS(mtl_enable_interrupts, "SND_SOC_SOF_INTEL_MTL"); static bool mtl_dsp_is_enabled(struct snd_sof_dev *sdev){	int val; 	val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);	if (val & MTL_HFDSSCS_CPA_MASK)		return true; 	return false;} /* pre fw run operations */static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev){	struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;	u32 dsphfpwrsts;	u32 dsphfdsscs;	u32 cpa;	u32 pgs;	int ret;	u32 dsppwrctl;	u32 dsppwrsts;	const struct sof_intel_dsp_desc *chip; 	/* Power down the DSP if it is left enabled to ensure clean boot state */	if (mtl_dsp_is_enabled(sdev)) {		dev_dbg(sdev->dev, "powering down DSP first\n"); 		ret = mtl_power_down_dsp(sdev);		if (ret < 0) {			dev_warn(sdev->dev,				 "%s: failed to power down already-enabled DSP\n", __func__);			/* Continue anyway to attempt recovery */		}	} 	chip = get_chip_info(sdev->pdata);	if (chip->hw_ip_version > SOF_INTEL_ACE_2_0) {		dsppwrctl = PTL_HFPWRCTL2;		dsppwrsts = PTL_HFPWRSTS2;	} else {		dsppwrctl = MTL_HFPWRCTL;		dsppwrsts = MTL_HFPWRSTS;	} 	/* Set the DSP subsystem power on */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,				MTL_HFDSSCS_SPA_MASK, MTL_HFDSSCS_SPA_MASK); 	/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */	usleep_range(1000, 1010); 	/* poll with timeout to check if operation successful */	cpa = MTL_HFDSSCS_CPA_MASK;	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,					    (dsphfdsscs & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,					    HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0) {		dev_err(sdev->dev, "failed to enable DSP subsystem\n");		return ret;	} 	/* Power up gated-DSP-0 domain in order to access the DSP shim register block. */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, dsppwrctl,				MTL_HFPWRCTL_WPDSPHPXPG, MTL_HFPWRCTL_WPDSPHPXPG); 	usleep_range(1000, 1010); 	/* poll with timeout to check if operation successful */	pgs = MTL_HFPWRSTS_DSPHPXPGS_MASK;	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, dsppwrsts, dsphfpwrsts,					    (dsphfpwrsts & pgs) == pgs,					    HDA_DSP_REG_POLL_INTERVAL_US,					    HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0)		dev_err(sdev->dev, "failed to power up gated DSP domain\n"); 	/* if SoundWire is used, make sure it is not power-gated */	if (hdev->info.handle && hdev->info.link_mask > 0)		snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL,					MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); 	return ret;} static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev){	int ret; 	if (sdev->first_boot) {		struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 		ret = hda_sdw_startup(sdev);		if (ret < 0) {			dev_err(sdev->dev, "could not startup SoundWire links\n");			return ret;		} 		/* Check if IMR boot is usable */		if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT)) {			hdev->imrboot_supported = true;			debugfs_create_bool("skip_imr_boot",					    0644, sdev->debugfs_root,					    &hdev->skip_imr_boot);		}	} 	hda_sdw_int_enable(sdev, true);	return 0;} static void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags){	char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;	u32 fwsts;	u32 fwlec; 	hda_dsp_get_state(sdev, level);	fwsts = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_STS);	fwlec = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP_ROM_ERROR); 	if (fwsts != 0xffffffff)		dev_err(sdev->dev, "Firmware state: %#x, status/error code: %#x\n",			fwsts, fwlec); 	sof_ipc4_intel_dump_telemetry_state(sdev, flags);} static bool mtl_dsp_primary_core_is_enabled(struct snd_sof_dev *sdev){	int val; 	val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE);	if (val != U32_MAX && val & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK)		return true; 	return false;} static int mtl_dsp_core_power_up(struct snd_sof_dev *sdev, int core){	unsigned int cpa;	u32 dspcxctl;	int ret; 	/* Only the primary core can be powered up by the host */	if (core != SOF_DSP_PRIMARY_CORE || mtl_dsp_primary_core_is_enabled(sdev))		return 0; 	/* Program the owner of the IP & shim registers (10: Host CPU) */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,				MTL_DSP2CXCTL_PRIMARY_CORE_OSEL,				0x2 << MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT); 	/* enable SPA bit */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,				MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK,				MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK); 	/* Wait for unstable CPA read (1 then 0 then 1) just after setting SPA bit */	usleep_range(1000, 1010); 	/* poll with timeout to check if operation successful */	cpa = MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK;	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,					    (dspcxctl & cpa) == cpa, HDA_DSP_REG_POLL_INTERVAL_US,					    HDA_DSP_RESET_TIMEOUT_US);	if (ret < 0) {		dev_err(sdev->dev, "%s: timeout on MTL_DSP2CXCTL_PRIMARY_CORE read\n",			__func__);		return ret;	} 	/* set primary core mask and refcount to 1 */	sdev->enabled_cores_mask = BIT(SOF_DSP_PRIMARY_CORE);	sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 1; 	return 0;} static int mtl_dsp_core_power_down(struct snd_sof_dev *sdev, int core){	u32 dspcxctl;	int ret; 	/* Only the primary core can be powered down by the host */	if (core != SOF_DSP_PRIMARY_CORE || !mtl_dsp_primary_core_is_enabled(sdev))		return 0; 	/* disable SPA bit */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE,				MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK, 0); 	/* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */	usleep_range(1000, 1010); 	ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_DSP2CXCTL_PRIMARY_CORE, dspcxctl,					    !(dspcxctl & MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK),					    HDA_DSP_REG_POLL_INTERVAL_US,					    HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);	if (ret < 0) {		dev_err(sdev->dev, "failed to power down primary core\n");		return ret;	} 	sdev->enabled_cores_mask = 0;	sdev->dsp_core_ref_count[SOF_DSP_PRIMARY_CORE] = 0; 	return 0;} int mtl_power_down_dsp(struct snd_sof_dev *sdev){	u32 dsphfdsscs, cpa;	int ret; 	/* first power down core */	ret = mtl_dsp_core_power_down(sdev, SOF_DSP_PRIMARY_CORE);	if (ret) {		dev_err(sdev->dev, "mtl dsp power down error, %d\n", ret);		return ret;	} 	/* Set the DSP subsystem power down */	snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFDSSCS,				MTL_HFDSSCS_SPA_MASK, 0); 	/* Wait for unstable CPA read (0 then 1 then 0) just after setting SPA bit */	usleep_range(1000, 1010); 	/* poll with timeout to check if operation successful */	cpa = MTL_HFDSSCS_CPA_MASK;	dsphfdsscs = snd_sof_dsp_read(sdev, HDA_DSP_BAR, MTL_HFDSSCS);	return snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, MTL_HFDSSCS, dsphfdsscs,					     (dsphfdsscs & cpa) == 0, HDA_DSP_REG_POLL_INTERVAL_US,					     HDA_DSP_RESET_TIMEOUT_US);}EXPORT_SYMBOL_NS(mtl_power_down_dsp, "SND_SOC_SOF_INTEL_MTL"); int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot){	struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;	const struct sof_intel_dsp_desc *chip = hda->desc;	unsigned int status, target_status;	u32 ipc_hdr, flags;	char *dump_msg;	int ret; 	/* step 1: purge FW request */	ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;	if (!imr_boot)		ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); 	snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); 	/* step 2: power up primary core */	ret = mtl_dsp_core_power_up(sdev, SOF_DSP_PRIMARY_CORE);	if (ret < 0) {		if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)			dev_err(sdev->dev, "dsp core 0/1 power up failed\n");		goto err;	}

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